CN110350880A - A kind of Novel ultra wide band operational amplifier - Google Patents
A kind of Novel ultra wide band operational amplifier Download PDFInfo
- Publication number
- CN110350880A CN110350880A CN201910576998.2A CN201910576998A CN110350880A CN 110350880 A CN110350880 A CN 110350880A CN 201910576998 A CN201910576998 A CN 201910576998A CN 110350880 A CN110350880 A CN 110350880A
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- pmos tube
- tube
- grid
- connect
- nmos tube
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/26—Push-pull amplifiers; Phase-splitters therefor
- H03F3/265—Push-pull amplifiers; Phase-splitters therefor with field-effect transistors only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45932—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by using feedback means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
Abstract
The invention belongs to integrated circuit fields, and in particular to a kind of Novel ultra wide band operational amplifier, comprising: differential signal outputs recommend inverting amplifier and bootstrapping gain amplifier；Inverting amplifier is recommended to connect with differential input end；Bootstrapping gain amplifier is connect with the output end for recommending inverting amplifier.The present invention using differential input end, recommend inverting amplifier, bootstrapping gain amplifier, traditional Differential Input can inhibit the influence of common-mode noise, recommending inverting amplifier may be implemented Full-swing output, the higher input amplitude of oscillation is provided for next stage, and there are also with roomy advantage for the structure, composition two stage amplifer is easier to keep time pole and dominant pole separate, can maximumlly utilize bandwidth to avoid the use of compensation circuit；Bootstrapping gain amplifier used herein extends the bandwidth of amplifier, reduces power consumption, reduce biasing circuit, save chip area.
Description
Technical field
The invention belongs to integrated circuit fields, and in particular to a kind of Novel ultra wide band operational amplifier.
Background technique
Operational amplifier is the key modules of high-speed high-precision flow line analog-digital converter, as analog-digital converter samples frequency
Rate gradually rises, and proposes increasingly higher demands to the bandwidth of amplifier.With the development of integrated circuit technology, characteristic size is not
Disconnected reduce plays very positive effect to the bandwidth of extension amplifier, but the reduction of brought gain is just needed using two-stage
The measures such as amplification solve.However traditional two-stage amplifying circuit can bring the deterioration of frequency characteristic, cause to must be added to compensation
To make, amplifier reaches stable to capacitor while this also reduces the bandwidth of amplifier.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of Novel ultra wide band operation amplifiers
Device.The technical problem to be solved in the present invention is achieved through the following technical solutions:
A kind of Novel ultra wide band operational amplifier, comprising: differential signal outputs recommend inverting amplifier and bootstrapping gain
Amplifier；
The input terminal for recommending inverting amplifier is connect with the differential signal outputs；The bootstrapping gain amplifier
Input terminal connect with the output end for recommending inverting amplifier.
In one embodiment of the invention, the inverting amplifier of recommending includes the first common mode feedback circuit VFB1, the
One power end VDD1, PMOS tube PM0, PMOS tube PM1, PMOS tube PM2, NMOS tube NM0 and NMOS tube NM1；
The grid of the PMOS tube PM1 is connect with the grid of the NMOS tube NM0, the grid of the PMOS tube PM1 and institute
The grid for stating NMOS tube NM0 is all connected with the differential signal outputs, the drain electrode of the PMOS tube PM1 and the NMOS tube NM0
Drain electrode connection intersection point be used as the first difference output end VOUT_1 for recommending inverting amplifier, the source electrode of the NMOS tube NM0 and
The source grounding GND of the NMOS tube NM1, the source electrode of the PMOS tube PM1 are connect with the source electrode of the PMOS tube PM2, institute
The source electrode of the source electrode and the PMOS tube PM2 of stating PMOS tube PM1 is all connected with the drain electrode of the PMOS tube PM0, the PMOS tube PM0
Source electrode connect the first power end VDD, the grid of the PMOS tube PM0 is defeated with the first common mode feedback circuit VFB1's
Outlet connection；The drain electrode of the PMOS tube PM2 is connect with the drain electrode of the NMOS tube NM1, and the drain electrode of the PMOS tube PM2
The second difference output end VOUT_2 of inverting amplifier, institute are recommended as described in the drain electrode connection intersection point of the NMOS tube NM1
The grid for stating PMOS tube PM2 is connect with the grid of the NMOS tube NM1, and the grid of the PMOS tube PM2 and the NMOS
The grid of pipe NM1 is all connected with the differential signal outputs；The first differential input end of the first common mode feedback circuit VFB1
Connect with the first difference output end VOUT_1, the second differential input end of the first common mode feedback circuit VFB1 with it is described
Second difference output end VOUT_2 connection.
In one embodiment of the invention, the bootstrapping gain amplifier includes: second source end VDD2, the second common mode
Feed circuit VFB2, bias voltage output VB, auxiliary OP AMP INVP, auxiliary OP AMP INVN, PMOS tube PM3, PMOS tube PM4,
PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5；
The grid of the PMOS tube PM7 is connect with the output end of the second common mode feedback circuit VFB2, the PMOS tube
The source electrode of PM7 is connect with the second source end VDD2, and the drain electrode of the PMOS tube PM7 is separately connected the PMOS tube PM5's
The source electrode of source electrode and the PMOS tube PM6；
The source electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM6, the grid of the PMOS tube PM5 and institute
Bias voltage output VB connection is stated, the drain electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM3, the PMOS
The drain electrode of pipe PM5 is also connect with the input terminal INVP_IN+ of the auxiliary OP AMP INVP；The grid of the PMOS tube PM3 with it is described
The output end INVP_OUT+ connection of auxiliary OP AMP INVP, the drain electrode of the PMOS tube PM3 connect with the drain electrode of the NMOS tube NM4
It connects, and the drain electrode of the PMOS tube PM3 connect intersection point with the drain electrode of the NMOS tube NM4 as the bootstrapping gain amplifier
The first difference output end VOUT1；The output end INVN_OUT+ of the grid of the NMOS tube NM4 and the auxiliary OP AMP INVN
Connection, the source electrode of the NMOS tube NM4 connect with the drain electrode of the NMOS tube NM2, the source electrode of the NMOS tube NM4 also with it is described
The input terminal INVN_IN connection of auxiliary OP AMP INVN；The grid of the NMOS tube NM2 and described recommend the of reverse phase amplification appliance
One difference output end VOUT_1 connection, the source grounding GND of the source electrode of the NMOS tube NM2 and the NMOS tube NM3；
The grid of the PMOS tube PM6 is connect with the bias voltage output VB, the drain electrode of the PMOS tube PM6 and institute
The source electrode connection of PMOS tube PM4 is stated, the drain electrode of the PMOS tube PM6 connects with the input terminal INVP_IN- of the auxiliary OP AMP INVP
It connects, the output end INVP_OUT- of the output end INVP of the grid and auxiliary OP AMP of the PMOS tube PM4 is connect, described
The drain electrode of PMOS tube PM4 is connect with the drain electrode of the NMOS tube NM5, and the drain electrode of the PMOS tube PM4 is with the NMOS tube NM5's
Second difference output end VOUT2 of the drain electrode connection intersection point as the bootstrapping gain amplifier；The grid of the NMOS tube NM5 with
The output end INVN_OUT- connection of the auxiliary OP AMP INVN, the leakage of the source electrode of the NMOS tube NM5 and the NMOS tube NM3
Pole connection, the source electrode of the NMOS tube NM5 are connect with the input terminal INVN_IN- of the auxiliary OP AMP INVN；The NMOS tube
The grid of NM3 is connect with the second difference output end VOUT_2 for recommending inverting amplifier；
The first differential input end of the second common mode feedback circuit VFB2 and the bootstrapping gain amplifier it is first poor
Divide output end VOUT1 connection, the second differential input end of the second common mode feedback circuit VFB2 and the bootstrapping gain are amplified
Second difference output end VOUT2 connection of device.
In one embodiment of the invention, the auxiliary OP AMP INVN includes PMOS tube PM8, PMOS tube PM9, NMOS tube
NM6, NMOS tube NM7；
The PMOS tube PM8 source electrode is connect with the source electrode of the PMOS tube PM9, the source electrode of the PMOS tube PM8 with it is described
The source electrode of PMOS tube PM9 is connect with the first power end VDD1；The grid of the PMOS tube PM8 and the NMOS tube NM6
Grid connection, and the grid of PMOS tube PM8 connect intersection point with the NMOS tube NM6 grid as the auxiliary OP AMP INVN
The drain electrode of input terminal INVN_IN+, the PMOS tube PM8 connect with the drain electrode of the NMOS tube NM6, and the PMOS tube
The drain electrode of PM8 connects output end INVN_OUT+ of the intersection point as the auxiliary OP AMP INVN with the drain electrode of the NMOS tube NM6；
The grid of the PMOS tube PM9 is connect with the grid of the NMOS tube NM7, and the grid of PMOS tube PM8 and institute
State input terminal INVN_IN- of the NMOS tube NM6 grid connection intersection point as the auxiliary OP AMP INVN, the leakage of the PMOS tube PM9
Pole is connect with the drain electrode of the NMOS tube NM7, and the drain electrode of the PMOS tube PM9 connect intersection point with the drain electrode of the NMOS tube NM7
Output end INVN_OUT- as the auxiliary OP AMP INVN.
In one embodiment of the invention, the auxiliary OP AMP INVP includes PMOS tube PM10, PMOS tube PM11, NMOS
Pipe NM8, NMOS tube NM9；
The source electrode of the PMOS tube PM10 is connect with the second source end VDD2 with the source electrode of the PMOS tube PM11；
The grid of PMOS tube PM10 is connect with the grid of the NMOS tube NM8, and the grid of the PMOS tube PM10 and the NMOS
Input terminal INVP_IN+ of the grid connection intersection point of pipe NM8 as auxiliary OP AMP INVP；The drain electrode of the PMOS tube PM10 and institute
The drain electrode connection of NMOS tube NM8 is stated, and the drain electrode of the PMOS tube PM10 connect intersection point work with the drain electrode of the NMOS tube NM8
For the output end INVP_OUT+ of auxiliary OP AMP INVP, the source electrode of the source electrode of the NMOS tube NM8 and the NMOS tube NM9 with
The first power end VDD1；
The grid of the PMOS tube PM11 is connect with the grid of the NMOS tube NM9, and the grid of the PMOS tube PM11
Pole connect input terminal INVP_IN- of the intersection point as auxiliary OP AMP INVP with the grid of the NMOS tube NM9；The PMOS tube
The drain electrode of PM11 is connect with the drain electrode of the NMOS tube NM9, and the drain electrode of the PMOS tube PM11 is with the NMOS tube NM9's
Output end INVP_OUT- of the drain electrode connection intersection point as auxiliary OP AMP INVP.
In one embodiment of the invention, the bootstrapping gain amplifier further include first resistor R1, second resistance R2,
First capacitor C1, the second capacitor C2；
The grid of the PMOS tube PM5 is connect by first resistor R1 with the bias voltage output VB；The NMOS
The grid of pipe NM2 passes sequentially through first capacitor C1, first resistor R1 and connect with the bias voltage output VB；
The grid of the PMOS tube PM6 is connect by second resistance R2 with the bias voltage output VB；The NMOS
The grid of pipe NM3 passes sequentially through the second capacitor C2, second resistance R2 and connect with the bias voltage output VB.
Beneficial effects of the present invention:
The application includes differential input end, recommends inverting amplifier and bootstrapping gain amplifier, and Differential Input can inhibit
The influence of common-mode noise；Recommending inverting amplifier may be implemented Full-swing output, provide the higher input amplitude of oscillation for next stage, and
And the structure forms two stage amplifer and is easier to keep time pole and dominant pole separate there are also with roomy advantage, it can be to avoid compensation
The use of circuit maximumlly utilizes bandwidth；The bandwidth for extending amplifier, drop of bootstrapping gain amplifier used by the application
Low power consumption reduces biasing circuit, saves chip area.
The present invention is described in further details below with reference to accompanying drawings and embodiments.
Detailed description of the invention
Fig. 1 is a kind of structural block diagram of Novel ultra wide band operational amplifier provided in an embodiment of the present invention；
Fig. 2 is a kind of another bootstrapping gain of the circuit of Novel ultra wide band operational amplifier provided in an embodiment of the present invention
Amplifier circuit figure；
Fig. 3 is a kind of auxiliary OP AMP INVN circuit diagram of Novel ultra wide band operational amplifier provided in an embodiment of the present invention；
Fig. 4 is a kind of auxiliary OP AMP INVP circuit diagram of Novel ultra wide band operational amplifier provided in an embodiment of the present invention；
Fig. 5 is a kind of bootstrapping gain amplifier circuit of Novel ultra wide band operational amplifier provided in an embodiment of the present invention
Figure；
Fig. 6 is a kind of circuit diagram of Novel ultra wide band operational amplifier provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Referring to Figure 1, Fig. 1 is a kind of structural block diagram of Novel ultra wide band operational amplifier provided in an embodiment of the present invention,
Include: differential signal outputs, recommend inverting amplifier and bootstrapping gain amplifier；
The input terminal for recommending inverting amplifier is connect with the differential signal outputs；The bootstrapping gain amplifier
Input terminal connect with the output end for recommending inverting amplifier.
In one embodiment of the invention, the inverting amplifier of recommending includes the first common mode feedback circuit VFB1, the
One power end VDD1, PMOS tube PM0, PMOS tube PM1, PMOS tube PM2, NMOS tube NM0 and NMOS tube NM1；
The grid of the PMOS tube PM1 is connect with the grid of the NMOS tube NM0, the grid of the PMOS tube PM1 and institute
The grid for stating NMOS tube NM0 is all connected with the differential signal outputs, the drain electrode of the PMOS tube PM1 and the NMOS tube NM0
Drain electrode connection intersection point be used as the first difference output end VOUT_1 for recommending inverting amplifier, the source electrode of the NMOS tube NM0 and
The source grounding GND of the NMOS tube NM1, the source electrode of the PMOS tube PM1 are connect with the source electrode of the PMOS tube PM2, institute
The source electrode of the source electrode and the PMOS tube PM2 of stating PMOS tube PM1 is all connected with the drain electrode of the PMOS tube PM0, the PMOS tube PM0
Source electrode connect the first power end VDD, the grid of the PMOS tube PM0 is defeated with the first common mode feedback circuit VFB1's
Outlet connection；The drain electrode of the PMOS tube PM2 is connect with the drain electrode of the NMOS tube NM1, and the drain electrode of the PMOS tube PM2
The second difference output end VOUT_2 of inverting amplifier, institute are recommended as described in the drain electrode connection intersection point of the NMOS tube NM1
The grid for stating PMOS tube PM2 is connect with the grid of the NMOS tube NM1, and the grid of the PMOS tube PM2 and the NMOS
The grid of pipe NM1 is all connected with the differential signal outputs；The first differential input end of the first common mode feedback circuit VFB1
Connect with the first difference output end VOUT_1, the second differential input end of the first common mode feedback circuit VFB1 with it is described
Second difference output end VOUT_2 connection.
Further, differential signal outputs include the first differential signal outputs VIN1 and the second differential signal outputs
The grid of VIN2, PMOS tube PM1 and the grid of NMOS tube NM0 are connect with the first differential signal outputs VIN1, the second difference
Signal output end VIN2 is connect with the grid of the grid of PMOS tube PM2 and NMOS tube NM1.
Specifically, when the common-mode voltage for recommending the differential signal in inverting amplifier by differential signal outputs input is big
(PMOS tube PM1, PMOS tube PM2 are in saturation region or subthreshold value when the threshold voltage of NMOS tube NM0 and NMOS tube NM1
Area), differential output signal can be amplified by recommending inverting amplifier at this time, and amplified AC signal is by recommending reverse phase
The the first difference output end VOUT_1 and the second difference output end VOUT_2 of amplifier are exported to bootstrapping gain amplifier.
The present invention using differential input end, recommend inverting amplifier, bootstrapping gain amplifier, traditional Differential Input
The influence that can inhibit common-mode noise, recommending inverting amplifier may be implemented Full-swing output, provide for next stage higher defeated
Enter the amplitude of oscillation, and the structure forms two stage amplifer and be easier to keep time pole and dominant pole separate there are also with roomy advantage, it can be with
The use of compensation circuit is avoided, bandwidth is maximumlly utilized；Bootstrapping gain amplifier extends amplifier used by the application
Bandwidth, reduce power consumption, reduce biasing circuit, save chip area.
In one embodiment of the invention, the bootstrapping gain amplifier includes: second source end VDD2, the second common mode
Feed circuit VFB2, bias voltage output VB, auxiliary OP AMP INVP, auxiliary OP AMP INVN, PMOS tube PM3, PMOS tube PM4,
PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5；
The grid of the PMOS tube PM7 is connect with the output end of the second common mode feedback circuit VFB2, the PMOS tube
The source electrode of PM7 is connect with the second source end VDD2, and the drain electrode of the PMOS tube PM7 is separately connected the PMOS tube PM5's
The source electrode of source electrode and the PMOS tube PM6；
The source electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM6, the grid of the PMOS tube PM5 and institute
Bias voltage output VB connection is stated, the drain electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM3, the PMOS
The drain electrode of pipe PM5 is also connect with the input terminal INVP_IN+ of the auxiliary OP AMP INVP；The grid of the PMOS tube PM3 with it is described
The output end INVP_OUT+ connection of auxiliary OP AMP INVP, the drain electrode of the PMOS tube PM3 connect with the drain electrode of the NMOS tube NM4
It connects, and the drain electrode of the PMOS tube PM3 connect intersection point with the drain electrode of the NMOS tube NM4 as the bootstrapping gain amplifier
The first difference output end VOUT1；The output end INVN_OUT+ of the grid of the NMOS tube NM4 and the auxiliary OP AMP INVN
Connection, the source electrode of the NMOS tube NM4 connect with the drain electrode of the NMOS tube NM2, the source electrode of the NMOS tube NM4 also with it is described
The input terminal INVN_IN connection of auxiliary OP AMP INVN；The grid of the NMOS tube NM2 and described recommend the of reverse phase amplification appliance
One difference output end VOUT_1 connection, the source grounding GND of the source electrode of the NMOS tube NM2 and the NMOS tube NM3；
The grid of the PMOS tube PM6 is connect with the bias voltage output VB, the drain electrode of the PMOS tube PM6 and institute
The source electrode connection of PMOS tube PM4 is stated, the drain electrode of the PMOS tube PM6 connects with the input terminal INVP_IN- of the auxiliary OP AMP INVP
It connects, the output end INVP_OUT- of the output end INVP of the grid and auxiliary OP AMP of the PMOS tube PM4 is connect, described
The drain electrode of PMOS tube PM4 is connect with the drain electrode of the NMOS tube NM5, and the drain electrode of the PMOS tube PM4 is with the NMOS tube NM5's
Second difference output end VOUT2 of the drain electrode connection intersection point as the bootstrapping gain amplifier；The grid of the NMOS tube NM5 with
The output end INVN_OUT- connection of the auxiliary OP AMP INVN, the leakage of the source electrode of the NMOS tube NM5 and the NMOS tube NM3
Pole connection, the source electrode of the NMOS tube NM5 are connect with the input terminal INVN_IN- of the auxiliary OP AMP INVN；The NMOS tube
The grid of NM3 is connect with the second difference output end VOUT_2 for recommending inverting amplifier；
The first differential input end of the second common mode feedback circuit VFB2 and the bootstrapping gain amplifier it is first poor
Divide output end VOUT1 connection, the second differential input end of the second common mode feedback circuit VFB2 and the bootstrapping gain are amplified
Second difference output end VOUT2 connection of device.
Specifically, referring to Fig. 2, Fig. 2 is a kind of electricity of Novel ultra wide band operational amplifier provided in an embodiment of the present invention
Another bootstrapping gain amplifier circuit figure on road, the amplified signal of differential push-pull input stage are input to bootstrapping gain amplifier
NMOS tube NM2, NM3, NMOS tube NM2, NM3 as commonsource amplifier amplification be input to its grid end signal it is defeated from drain terminal
Out, then after cathode-input amplifier NM4, NM5 are amplified be sequentially delivered to current source load PMOS tube PM3/PM4, PM5/PM6,
PM7.Auxiliary OP AMP INVN, auxiliary OP AMP INVP are respectively that NM4, NM5 and PM3, PM4 provide high gate source voltage, can be significantly
It improves the output impedance of bootstrapping gain output stage and then increases its gain.
NMOS tube NM2, NM3 is exported as the signal that commonsource amplifier amplification is input to its grid from grid, after amplification
Signal be transmitted in auxiliary OP AMP INVN signal amplified, be added in NMOS tube through the amplified signal of auxiliary OP AMP INVN
The grid of NM4, NM5；The amplified grid for being transmitted to PMOS tube PM3, PM4 of signal that auxiliary OP AMP INVP carrys out transmitting, then
It is exported via after the amplification of PMOS tube PM3, PM4 in its drain electrode；Increase respectively through bootstrapping through NMOS tube and the amplified signal of PMOS tube
The second difference output end VOUT2 output of first difference output end VOUT1 of beneficial amplifier, gain amplifier of booting.
In one embodiment of the invention, Fig. 3 is referred to, Fig. 3 is a kind of novel ultra-wide provided in an embodiment of the present invention
Auxiliary OP AMP INVN circuit diagram with operational amplifier, the auxiliary OP AMP INVN include PMOS tube PM8, PMOS tube PM9, NMOS
Pipe NM6, NMOS tube NM7；
The PMOS tube PM8 source electrode is connect with the source electrode of the PMOS tube PM9, the source electrode of the PMOS tube PM8 with it is described
The source electrode of PMOS tube PM9 is connect with the first power end VDD1；The grid of the PMOS tube PM8 and the NMOS tube NM6
Grid connection, and the grid of PMOS tube PM8 connect intersection point with the NMOS tube NM6 grid as the auxiliary OP AMP INVN
The drain electrode of input terminal INVN_IN+, the PMOS tube PM8 connect with the drain electrode of the NMOS tube NM6, and the PMOS tube
The drain electrode of PM8 connects output end INVN_OUT+ of the intersection point as the auxiliary OP AMP INVN with the drain electrode of the NMOS tube NM6；
The grid of the PMOS tube PM9 is connect with the grid of the NMOS tube NM7, and the grid of PMOS tube PM8 and institute
State input terminal INVN_IN- of the NMOS tube NM6 grid connection intersection point as the auxiliary OP AMP INVN, the leakage of the PMOS tube PM9
Pole is connect with the drain electrode of the NMOS tube NM7, and the drain electrode of the PMOS tube PM9 connect intersection point with the drain electrode of the NMOS tube NM7
Output end INVN_OUT- as the auxiliary OP AMP INVN.
In one embodiment of the invention, Fig. 4 is referred to, Fig. 4 is a kind of novel ultra-wide provided in an embodiment of the present invention
Auxiliary OP AMP INVP circuit diagram with operational amplifier, the auxiliary OP AMP INVP include PMOS tube PM10, PMOS tube PM11,
NMOS tube NM8, NMOS tube NM9；
The source electrode of the PMOS tube PM10 is connect with the second source end VDD2 with the source electrode of the PMOS tube PM11；
The grid of PMOS tube PM10 is connect with the grid of the NMOS tube NM8, and the grid of the PMOS tube PM10 and the NMOS
Input terminal INVP_IN+ of the grid connection intersection point of pipe NM8 as auxiliary OP AMP INVP；The drain electrode of the PMOS tube PM10 and institute
The drain electrode connection of NMOS tube NM8 is stated, and the drain electrode of the PMOS tube PM10 connect intersection point work with the drain electrode of the NMOS tube NM8
For the output end INVP_OUT+ of auxiliary OP AMP INVP, the source electrode of the source electrode of the NMOS tube NM8 and the NMOS tube NM9 with
The first power end VDD1；
The grid of the PMOS tube PM11 is connect with the grid of the NMOS tube NM9, and the grid of the PMOS tube PM11
Pole connect input terminal INVP_IN- of the intersection point as auxiliary OP AMP INVP with the grid of the NMOS tube NM9；The PMOS tube
The drain electrode of PM11 is connect with the drain electrode of the NMOS tube NM9, and the drain electrode of the PMOS tube PM11 is with the NMOS tube NM9's
Output end INVP_OUT- of the drain electrode connection intersection point as auxiliary OP AMP INVP.
In the above-described embodiment, auxiliary OP AMP INVN, auxiliary OP AMP INVP are compared using auxiliary inverting amplifier structure
In the auxiliary OP AMP of traditional cascode structure, biasing circuit can be greatly reduced using inverting amplifier structure first, thus
Reduce power consumption；Again because auxiliary OP AMP INVN, auxiliary OP AMP INVP have only used 8 metal-oxide-semiconductors, chip area is substantially reduced,
The reduction of number of transistors purpose also reduces the number of parasitic zero pole point, to realize ultra wide band amplifier.
In one embodiment of the invention, Fig. 5 is referred to, Fig. 5 is a kind of novel ultra-wide provided in an embodiment of the present invention
Bootstrapping gain amplifier circuit figure with operational amplifier, the bootstrapping gain amplifier further include first resistor R1, the second electricity
Hinder R2, first capacitor C1, the second capacitor C2；
The grid of the PMOS tube PM5 is connect by first resistor R1 with the bias voltage output VB；The NMOS
The grid of pipe NM2 passes sequentially through first capacitor C1, first resistor R1 and connect with the bias voltage output VB；
The grid of the PMOS tube PM6 is connect by second resistance R2 with the bias voltage output VB；The NMOS
The grid of pipe NM3 passes sequentially through the second capacitor C2, second resistance R2 and connect with the bias voltage output VB.
Specifically, referring to Fig. 6, Fig. 6 is a kind of electricity of Novel ultra wide band operational amplifier provided in an embodiment of the present invention
Lu Tu recommends the grid input that the amplified difference AC signal of inverting amplifier passes through NMOS tube NM3 and NMOS tube NM2 respectively
Bootstrapping gain amplifier, and PMOS tube PM6 and PMOS tube are transmitted signals to by first capacitor C1, the second capacitor C2 respectively
PM5.Since the gate bias voltage of NMOS tube NM2, NMOS tube NM3 and PMOS tube PM5, PMOS tube PM6 are different, NMOS tube
The syntype bias voltage of NM2, NM3 are the output common mode voltage for recommending inverting amplifier, the bias voltage of PMOS tube PM5, PM6 by
Bias voltage output VB determines that first capacitor C1, the second capacitor C2 recommend the output difference signal of inverting amplifier in transmitting
While, but also NMOS tube NM2, NM3 and the bias voltage of PMOS tube PM5, PM6 are mutually indepedent, guarantee the normal work of each metal-oxide-semiconductor
Make.
Further, the first power end VDD1 voltage is the half of second source end VDD2 voltage, i.e. auxiliary OP AMP INVN
Use voltage range for VDD1-GND power supply, auxiliary OP AMP INVP uses voltage range for VDD2~VDD1 power supply.Auxiliary OP AMP
In INVN, passes through drain electrode respectively through NMOS tube NM2 and the amplified signal of NMOS tube NM3 and is transmitted to inside auxiliary OP AMP INVN,
Signal after PMOS tube PM8, PM9 and NMOS tube NM6, NM7 is amplified again, and be respectively sent to NMOS tube NM4,
NM5, NMOS tube NM4, NM5 carry out third time amplification to the signal, and amplifying to differential signal gradually improves amplifier
Gain.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (6)
1. a kind of Novel ultra wide band operational amplifier characterized by comprising differential signal outputs recommend inverting amplifier
With bootstrapping gain amplifier；
The input terminal for recommending inverting amplifier is connect with the differential signal outputs；The defeated of gain amplifier of booting
Enter end to connect with the output end for recommending inverting amplifier.
2. Novel ultra wide band operational amplifier according to claim 1, which is characterized in that described to recommend inverting amplifier packet
Include the first common mode feedback circuit VFB1, the first power end VDD1, PMOS tube PM0, PMOS tube PM1, PMOS tube PM2, NMOS tube NM0
With NMOS tube NM1；
The grid of the PMOS tube PM1 is connect with the grid of the NMOS tube NM0, the grid of the PMOS tube PM1 and described
The grid of NMOS tube NM0 is all connected with the differential signal outputs, and the drain electrode of the PMOS tube PM1 is with the NMOS tube NM0's
Drain electrode connection intersection point is as the first difference output end VOUT_1 for recommending inverting amplifier, the source electrode of the NMOS tube NM0 and institute
The source grounding GND of NMOS tube NM1 is stated, the source electrode of the PMOS tube PM1 is connect with the source electrode of the PMOS tube PM2, described
The source electrode of the source electrode of PMOS tube PM1 and the PMOS tube PM2 are all connected with the drain electrode of the PMOS tube PM0, the PMOS tube PM0's
Source electrode connects the first power end VDD, the output of the grid of the PMOS tube PM0 and the first common mode feedback circuit VFB1
End connection；The drain electrode of the PMOS tube PM2 is connect with the drain electrode of the NMOS tube NM1, and the drain electrode of the PMOS tube PM2 with
The drain electrode connection intersection point of the NMOS tube NM1 recommends the second difference output end VOUT_2 of inverting amplifier as described in, described
The grid of PMOS tube PM2 is connect with the grid of the NMOS tube NM1, and the grid of the PMOS tube PM2 and the NMOS tube
The grid of NM1 is all connected with the differential signal outputs；The first differential input end of the first common mode feedback circuit VFB1 with
The first difference output end VOUT_1 connection, the second differential input end of the first common mode feedback circuit VFB1 and described the
Two difference output end VOUT_2 connections.
3. Novel ultra wide band operational amplifier according to claim 1, which is characterized in that the bootstrapping gain amplifier packet
It includes: second source end VDD2, the second common mode feedback circuit VFB2, bias voltage output VB, auxiliary OP AMP INVP, auxiliary OP AMP
INVN, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, NMOS tube NM2, NMOS tube NM3,
NMOS tube NM4, NMOS tube NM5；
The grid of the PMOS tube PM7 is connect with the output end of the second common mode feedback circuit VFB2, the PMOS tube PM7's
Source electrode is connect with the second source end VDD2, the drain electrode of the PMOS tube PM7 be separately connected the PMOS tube PM5 source electrode and
The source electrode of the PMOS tube PM6；
The source electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM6, the grid of the PMOS tube PM5 and it is described partially
Voltage output end VB connection is set, the drain electrode of the PMOS tube PM5 is connect with the source electrode of the PMOS tube PM3, the PMOS tube PM5
Drain electrode also connect with the input terminal INVP_IN+ of the auxiliary OP AMP INVP；The grid of the PMOS tube PM3 and the auxiliary
The drain electrode of the output end INVP_OUT+ connection of amplifier INVP, the PMOS tube PM3 is connect with the drain electrode of the NMOS tube NM4, and
And the drain electrode connection intersection point of the drain electrode of the PMOS tube PM3 and the NMOS tube NM4 as the bootstrapping gain amplifier the
One difference output end VOUT1；The grid of the NMOS tube NM4 is connect with the output end INVN_OUT+ of the auxiliary OP AMP INVN,
The source electrode of the NMOS tube NM4 is connect with the drain electrode of the NMOS tube NM2, the source electrode of the NMOS tube NM4 also with the auxiliary
The input terminal INVN_IN connection of amplifier INVN；The grid of the NMOS tube NM2 and described recommend the first poor of reverse phase amplification appliance
Divide output end VOUT_1 connection, the source grounding GND of the source electrode of the NMOS tube NM2 and the NMOS tube NM3；
The grid of the PMOS tube PM6 is connect with the bias voltage output VB, the drain electrode of the PMOS tube PM6 with it is described
The source electrode of PMOS tube PM4 connects, and the drain electrode of the PMOS tube PM6 connects with the input terminal INVP_IN- of the auxiliary OP AMP INVP
It connects, the output end INVP_OUT- of the output end INVP of the grid and auxiliary OP AMP of the PMOS tube PM4 is connect, described
The drain electrode of PMOS tube PM4 is connect with the drain electrode of the NMOS tube NM5, and the drain electrode of the PMOS tube PM4 is with the NMOS tube NM5's
Second difference output end VOUT2 of the drain electrode connection intersection point as the bootstrapping gain amplifier；The grid of the NMOS tube NM5 with
The output end INVN_OUT- connection of the auxiliary OP AMP INVN, the leakage of the source electrode of the NMOS tube NM5 and the NMOS tube NM3
Pole connection, the source electrode of the NMOS tube NM5 are connect with the input terminal INVN_IN- of the auxiliary OP AMP INVN；The NMOS tube
The grid of NM3 is connect with the second difference output end VOUT_2 for recommending inverting amplifier；
The first differential input end of the second common mode feedback circuit VFB2 and the first difference of the bootstrapping gain amplifier are defeated
Outlet VOUT1 connection, the second differential input end of the second common mode feedback circuit VFB2 and the bootstrapping gain amplifier
Second difference output end VOUT2 connection.
4. Novel ultra wide band operational amplifier according to claim 3, which is characterized in that the auxiliary OP AMP INVN includes
PMOS tube PM8, PMOS tube PM9, NMOS tube NM6, NMOS tube NM7；
The PMOS tube PM8 source electrode is connect with the source electrode of the PMOS tube PM9, the source electrode and the PMOS of the PMOS tube PM8
The source electrode of pipe PM9 is connect with the first power end VDD1；The grid of the grid of the PMOS tube PM8 and the NMOS tube NM6
Pole connection, and the grid of PMOS tube PM8 connect intersection point with the NMOS tube NM6 grid as the defeated of the auxiliary OP AMP INVN
Entering and holds INVN_IN+, the drain electrode of the PMOS tube PM8 is connect with the drain electrode of the NMOS tube NM6, and the PMOS tube PM8
Drain electrode and the drain electrode of the NMOS tube NM6 connect output end INVN_OUT+ of the intersection point as the auxiliary OP AMP INVN；
The grid of the PMOS tube PM9 is connect with the grid of the NMOS tube NM7, and the grid of PMOS tube PM8 with it is described
NMOS tube NM6 grid connects input terminal INVN_IN- of the intersection point as the auxiliary OP AMP INVN, the drain electrode of the PMOS tube PM9
It is connect with the drain electrode of the NMOS tube NM7, the drain electrode of the PMOS tube PM9 connect intersection point work with the drain electrode of the NMOS tube NM7
For the output end INVN_OUT- of the auxiliary OP AMP INVN.
5. Novel ultra wide band operational amplifier according to claim 3, which is characterized in that the auxiliary OP AMP INVP includes
PMOS tube PM10, PMOS tube PM11, NMOS tube NM8, NMOS tube NM9；
The source electrode of the PMOS tube PM10 is connect with the second source end VDD2 with the source electrode of the PMOS tube PM11；PMOS
The grid of pipe PM10 is connect with the grid of the NMOS tube NM8, and the grid of the PMOS tube PM10 and the NMOS tube NM8
Input terminal INVP_IN+ of the grid connection intersection point as auxiliary OP AMP INVP；The drain electrode of the PMOS tube PM10 and the NMOS
The drain electrode of pipe NM8 connects, and the drain electrode of the PMOS tube PM10 connect intersection point with the drain electrode of the NMOS tube NM8 as auxiliary
The source electrode of the output end INVP_OUT+ of amplifier INVP, the source electrode of the NMOS tube NM8 and the NMOS tube NM9 are with described
One power end VDD1；
The grid of the PMOS tube PM11 is connect with the grid of the NMOS tube NM9, and the grid of the PMOS tube PM11 with
Input terminal INVP_IN- of the grid connection intersection point of the NMOS tube NM9 as auxiliary OP AMP INVP；The PMOS tube PM11's
Drain electrode is connect with the drain electrode of the NMOS tube NM9, and the drain electrode of the PMOS tube PM11 and the drain electrode of the NMOS tube NM9 connect
Output end INVP_OUT- of the contact point as auxiliary OP AMP INVP.
6. Novel ultra wide band operational amplifier according to claim 3, which is characterized in that the bootstrapping gain amplifier is also
Including first resistor R1, second resistance R2, first capacitor C1, the second capacitor C2；
The grid of the PMOS tube PM5 is connect by first resistor R1 with the bias voltage output VB；The NMOS tube NM2
Grid pass sequentially through first capacitor C1, first resistor R1 and connect with the bias voltage output VB；
The grid of the PMOS tube PM6 is connect by second resistance R2 with the bias voltage output VB；The NMOS tube NM3
Grid pass sequentially through the second capacitor C2, second resistance R2 and connect with the bias voltage output VB.
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| CN201910576998.2A CN110350880A (en) | 2019-06-28 | 2019-06-28 | A kind of Novel ultra wide band operational amplifier |
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| CN201910576998.2A CN110350880A (en) | 2019-06-28 | 2019-06-28 | A kind of Novel ultra wide band operational amplifier |
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| CN112152627A (en) * | 2020-08-25 | 2020-12-29 | 西安电子科技大学 | MDAC applied to driving of push-pull output stage of analog-to-digital converter (ADC) of GS/s assembly line |
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Application publication date: 20191018 |