CN111740742A - High-speed and high-precision image signal analog-to-digital conversion circuit - Google Patents
High-speed and high-precision image signal analog-to-digital conversion circuit Download PDFInfo
- Publication number
- CN111740742A CN111740742A CN202010478837.2A CN202010478837A CN111740742A CN 111740742 A CN111740742 A CN 111740742A CN 202010478837 A CN202010478837 A CN 202010478837A CN 111740742 A CN111740742 A CN 111740742A
- Authority
- CN
- China
- Prior art keywords
- signal
- analog
- module
- sub
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 26
- 230000003321 amplification Effects 0.000 claims abstract description 10
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 10
- 238000013139 quantization Methods 0.000 claims description 3
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a high-speed high-precision image signal analog-digital conversion circuit, belonging to the technical field of conversion circuits, wherein the high-speed high-precision image signal analog-digital conversion circuit comprises a multi-stage pipeline circuit, a delay alignment register array and a digital calibration circuit, each stage of pipeline circuit comprises a sample-hold module, two sub-ADC modules, a sub-DAC module, a subtraction circuit, a margin amplification module and an output register, an analog input signal is a group of pipeline circuits, firstly, the signal is sampled and held by the sample-hold module, then, the signal is input to the sub-ADC module to be quantized, a digital signal is output to the output register and the sub-DAC module, the sub-DAC module converts the signal into an analog signal and then outputs the analog signal to the subtraction circuit, the analog signal is subtracted from the signal after the sample-hold, and then, the signal is amplified by a certain multiple through the margin amplification module and then is output, the conversion speed is improved, and through comparison, the conversion quality is improved, and errors are avoided.
Description
Technical Field
The invention belongs to the technical field of conversion circuits, and particularly relates to a high-speed and high-precision image signal analog-to-digital conversion circuit.
Background
An analog-to-digital converter, or ADC for short, generally refers to an electronic component that converts an analog signal into a digital signal. A typical analog-to-digital converter converts an input voltage signal into an output digital signal. Since digital signals do not have practical significance per se, only one relative magnitude is represented. Therefore, any analog-to-digital converter needs a reference analog quantity as a conversion standard, and a common reference standard is the maximum convertible signal size. And the output digital quantity represents the magnitude of the input signal relative to the reference signal.
The prior art has the following problems: the existing image signal analog-to-digital conversion circuit has the disadvantages of slow conversion speed, influence on the conversion speed of image signals, complex structure and inconvenience in use.
Disclosure of Invention
To solve the problems set forth in the background art described above. The invention provides a high-speed and high-precision image signal analog-to-digital conversion circuit which has the characteristics of simple structure, high conversion speed and portability.
In order to achieve the purpose, the invention provides the following technical scheme: a high-speed high-precision image signal analog-to-digital conversion circuit comprises a multi-stage pipeline circuit, a delay alignment register array and a digital calibration circuit, wherein each stage of pipeline circuit comprises a sample-hold module, two sub-ADC modules, a sub-DAC module, a subtraction circuit, a margin amplification module and an output register, an analog input signal group pipeline circuit firstly carries out sample-hold on the signal in the sample-hold module, then the signal is input to the sub-ADC modules to carry out quantization on the signal, the digital signal is output to the output register and the sub-DAC module, the sub-DAC module converts the signal into an analog signal and then outputs the analog signal to the subtraction circuit, the analog signal is subtracted from the signal after sample-hold, then the signal is amplified by a certain multiple through the margin amplification module and output to the delay alignment register array, the output register of each group of pipeline circuits is connected with the delay alignment register array, the output of the delay alignment register array is connected with the digital calibration circuit, and the signal is output after being calibrated.
In a further aspect of the present invention, the high-speed and high-precision analog-to-digital conversion circuit for image signals comprises a timer, and outputs of the timer are respectively connected to the delay alignment register array and the digital calibration circuit.
Compared with the prior art, the invention has the beneficial effects that:
the invention includes a sample hold module, two sub ADC modules, a sub DAC module, a subtraction circuit, a margin amplifying module and an output register in each stage of pipeline circuit, analog input signal is a group of pipeline circuits, firstly, the sample hold module samples and holds the signal, then the signal is input to the sub ADC module to quantize the signal, and output digital signal to the output register and the sub DAC module, the sub DAC module converts the signal into analog signal and outputs to the subtraction circuit, the analog signal and the signal after sample hold are subtracted, then the signal is amplified by a certain multiple by the margin amplifying module and output to the delay alignment register array, thereby improving the conversion speed, and improving the conversion quality and avoiding errors by comparison.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides the following technical solutions: a high-speed high-precision image signal analog-to-digital conversion circuit comprises a multi-stage pipeline circuit, a delay alignment register array and a digital calibration circuit, wherein each stage of pipeline circuit comprises a sample-hold module, two sub-ADC modules, a sub-DAC module, a subtraction circuit, a margin amplification module and an output register, an analog input signal group pipeline circuit firstly carries out sample-hold on the signal in the sample-hold module, then the signal is input to the sub-ADC modules to carry out quantization on the signal, the digital signal is output to the output register and the sub-DAC module, the sub-DAC module converts the signal into an analog signal and then outputs the analog signal to the subtraction circuit, the analog signal is subtracted from the signal after sample-hold, then the signal is amplified by a certain multiple through the margin amplification module and output to the delay alignment register array, and the output register of each group of pipeline circuits is connected with the delay alignment register array, the output of the delay alignment register array is connected with the digital calibration circuit, and the signal is output after being calibrated.
Furthermore, the high-speed and high-precision image signal analog-to-digital conversion circuit comprises a timer, and the output of the timer is respectively connected with the delay alignment register array and the digital calibration circuit.
The working principle and the using process of the invention are as follows: the analog-to-digital conversion circuit comprises a multi-stage pipeline circuit, a delay alignment register array and a digital calibration circuit, wherein each stage of pipeline circuit comprises a sample-hold module, two sub-ADC modules, a sub-DAC module, a subtraction circuit, a margin amplification module and an output register, an analog input signal is a group of pipeline circuits, firstly, a signal is sampled and held by the sample-hold module, then the signal is input to the sub-ADC modules to be quantized, a digital signal is output to the output register and the sub-DAC module, the sub-DAC module converts the signal into an analog signal and outputs the analog signal to the subtraction circuit, the analog signal is subtracted from the signal after sample-hold, then the signal is amplified by a margin amplification module by a certain factor and output to the delay alignment register array, the output register of each group of pipeline circuits is connected with the delay alignment register array, the output of the delay alignment register array is connected with the digital calibration, and outputting the signal after calibration.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (2)
1. A high-speed, high-precision image signal analog-to-digital conversion circuit is characterized in that: the high-speed and high-precision image signal analog-to-digital conversion circuit comprises a multi-stage pipeline circuit, a delay alignment register array and a digital calibration circuit, wherein each stage of pipeline circuit comprises a sample-hold module, two sub-ADC modules, a sub-DAC module, a subtraction circuit, a margin amplification module and an output register, an analog input signal group pipeline circuit firstly carries out sample-hold on the signal in the sample-hold module, then the signal is input to the sub-ADC module to carry out quantization on the signal, the digital signal is output to the output register and the sub-DAC module, the sub-DAC module converts the signal into an analog signal and then outputs the analog signal to the subtraction circuit, the analog signal is subtracted from the signal after sample-hold, then the signal is amplified by a certain multiple through the margin amplification module and is output to the delay alignment register array, and the output register of each group pipeline circuit is connected with the delay alignment, the output of the delay alignment register array is connected with the digital calibration circuit, and the signal is output after being calibrated.
2. A high-speed, high-precision image signal analog-to-digital conversion circuit according to claim 1, characterized in that: the high-speed and high-precision image signal analog-to-digital conversion circuit comprises a timer, and the output of the timer is respectively connected with the delay alignment register array and the digital calibration circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010478837.2A CN111740742A (en) | 2020-05-29 | 2020-05-29 | High-speed and high-precision image signal analog-to-digital conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010478837.2A CN111740742A (en) | 2020-05-29 | 2020-05-29 | High-speed and high-precision image signal analog-to-digital conversion circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111740742A true CN111740742A (en) | 2020-10-02 |
Family
ID=72648052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010478837.2A Pending CN111740742A (en) | 2020-05-29 | 2020-05-29 | High-speed and high-precision image signal analog-to-digital conversion circuit |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111740742A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114499524A (en) * | 2021-12-09 | 2022-05-13 | 珠海横琴精韵科技有限公司 | Analog-to-digital conversion method of pipelined ADC |
CN116318154A (en) * | 2023-05-17 | 2023-06-23 | 南方电网数字电网研究院有限公司 | Analog-to-digital conversion device and signal conversion equipment |
CN117076345A (en) * | 2023-10-12 | 2023-11-17 | 北京紫光芯能科技有限公司 | Analog-to-digital conversion processing method, system and related equipment based on MCAL |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101552609A (en) * | 2009-02-12 | 2009-10-07 | 苏州通创微芯有限公司 | Pipelined analog-digital converter |
CN201957001U (en) * | 2011-02-16 | 2011-08-31 | 东南大学 | Pipeline analog-to-digital converter capable of carrying out background digital calibration |
US8659461B1 (en) * | 2012-11-13 | 2014-02-25 | University Of Macau | Analog to digital converter circuit |
CN104300981A (en) * | 2014-09-30 | 2015-01-21 | 成都市晶林科技有限公司 | High-speed and high-precision image signal analog-to-digital conversion circuit |
CN204131502U (en) * | 2014-09-30 | 2015-01-28 | 成都市晶林科技有限公司 | At a high speed, high precision image signal analog to digital conversion circuit |
CN105959005A (en) * | 2016-04-20 | 2016-09-21 | 北京交通大学 | Digital background calibration device for pipeline ADC |
-
2020
- 2020-05-29 CN CN202010478837.2A patent/CN111740742A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101552609A (en) * | 2009-02-12 | 2009-10-07 | 苏州通创微芯有限公司 | Pipelined analog-digital converter |
CN201957001U (en) * | 2011-02-16 | 2011-08-31 | 东南大学 | Pipeline analog-to-digital converter capable of carrying out background digital calibration |
US8659461B1 (en) * | 2012-11-13 | 2014-02-25 | University Of Macau | Analog to digital converter circuit |
CN104300981A (en) * | 2014-09-30 | 2015-01-21 | 成都市晶林科技有限公司 | High-speed and high-precision image signal analog-to-digital conversion circuit |
CN204131502U (en) * | 2014-09-30 | 2015-01-28 | 成都市晶林科技有限公司 | At a high speed, high precision image signal analog to digital conversion circuit |
CN105959005A (en) * | 2016-04-20 | 2016-09-21 | 北京交通大学 | Digital background calibration device for pipeline ADC |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114499524A (en) * | 2021-12-09 | 2022-05-13 | 珠海横琴精韵科技有限公司 | Analog-to-digital conversion method of pipelined ADC |
CN116318154A (en) * | 2023-05-17 | 2023-06-23 | 南方电网数字电网研究院有限公司 | Analog-to-digital conversion device and signal conversion equipment |
CN116318154B (en) * | 2023-05-17 | 2023-09-15 | 南方电网数字电网研究院有限公司 | Analog-to-digital conversion device and signal conversion equipment |
CN117076345A (en) * | 2023-10-12 | 2023-11-17 | 北京紫光芯能科技有限公司 | Analog-to-digital conversion processing method, system and related equipment based on MCAL |
CN117076345B (en) * | 2023-10-12 | 2024-02-27 | 北京紫光芯能科技有限公司 | Analog-to-digital conversion processing method, system and related equipment based on MCAL |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111740742A (en) | High-speed and high-precision image signal analog-to-digital conversion circuit | |
CN101777917B (en) | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof | |
CN102751990A (en) | Pipelined analog-to-digital converter capable of improving dynamic performance | |
KR101224102B1 (en) | The SHA-less Pipelined Analog-to-Digital Converter | |
US20130127646A1 (en) | Multiplying digital-to-analog converter (dac) | |
CN100546194C (en) | Operational amplifier shared circuit and pipeline analog-to-digital converter applying same | |
CN111446964A (en) | Novel fourteen-bit assembly line-successive approximation type analog-digital converter | |
TW202017323A (en) | Gain calibration device and method for residue ampilifier of pipeline analog to digital converter | |
CN104682958A (en) | Noise-shaping flash successive approximation register analog-to-digital converter (Noise-Shaping Flash-SAR ADC) | |
CN102013894B (en) | Low-power pipeline analogue-digital converter (ADC) | |
CN110224701B (en) | Pipelined ADC | |
CN109462402B (en) | Mixed type assembly line ADC structure | |
CN111740741B (en) | Pipelined ADC capacitance mismatch calibration circuit and method | |
CN101277115B (en) | Multiplying digital-analog conversion circuit sharing operational amplifier | |
CN112104370A (en) | High-precision analog-to-digital converter conversion speed improving circuit | |
CN114629497B (en) | Comparator offset voltage eliminating circuit for column parallel single-slope analog-to-digital converter | |
CN113659988B (en) | Single-period multi-bit quantized successive approximation type analog-to-digital converter | |
CN107786206A (en) | Pipeline SAR-ADC system | |
CN112398472B (en) | Error quantization 10-bit monoclinic ADC for image sensor | |
CN207410329U (en) | Pipeline SAR-ADC device | |
CN112511169A (en) | Production line ADC dynamic compensation system and method based on Sigma-Delta modulator | |
CN111147077B (en) | Gain calibration device and method for residual amplifier of analog-digital converter | |
El-Sankary et al. | Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers | |
Song et al. | a Enob 10.3 bit, 103 μW On-Chip Calibration SAR ADC | |
CN115149948B (en) | PIPELINED SAR ADC with high linearity characteristic |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |