CN114978165A - Time-interleaved pipelined successive approximation analog-to-digital converter - Google Patents

Time-interleaved pipelined successive approximation analog-to-digital converter Download PDF

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CN114978165A
CN114978165A CN202210670904.XA CN202210670904A CN114978165A CN 114978165 A CN114978165 A CN 114978165A CN 202210670904 A CN202210670904 A CN 202210670904A CN 114978165 A CN114978165 A CN 114978165A
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stage
digital converter
successive approximation
analog
amplifier
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金晶
潘强
过悦康
刘晓鸣
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Shanghai Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

A time-interleaved pipelined successive approximation analog-to-digital converter comprising: the invention has sampling frequency and wide signal bandwidth above GHz, can carry on the high-speed conversion to the signal in the radio frequency system, utilize on-chip analog and digital calibration technology to solve the mismatch problem among the channels of the time interweaving analog-to-digital converter at the same time, in addition, the invention adopts the sub analog-to-digital converter of the successive approximation mixed type architecture (PSAR) of the assembly line, realize the low-power consumption design.

Description

Time-interleaved pipelined successive approximation analog-to-digital converter
Technical Field
The invention relates to a technology in the field of wireless communication, in particular to a time-interleaved pipeline successive approximation analog-to-digital converter.
Background
The time-interleaved analog-to-digital converter can achieve the sampling rate which is difficult to achieve by the single-core analog-to-digital converter through the alternative work of the N paths of single-core analog-to-digital converters, so the time-interleaved analog-to-digital converter is often applied to high-speed occasions. The pipeline successive approximation analog-to-digital converter combines the high-speed characteristic of the pipeline ADC and the low power consumption advantage of the successive approximation ADC, and is very suitable for designing the high-speed low-power consumption middle and high-precision analog-to-digital converter. But the problem of mismatch between channels of the time-interleaved analog-to-digital converter includes: mismatch caused by channel offset mismatch, gain mismatch and sampling time deviation have great influence on the performance of the time-interleaved analog-to-digital converter. Meanwhile, the performance of the whole ADC is also deteriorated by the inter-stage gain mismatch and the offset of the module circuit of the pipeline successive approximation hybrid analog-to-digital converter, and in addition, the inter-stage residual amplifier is also a design difficulty.
Disclosure of Invention
The invention provides a time-interleaved assembly line successive approximation analog-to-digital converter aiming at the defects of larger overall power consumption and area consumption of an input buffer of the existing high-speed time-interleaved analog-to-digital converter, which has a sampling frequency above GHz and a wide signal bandwidth, can perform high-speed conversion on signals in a radio frequency system, and simultaneously solves the problem of mismatch among channels of the time-interleaved analog-to-digital converter by utilizing an on-chip analog and digital calibration technology.
The invention is realized by the following technical scheme:
the invention relates to a time-interleaved pipeline successive approximation analog-to-digital converter, comprising: the device comprises a pipeline successive approximation analog-to-digital converter unit, an on-chip integrated input buffer unit, a clock generation module unit and a digital reconstruction filter unit, wherein: the input buffer unit receives an input signal of the time-interleaved pipeline successive approximation analog-to-digital converter and provides 50-ohm impedance matching for input; the pipeline successive approximation analog-to-digital converter unit performs analog-to-digital conversion processing according to the analog output information of the input buffer to obtain a digital code value corresponding to the analog input signal; the clock generation module unit carries out frequency division and phase processing according to a clock input signal, provides a sampling clock for the pipeline successive approximation analog-to-digital converter unit and controls the overall working time sequence of the time-interleaved pipeline successive approximation analog-to-digital converter; and the digital reconstruction filter unit performs interleaving reconstruction according to the data output by the pipeline successive approximation analog-to-digital converter unit to obtain a digital output code value of the time interleaving pipeline successive approximation analog-to-digital converter.
The assembly line successive approximation analog-to-digital converter unit is of a four-channel structure, and each channel comprises: three-stage sub successive approximation register analog-to-digital converter (SAR ADC), two inter-stage residual amplifiers, a bootstrap switch, a single-core digital calibration module, and a digital error correction logic DEC, wherein: the bootstrap switch works at the frequency of Fs/4 to sample the input, the first-stage SAR ADC quantizes the input and obtains a residual error, and the residual error amplifier amplifies the residual error voltage to the next-stage SAR ADC; the three-stage SAR ADC resolution ratio is 5bit, 5bit and 6bit respectively, and the gain of the two-stage interstage residual error amplifier is 8 x; the single-core digital calibration module completes the offset calibration of a comparator of the three-level SAR ADC, the offset calibration of a residual error amplifier and the gain calibration of an inter-stage residual error amplifier; and the DEC performs logic operation on the output of the three-level sub SAR ADC to obtain output data.
The interstage residual error amplifier comprises: a body circuit, a common mode detection circuit and a gain compensation circuit, wherein: the dynamic amplifier works in three phases, and resets, amplifies and maintains to realize residual voltage amplification. The common mode detection circuit controls an output common mode and controls the amplification process of the residual error amplifier, and the gain compensation circuit adjusts the amplification factor of the residual error amplifier according to different working environments and PVT.
The input buffer includes: a Source Follower (Source Follower) architecture buffer and an on-chip negative voltage generator, wherein: the buffer provides driving capability for the input of the analog-to-digital converter and 50-ohm impedance matching for the previous stage, and the on-chip negative voltage generator provides negative voltage power supply for the input buffer, so that the linearity of the input buffer is improved.
Technical effects
The invention can realize the resolution of 12bit and the signal bandwidth close to GHz by the design method of the whole architecture of the four-channel time-interleaved pipeline successive approximation analog-digital converter, the mismatch calibration scheme among the channels thereof, the pipeline successive approximation analog-digital converter unit and the calibration scheme thereof, and the gain compensation technology of the interstage residual amplifier based on the dynamic amplifier, and has the characteristic of low power consumption. The mismatch between channels due to time interleaving and the non-idealities of the sub-successive approximation register ADC itself are corrected by the digital calibration system.
Drawings
FIG. 1 is a schematic diagram of a four-channel time-interleaved pipelined successive approximation analog-to-digital converter;
FIG. 2 is a schematic diagram of a four-channel time-interleaved pipeline successive approximation analog-to-digital converter inter-channel timing error calibration module;
FIG. 3 is a timing diagram of the operation of a four-channel time-interleaved pipelined successive approximation analog-to-digital converter;
FIG. 4 is a schematic diagram of a pipeline successive approximation ADC unit;
FIG. 5 is a timing diagram of the operation of a three-level sub-successive approximation register type analog-to-digital converter;
FIG. 6 is a circuit diagram of a dynamic amplifier based residual amplifier;
FIG. 7 is a circuit diagram of an on-chip integrated input buffer.
Detailed Description
As shown in fig. 1, the present embodiment relates to a four-channel time-interleaved pipelined successive approximation analog-to-digital converter, which includes: clock generation module, controllable delay chain, consecutive input buffer, assembly line successive approximation analog-to-digital converter unit, digital reconstruction filter and calibration module, wherein: the clock generation module and the controllable delay chain are used for forming an inter-channel timing error calibration module, and the input buffer receives a signal voltage V in Connected with a bootstrap switch of the four-way sub-analog-to-digital converter, a clock generation module connected with the pipeline successive approximation analog-to-digital converter unit for receiving a master frequency clock CLK of the time-interleaved successive approximation analog-to-digital converter S The frequency of the master frequency clock is the sampling frequency of the time-interleaved analog-to-digital converter, and the clock generation module outputs four down-conversion clocks, i.e.CLK 0 、CLK 1 、CLK 2 And CLK 3 Their frequency is 1/4 times the sampling frequency of the time-interleaved successive approximation analog-to-digital converter, and their phases differ by 90 ° from each other. Respectively controlling three-stage sub successive approximation register type analog-digital converters and bootstrap switches in four channels in the pipeline successive approximation analog-digital converter unit so as to realize four-channel time interleaving, wherein three-stage sub successive approximation register type analog-digital converters ADC 0-3 in the four channels alternately work at the speed of sampling frequency 1/4 of the time interleaving pipeline successive approximation analog-digital converter and output 12-bit data D 0 <11:0>、D 1 <11:0>、D 2 <11:0>、D 3 <11:0>Outputting the uncalibrated data D after being reconstructed by a digital reconstruction filter ch <11:0>To the calibration module, the calibration module outputs the calibrated output Dout<11:0>。
As shown in fig. 2, the inter-channel timing error calibration module includes: clock generation module, frequency divider and parallelly connected four controllable delay chain, wherein: the clock generation module receives a master clock CLK of the time-interleaved successive approximation analog-to-digital converter S After passing through an on-chip clock buffer, is divided by a frequency divider 4 to generate CLK 0 、CLK 1 、CLK 2 、CLK 3 And the four-phase clock. The four-phase clock respectively controls three stages of successive approximation register type analog-digital converters ADC 0-3 in four channels to sample.
Due to the parasitic, wiring, and manufacturing process variations, the phases of the four-phase clocks may vary and accurate 1/4 phase spacing may not be achieved, resulting in timing errors.
In the embodiment, the phase interval between four phases of time is adjusted through the controllable delay chains, and each controllable delay chain is regulated and controlled by an 8-bit digital input code value, namely Dtune0<7:0>, Dtune1<7:0>, Dtune2<7:0> and Dtune3<7:0>, so that the calibration of timing errors is realized, harmonic waves caused by the timing errors are eliminated, and the linearity and the spurious-free dynamic range of the time-interleaved pipeline successive approximation analog-to-digital converter are improved.
As shown in the figureAnd 3, a timing diagram of the four-channel time-interleaved pipeline successive approximation analog-to-digital converter is shown. CLK S 、CLK 0 、CLK 1 、CLK 2 、CLK 3 For the clock generation module input signal shown in FIG. 1 and the control signal of the three-stage sub successive approximation register type analog-to-digital converter ADC in the four channels, D 0 <11:0>、D 1 <11:0>、D 2 <11:0>、D 3 <11:0>Data is output for a three-stage sub successive approximation register type analog-to-digital converter (ADC) in four channels. [ n-1 ]]、[n]、[n+1]… represents the digital output code value of the input signal at the n-1, n +1 … sample times. See timing diagram, CLK S 、CLK 0 、CLK 1 、CLK 2 、CLK 3 Are separated by 1/4 phases when CLK 0 When the signal is high, the bootstrap switch of the channel 0 is closed, the ADC0 starts sampling, after one sampling time, the sampling is finished, the bootstrap switch is disconnected, the first three-level sub successive approximation register type analog-digital converter ADC0 starts to convert, after one conversion time, the conversion is finished, and the output result D is obtained 0 <11:0>The nth cycle data. Then, sampling and conversion are sequentially started by the second-third-level successive approximation register type analog-digital converters ADC 1-3 to obtain D 1 <11:0>、D 2 <11:0>、D 3 <11:0>Then enter the (n + 1) th cycle, and the process is repeated.
As shown in fig. 4, the three-stage sub successive approximation register type analog-to-digital converter includes: three inter-stage residual amplifiers SAR1, SAR2 and SAR3, two-stage residual amplifiers RA1 and RA2, wherein: the first-stage residual amplifier SAR1 is connected with a first-stage residual amplifier RA1, the first-stage residual amplifier RA1 is connected with a second-stage residual amplifier SAR2, the second-stage residual amplifier SAR2 is connected with a second-stage residual amplifier RA2, the second-stage residual amplifier RA2 is connected with a third-stage residual amplifier SAR3, and the first-stage residual amplifier receives bootstrap sampling switch signals SW _ p and SW _ m (sampling switch).
The three-stage sub successive approximation register type analog-digital converter is a first-stage 5-bit SAR ADC, a second-stage 5-bit SAR ADC and a third-stage 6-bit SAR ADC respectively.
In FIG. 4, φ s Is the sampling clock. CDAC _ p and CDAC _ m (Capacitor Digital-to-Analog Converter) are first-stage sampling capacitors. Phi is a c1 Comparing the clock phi for the first stage comparator c2 Comparing the clock phi for the second stage comparator c3 The clock is compared for the third stage comparator. D<15:0>Raw output data of a pipeline analog-to-digital converter with 16 bits without calibration and digital error logic, wherein D<15:11>Output data for the first stage SAR ADC, D<10:6>Output data for the second stage SAR ADC, D<5:0>Is the output data of the third stage SAR ADC. Dout<11:0>The method is actual output data of original output data of each stage of sub SAR ADC after detuning, gain calibration and Digital Error Correction (DEC).
Different from the existing pipeline successive approximation analog-to-digital converter, the device does not use a closed-loop amplifier as an inter-stage residual error amplifier, but uses a dynamic amplifier as an inter-stage residual error amplifier, thereby reducing power consumption and saving area. The embodiment reduces the gain variation of the dynamic amplifier under different PVT conditions by an analog gain compensation technology.
In the CDAC used in this embodiment, PN CAP and Cali DAC are added on the basis of Main DAC, where: the Main DAC is the same as the traditional CDAC, an upper polar plate is adopted for sampling to improve the sampling speed, and meanwhile, a split type monotonous setting method is adopted to ensure that the common-mode voltage of the upper polar plate of the CDAC keeps unchanged in comparison and setting; PN Cap is used for pseudo-random PN (pseudoandom) signal injection and gain calibration of inter-stage residual amplifiers. The Cali DAC is used to perform offset calibration of the comparator and the residual amplifier.
When the SAR ADC is in a sampling and ending stage, the PN Cap is in a Reset state, the lower plate of the PN Cap on the CDAC _ p is connected with the positive reference voltage VREFP, and the lower plate of the PN Cap on the CDAC _ m is connected with the negative reference voltage VREFM. When the SAR ADC finishes the conversion stage and enters the residual error amplification stage, the PN Cap overturns the voltage of the lower polar plate according to the input pseudo-differential random signal PN. If "PN ═ 1", the PN Cap bottom plate voltage on CDAC _ p keeps the positive reference voltage unchanged, and the PN Cap bottom plate voltage on CDAC _ m is turned over from the negative reference voltage to the positive reference voltage; if "PN is equal to 0", the PN Cap bottom plate voltage under CDAC _ p keeps the negative reference voltage, and the PN Cap top plate voltage on CDAC _ m is flipped from the positive reference voltage to the negative reference voltage. The injected pn signal is multiplied by the output signal of the ADC in the calibration module, accumulated and averaged, and then the gain of the inter-stage residual error amplifier can be obtained. The Cali DAC is used to calibrate the offset of the comparator and the residual amplifier. When the SAR ADC is in a sampling phase, the Cali DAC is in a reset phase, the lower plate of the Cali DAC in the CDAC _ p is connected with a positive reference voltage, and the lower plate of the Cali DAC in the CDAC _ m is connected with a negative reference voltage. When the SAR ADC is in a comparison stage, the Cali DAC is in a comparator offset calibration mode, and the lower plate of the Cali DAC is respectively connected to a positive reference voltage and a negative reference voltage according to an offset calibration code of the comparator, so that offset calibration of the comparator is completed. When the SAR ADC is in a residual error amplification stage, the lower plate of the Cali DAC is respectively connected to a positive reference voltage and a negative reference voltage according to the offset calibration code of the residual error amplifier, and the offset calibration of the residual error amplifier is completed.
As shown in FIG. 5, φ s The bootstrap switch is controlled to be turned on and off, and is a sampling clock with the sampling frequency of 1/fsub. fsub is the sampling frequency of the three-stage pipeline successive ADC, which has the value of 1/4Fs, Fs being the overall sampling frequency of the time-interleaved ADC. Phi is a c1 、φ c2 、φ c3 The comparison clocks of the comparators of the first-stage SAR ADC, the second-stage SAR ADC and the third-stage SAR ADC are respectively. The inter-stage residual amplifier uses a dynamic amplifier based architecture, and therefore requires a reset signal. Phi is a RA1 、φ RST1 The amplification phase and the reset phase of the first stage residual amplifier, respectively. Phi is a RA2 、φ RST2 The amplification phase and the reset phase of the second stage residual amplifier, respectively. D<15:0>Raw data output for a three-stage pipeline, wherein: d<15:11>For the first stage, output data, D<10:6>For the second stage, output data, D<5:0>For the third stage, output data, D<15:0>In the timing chart of (1), a gray shaded portion is an unstable state, and white is a stable state. Referring to the timing diagram, when the nth switching cycle comes, phi first s Is pulled high, enters a sampling stage of a three-stage assembly line successive approximation ADC, and is phi after the sampling stage s Is pulled low. The first-stage comparator starts to work, enters the conversion stage of the first-stage SAR ADC, has an SAR logic of 1b/1cycle, finishes comparison after 5 times of comparison, and D<15:11>Changing from unstable state to stable state to obtain D<15:11>N of (a)]A period of one cycle of the converted value, and at the same time, phi RA1 And the voltage is pulled up, the first-stage residual error amplifier starts to work and enters an amplification stage, and the residual error voltage of the first-stage SAR ADC is amplified to the second-stage SAR ADC. The second stage comparator starts working, enters the conversion stage of the second stage SAR ADC, finishes the comparison stage after 5 times of comparison, and finishes the comparison step D<10:6>From the unstable state to the stable state to obtain D<10:6>N of (a)]The period switches the value. At the same time, phi RA2 And the voltage is pulled up, the first-stage residual error amplifier starts to work and enters an amplification stage, and the residual error voltage of the second-stage SAR ADC is amplified to the third-stage SAR ADC. The third stage comparator starts to work, enters the conversion stage of the third stage SAR ADC, finishes comparison after 6 times of comparison, and D<5:0>From the unstable state to the stable state to obtain D<5:0>N of (a)]The period switches the value. After timing alignment and digital alignment and DEC, Dout is obtained<11:0>Is output in the nth period. It should be noted that the whole conversion process is pipelined, and when the first stage completes the data conversion of the nth cycle and amplifies the residual voltage to the second stage and the second stage starts to perform the data converter of the nth cycle, the first stage starts to receive the sampling signal of the (n + 1) th cycle and starts to convert.
As shown in fig. 6, the inter-stage residual amplifier includes: main part circuit, common mode detection circuit and analog gain compensation circuit, wherein: the common mode detection circuit respectively outputs CMD signals to the main body circuit and the analog gain compensation circuit, wherein VIP and VIM are input differential signals, CLK _ RA is a residual error amplifier amplification signal, CLK _ RST is a residual error amplifier reset signal, VOP and VOM are residual error amplifier differential output signals, and CMD is a common mode detection output signal.
As shown in fig. 6a, the main body circuit includes: tail current controlPipe making M 0 、M 1 Differential pair transistors M for input 2 、M 3 Connecting pipe M for controlling amplifying circuit and output capacitor 4 、M 5 Reset pair transistor M 6 、M 7 And a load capacitor C of the subsequent stage L 。
As shown in fig. 6b, in the common mode detection circuit: c 0 、C 1 Output common mode voltage, M, for detecting VOP, VOM 8 ～M 18 And detecting the output common-mode voltage and generating a CMD signal to control the residual error amplifier to work, and when the output common-mode voltage reaches VCM, pulling down the CMD to the ground level, thereby turning off the residual error amplifier and finishing the amplification process. The reference Voltage generator controls an initial Voltage of the common mode detection circuit, an output Voltage of the reference Voltage generator changes according to a Process, Voltage, and when the PVT causes a gain of the residual error amplifier to decrease, the output Voltage of the reference Voltage generator is raised, so that an amplification time of the residual error amplifier is increased, and the gain of the residual error amplifier is increased. On the contrary, when the PVT causes the gain of the residual amplifier to increase, the output voltage of the reference voltage generator decreases, thereby reducing the amplification time of the residual amplifier and decreasing the gain of the residual amplifier, thereby keeping the gain of the residual amplifier stable. It should be noted that the reference voltage generator is not limited to the only circuit configuration, as long as it can generate an output voltage with a trend opposite to the PVT variation trend of the residual amplifier bulk gain, and it can be used as a circuit for implementing the reference voltage generator.
As shown in fig. 7, the input buffer outputs an input signal to four pipeline successive approximation analog-to-digital converters after buffering according to a time-interleaved pipeline successive approximation analog-to-digital converter, and the input buffer adopts a structure based on a source follower, and specifically includes: source follower M 0 ～M 3 Coupling DC blocking circuit R 0 ～R 3 、C 0 ～C 3 And a bootstrap switch S 0 ～S 4 Wherein: the source follower and the coupling blocking circuit form a main circuit, and the bootstrap switch is connected with the assembly line successive approximation analog-to-digital converter unit.
The source follower M0-M3 are large in size, and sufficient driving capability is provided for output.
In the figure: VIN is the input buffer input voltage, VOUT is the input buffer output voltage, V b1 、V b2 、V b3 、V b4 Four dc bias voltages for the input buffers. VDD (1.8V) is the positive supply voltage to the input buffer. VSS (-0.5V) is the negative supply voltage of the input buffer, V b1 、V b2 、V b3 、V b4 For resistive voltage division generation, EN<3:0>Is the enable signal of four bias circuits when EN<3:0>When the level is high, the four bias circuits normally output bias voltages. When EN<3:0>At low level, the four bias circuits are turned off, V b1 、V b2 、V b3 、V b4 Is set to VDD (1.8V) and the input buffer is turned off. V b1 、V b2 、V b3 、V b4 Can be regulated by 8-bit control words. Runt 0<7:0>、Rtune1<7:0>、Rtune2<7:0>、Rtune3<7:0>The proportion of the resistors in the four bias circuits can be regulated and controlled respectively, thereby regulating and controlling V b1 、V b2 、V b3 、V b4 The voltage of (c). The Negative power supply voltage VSS (-0.5V) is supplied by an on-chip integrated Negative Charge Pump, and compared with the traditional off-chip power supply, the on-chip Negative power supply voltage VSS has higher integration level, smaller power supply ripple and better performance.
Through specific practical experiments, under the 28nm process, the implemented four-channel pipeline successive approximation analog-digital converter unit can reach the sampling frequency of 2GHz and the signal bandwidth of 800MHz, the signal-to-noise-distortion ratio can reach 61.3dB, and the spurious-free dynamic range is 73 dB.
Compared with the prior art, the device realizes 2GHz sampling and a high-speed high-performance analog-to-digital converter with 800MHz signal bandwidth, the signal-to-noise-distortion ratio reaches 61.3dB, and the spurious-free dynamic range is 73 dB.
The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (6)

1. A time-interleaved pipelined successive approximation analog-to-digital converter, comprising: the device comprises a pipeline successive approximation analog-to-digital converter unit, an on-chip integrated input buffer unit, a clock generation module unit and a digital reconstruction filter unit, wherein: the input buffer unit receives an input signal of the time-interleaved pipeline successive approximation analog-to-digital converter and provides 50-ohm impedance matching for input; the pipeline successive approximation analog-to-digital converter unit performs analog-to-digital conversion processing according to the analog output information of the input buffer to obtain a digital code value corresponding to the analog input signal; the clock generation module unit carries out frequency division and phase processing according to a clock input signal, provides a sampling clock for the pipeline successive approximation analog-to-digital converter unit and controls the overall working time sequence of the time-interleaved pipeline successive approximation analog-to-digital converter; and the digital reconstruction filter unit performs interleaving reconstruction according to the data output by the pipeline successive approximation analog-to-digital converter unit to obtain a digital output code value of the time interleaving pipeline successive approximation analog-to-digital converter.
2. The time-interleaved pipelined successive approximation analog-to-digital converter as claimed in claim 1, wherein said pipelined successive approximation analog-to-digital converter unit is of a four-channel structure, each channel comprising: three-stage sub successive approximation register analog-to-digital converter, two inter-stage residual amplifiers, a bootstrap switch, a single-core digital calibration module and a digital error correction logic DEC, wherein: the bootstrap switch works at the frequency of Fs/4 to sample the input, the first-stage SAR ADC quantizes the input and obtains a residual error, and the residual error amplifier amplifies the residual error voltage to the next-stage SAR ADC; the three-stage SAR ADC resolution ratio is 5bit, 5bit and 6bit respectively, and the gain of the two-stage interstage residual error amplifier is 8 x; the single-core digital calibration module completes the offset calibration of a comparator of the three-level SAR ADC, the offset calibration of a residual error amplifier and the gain calibration of an inter-stage residual error amplifier; and the DEC performs logic operation on the output of the three-level sub SAR ADC to obtain output data.
3. The time-interleaved pipelined successive approximation analog-to-digital converter of claim 1 wherein said inter-stage residual amplifier comprises: a body circuit, a common mode detection circuit and a gain compensation circuit, wherein: the dynamic amplifier works in three phases, and resets, amplifies and maintains to realize residual voltage amplification. The common mode detection circuit controls an output common mode and controls the amplification process of the residual error amplifier, and the gain compensation circuit adjusts the amplification factor of the residual error amplifier according to different working environments and PVT.
4. The time-interleaved pipelined successive approximation analog-to-digital converter of claim 1 wherein said input buffer comprises: a source follower architecture buffer and an on-chip negative voltage generator, wherein: the buffer provides driving capability for the input of the analog-to-digital converter and 50-ohm impedance matching for the previous stage, and the on-chip negative voltage generator provides negative voltage power supply for the input buffer, so that the linearity of the input buffer is improved.
5. The time-interleaved pipelined successive approximation analog-to-digital converter as claimed in claim 2, wherein said three-stage sub-successive approximation register-type analog-to-digital converter comprises: three inter-stage residual amplifiers SAR1, SAR2 and SAR3, two-stage residual amplifiers RA1 and RA2, wherein: the first-stage residual amplifier SAR1 is connected with a first-stage residual amplifier RA1, the first-stage residual amplifier RA1 is connected with a second-stage residual amplifier SAR2, the second-stage residual amplifier SAR2 is connected with a second-stage residual amplifier RA2, the second-stage residual amplifier RA2 is connected with a third-stage residual amplifier SAR3, and the first-stage residual amplifier receives bootstrap sampling switch signals SW _ p and SW _ m.
6. The time-interleaved pipelined successive approximation analog-to-digital converter of claim 2 or 5, wherein the three-stage sub-successive approximation register type analog-to-digital converters are a first-stage 5-bit, a second-stage 5-bit and a third-stage 6-bit SAR ADC, respectively.
CN202210670904.XA 2022-06-08 2022-06-08 Time-interleaved pipelined successive approximation analog-to-digital converter Pending CN114978165A (en)

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CN115642915A (en) * 2022-12-23 2023-01-24 南京航空航天大学 Assembly line successive approximation type ADC (analog to digital converter) bit weight calibration system and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115642915A (en) * 2022-12-23 2023-01-24 南京航空航天大学 Assembly line successive approximation type ADC (analog to digital converter) bit weight calibration system and method
CN115642915B (en) * 2022-12-23 2023-04-07 南京航空航天大学 Assembly line successive approximation type ADC (analog to digital converter) bit weight calibration system and method

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