KR20140063059A - Hybrid pipeline adc using time-interleaved sar and flash adc - Google Patents

Abstract

The present invention relates to a pipelined ADC. A first end thereof is configured to be formed by two SAR ADC which is provided in a dual channel and the remaining end thereof is configured to be formed by a first flash ADC and a second flash ADC which are provided in a single channel. The present invention is capable of rapid operation because a Nyquist input signal is appropriately processed even without a secure hash algorithm (SHA) and simultaneously the speed of the operation is not limited by the SAR ADC.

Description

[0001] Hybrid pipeline ADC using dual channel SAR and flash ADC [

The present invention relates to a pipelined ADC, and more particularly, to a pipelined ADC operating at high speed using a dual channel SAR and a flash ADC and a mobile display system including the pipelined ADC.

With the development of portable electronic devices and communication systems, high definition (HD) images can be viewed on smart phones. In such a mobile display system, an analog-to-digital converter (ADC) for converting an analog signal including RGB signals into a digital signal is indispensably required. ADCs for these applications require 12-bit resolution and operating speeds of over 75 MS / s. Traditionally, pipelined architectures have been used to implement these specifications. In the pipelined architecture, the analog input is sampled by the residual voltage amplifier and the flash ADC used in the multiplying digital-to-analog converter (MDAC), so a separate sample- and-hold amplifiers (SHAs). Since the area occupied by the SHA and the power occupied by the entire ADC are not so small, a pipeline structure implemented without SHA for small area and low power has been proposed many times recently. However, existing structures that do not use SHA do not have a fundamental solution other than to add complex digital circuits or partially solve them through sophisticated layouts to maintain performance up to Nyquist's input. On the other hand, the successive approximation register (SAR) ADC has its own sample-and-hold function. Therefore, it is possible to properly process high frequency input signals without a separate SHA, but the number of capacitors required increases with increasing resolution, And consequently the resolution and operation speed of the entire ADC are limited. Especially, SAR ADC designed with high resolution of 12 bit level has internal circuit operation at least 13 times faster than ADC operation speed including input sampling time, so sampling and holding time is insufficient and high-speed operation is difficult. In order to mitigate the increase in area due to the increase in the number of capacitors, the size of the unit capacitors is reduced, but the performance degradation due to the parasitic capacitance and the capacitor mismatch is further increased. To improve this, a two-stage pipelined SAR ADC is used to improve the required number of capacitors and operation speed, but still not enough for high-speed operation.

A pipelined ADC according to an embodiment of the present invention is an analog-to-digital converter (Application No. KR10-2001-0087244) and a multi-stage successive approximation register analog-to-digital converter and an analog- -2008-0090653) ", which is used in A / D conversion.

The first problem to be solved by the present invention is to provide a pipelined ADC using a dual channel SAR and a flash ADC to structurally solve the performance degradation in Nyquist's input processing in an SHA-free pipelined ADC.

A second object of the present invention is to provide a mobile display system including a pipelined ADC using a dual channel SAR and a flash ADC.

In order to solve the first problem, the first stage includes a first flash ADC and a second flash ADC, each of which is formed of two SAR ADCs, each of which is implemented as a dual channel, A plurality of pipelined ADCs are formed.

According to an embodiment of the present invention, each of the SAR ADCs and the MDACs share an amplifier, and the amplifier alternately performs the residual voltage amplification of the selected SAR ADC of the two SAR ADCs and the residual voltage amplification of the MDACs Lt; / RTI > ADC.

According to another embodiment of the present invention, each SAR ADC performs sampling for half a period of the clock, performs SAR operation for the next one period, and repeats performing the residual voltage amplification for the next half period, Performing sampling for half a period of the clock, and performing amplification for the next half-cycle, each SAR ADC performing the sampling and amplification for one period when another SAR ADC performs the SAR operation Which may be a pipelined ADC.

According to another embodiment of the present invention, one of the two input stages of the amplifier may be shared by the two SAR ADCs and the other input stage may be connected to the MDAC. And the SAR ADC channel coupled to the input end of the amplifier is selected by a CMOS switch external to the amplifier.

According to another embodiment of the present invention, the reference voltage used in the SAR operation of the SAR ADC and the reference voltage used in the amplification operation of the amplifier are separated from each other. The reference voltage used and the reference voltage used in the amplifying operation are shared by the reference voltage generating circuit and the reference voltage driving circuit is separated.

According to another embodiment of the present invention, the second flash ADC may be a pipelined ADC in which a most significant bit is first determined and a lower bit is determined.

In order to solve the second problem, the present invention provides a mobile display system including the pipelined ADC.

According to the present invention, it is possible to appropriately process Nyquist input signals without SHA, and at the same time, the resolution to be processed by the SAR ADC is lowered, so that high-speed operation is possible. In addition, all three amplifiers required are shared and implemented by only one amplifier, which can remove the mismatch occurring in the amplifier and reduce the area and power. Further, the sampling clock used in each channel is synchronized with one reference clock to solve the problem of input sampling signal mismatch between channels, and the reference voltage generating circuit separates only the voltage driving circuit used for stable fixing of the reference voltage A problem of reference voltage instability that may occur as a result of overlapping of different operation modes and inconsistency problems that may occur between reference voltages are solved.

Figure 1 illustrates a pipelined ADC according to an embodiment of the present invention.
Figure 2 shows the timing of the main circuit block of a pipelined ADC according to an embodiment of the present invention.
3 illustrates a dual-channel SAR ADC and a shared amplifier according to an embodiment of the present invention.
4 illustrates an on-chip clock generation circuit of a pipelined ADC according to an embodiment of the present invention.
5 illustrates a shared amplifier of a pipelined ADC according to an embodiment of the present invention.
FIG. 6 conceptually illustrates separation of a reference voltage driving circuit of a pipelined ADC according to an embodiment of the present invention.
FIG. 7 illustrates a reference voltage generation circuit and a reference current generation circuit separated by a separate voltage driving circuit of a pipelined ADC according to an embodiment of the present invention.
Figure 8 illustrates a pipelined ADC implemented on a chip according to an embodiment of the present invention.
Figure 9 shows the measured DNL and INL of the ADC of Figure 8;
Figure 10 shows the measured FFT spectrum of the ADC of Figure 8;
Figure 11 shows the measured dynamic performance of the ADC of Figure 8;

Prior to the description of the concrete contents of the present invention, for the sake of understanding, the outline of the solution of the problem to be solved by the present invention or the core of the technical idea is first given.

The pipelined ADC according to an exemplary embodiment of the present invention includes a first flash ADC and a second flash ADC. The first and second flash ADCs are formed by two SAR ADCs, Is formed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art, however, that these examples are provided to further illustrate the present invention, and the scope of the present invention is not limited thereto.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: It is possible to quote the above. In the following detailed description of the principles of operation of the preferred embodiments of the present invention, it is to be understood that the present invention is not limited to the details of the known functions and configurations, and other matters may be unnecessarily obscured, A detailed description thereof will be omitted.

The pipelined ADC according to an exemplary embodiment of the present invention is a pipelined ADC that operates at high speed and simultaneously satisfies high resolution, low power, and small area. A pipelined ADC according to an embodiment of the present invention may be a 12-bit 80 MS / s ADC having a three-stage pipeline structure manufactured by a 0.11um CMOS process.

The pipelined ADC according to an exemplary embodiment of the present invention uses a SAR ADC for the first stage to appropriately process Nyquist's input signal without SHA and the remaining pipeline stages include a flash ADC Lt; / RTI > As a result, the SAR ADC handles only 4 bits, so the number of capacitors required is low. By configuring the dual channel, it is sampled and held for half a period of 80 MHz clock, so the operation speed of the entire ADC is not limited by SAR ADC. On the other hand, a three-stage pipeline ADC requires a total of three amplifiers, theoretically a residual voltage amplifier that amplifies the residual voltage of each channel of the SAR ADC and an amplifier used in the MDAC. If the number of amplifiers required by such a number of amplifiers is implemented as the number of amplifiers as they are, there may be a performance degradation due to offset and gain mismatch between amplifiers as well as increase in area and power, Therefore, it is possible to implement the amplifier with only one amplifier, thereby eliminating the mismatch occurring in the amplifier and reducing the area and power. In addition, the sampling clock used on each channel of the dual-channel SAR ADC can be synchronized to a single reference clock, minimizing the input-to-channel sampling signal mismatch problem. On the other hand, when the SAR ADC of the MDAC and the one channel performs amplification operation, the SAR ADC of the other channel may cause instability problem of the reference voltage fixing time if the SAR operation is performed at a high speed. However, The above problem can be avoided. At this time, the reference voltage generating circuit can share only the voltage driving circuit used for stabilizing the reference voltage, thereby minimizing inconsistencies between the reference voltage used in the SAR ADC and the reference voltage used in the remaining pipeline stages . In addition, the 320MHz high-speed clock used in the SAR ADC can be designed in the chip for easy application to SoC applications. It can adjust the frequency and duty cycle through the external 3-bit control signal, The amplifier amplification time can be adjusted as needed.

The SAR ADC to which the above-described techniques are applied will be described in detail with reference to the drawings.

Figure 1 illustrates a pipelined ADC according to an embodiment of the present invention.

The pipelined ADC according to an exemplary embodiment of the present invention includes a first flash ADC and a second flash ADC. The first and second flash ADCs are formed by two SAR ADCs, .

More specifically, the entire structure of a pipelined ADC according to an embodiment of the present invention includes a first four-bit SAR ADC, a shared amplifier, a 4-bit and a 6-bit flash ADC (a first flash ADC flash1) and second flash ADC (flash2)), MDAC and digital correction logic (DCL), and the reference current generator, the reference voltage generator having two kinds of voltage driving circuits, the timing circuit And may include a clock generation circuit.

Two 4-bit SAR ADCs in the building block can operate at 40MS / s, and the internal clock used during SAR operation can use a 320MHz clock to determine 4 bits during a half-cycle of the 40MHz clock, Lt; / RTI > The 40 MS / s data generated by each of the two SAR ADCs is converted to 80 MS / s data from the DCL and processed at 80 MS / s without any conversion in the case of the remaining pipeline stages composed of flash ADCs have.

The number of preamplifiers required can be reduced by half by applying the interpolation technique to the first and second flash ADCs. In addition, in the case of the second flash ADC, the most significant bit (MSB) is first determined By using a two-stage reference voltage selection technique that determines the low-order 5 bits, the number of preamplifiers and latches required can be reduced to half, thereby reducing the required power and area.

Figure 2 shows the timing of the main circuit block of a pipelined ADC according to an embodiment of the present invention.

A pipelined ADC according to an embodiment of the present invention shares an amplifier between each SAR ADC and MDAC, and the amplifier alternately performs the residual voltage amplification of the selected SAR ADC and the residual voltage amplification of the MDAC.

More specifically, the first stage SAR ADC is implemented in dual channels, which allows sampling and holding throughout the clock period to overcome the shortage of signal settling time due to lack of sampling and hold time, which is a disadvantage of SAR ADC. In the case of a shared amplifier, it can always operate as an MDAC amplifier in the Q1 phase of the clock and as a residual voltage amplifier in the Q2 phase, thereby minimizing the mismatch between the two SAR ADC channels. The clock may utilize an 80 MHz clock.

Each of the SAR ADCs performs sampling for half a period of the clock, performs a SAR operation for the next one period, and performs a residual voltage amplification for the next half period, and the MDAC performs sampling for half a period of the clock And repeats performing the amplification for the next half period, and each SAR ADC can perform the sampling and amplification for one period when another SAR ADC performs the SAR operation.

In the first stage dual-channel SAR ADC, each channel samples the input alternately for every Q1 phase and converts it to a 4-bit digital code via SAR operation. At this time, due to the characteristics of the SAR ADC, when the SAR operation is completed, the residual voltage is automatically left. When this value is Q2 phase, the two channels are alternately amplified 8 times through the residual voltage amplifier, flash1) and MDAC. The subsequent process is performed in the same manner as a general pipelined ADC, so that a 12-bit digital code for the finally input analog signal can be output at a rate of 80 MS / s.

3 illustrates a dual-channel SAR ADC and a shared amplifier according to an embodiment of the present invention.

The SAR ADC used in the first stage is designed as a dual channel as shown in Fig. 3 to ensure sufficient sampling and holding time, and the sampling clock is synchronized to one reference clock to solve the input sampling signal mismatch between channels. In order to stabilize the reference voltage, the reference voltage (reft_sar, refc_sar) used in the SAR operation and the reference voltage (reft_mf, refc_mf) used in the amplification operation can be selectively used according to the operation mode.

For the input switch of the SAR ADC to which the analog input signal is first applied, a gate-bootstrapping switch can be used to minimize the interchannel sampling mismatch and sample the analog input signal without distortion, regardless of the signal size. Also, with the use of a pipelined architecture, the SAR ADC only processes 4 bits, so the number of required unit capacitors is very small compared to a single SAR ADC that handles high resolution. Accordingly, considering a kT / C noise in place of a small unit capacitor, it is possible to mitigate the performance degradation due to capacitor mismatching and parasitic capacitance by using a sufficiently large unit capacitor at a level of 100 fF.

4 illustrates an on-chip clock generation circuit of a pipelined ADC according to an embodiment of the present invention.

A pipelined ADC according to an embodiment of the present invention can perform a SAR operation for determining four bits during a half period of an 80 MHz clock, and a high-speed clock signal of 320 MHz is required for this purpose. This 320 MHz clock can be internally generated through the circuit of FIG. 4 for synchronization with an externally applied 80 MHz main clock and ease of SoC application. At this time, the reference voltage sampling and the preamplifier amplification time can be adjusted as needed so that the clock period and the duty cycle can be controlled from an external 3-bit digital signal so that the circuit operates stably.

5 illustrates a shared amplifier of a pipelined ADC according to an embodiment of the present invention.

One of the two input stages of the shared amplifier is shared by the two SAR ADCs, and the other input stage is connected to the MDAC. The SAR ADC channels connected to the inputs used by the two SAR ADCs may be selected by a CMOS switch external to the amplifier and a portion of the phase may be selected by an overlapping clock, Capacitors can be shared.

More specifically, the shared amplifier uses a two-stage folded-cascode structure having two input stages as shown in FIG. 5 to properly operate in three operation modes while ensuring an output swing range and a high voltage gain of 1 Vp-p or more do. At this time, the three operation modes can consist of a residual voltage amplifier that amplifies the residual voltage of each SAR ADC 8 times and an amplifier used in MDAC. Since the first stage residual voltage amplifier and the second stage MDAC have different specifications, the mismatch between the residual voltage amplifiers of the two SAR ADC channels causes channel mismatches. It causes. There are offset and gain mismatches in the amplifier mismatch that can occur in time-interleaving structures such as the first stage SAR ADC.

In order to solve such a mismatch, the pipelined ADC according to the embodiment of the present invention is shared to the amplifier input terminal when the amplifier is shared. For the input stage, sharing the three amplifiers requires three input pairs in the amplifier, but if each is used separately, a 40 MHz clock line and switch must be added in the amplifier to select the amplifier input used by each SAR ADC channel , A separate feedback capacitor is required for each input stage. Therefore, two input stages are used in the SAR ADC and MDAC, respectively. In the input stage used in the SAR ADC, two channels are used, and each channel can be selected by a CMOS switch external to the amplifier as shown in FIG. This allows the feedback capacitor to be shared by both channels without adding additional circuitry within the amplifier, thereby minimizing possible mismatch between channels. In addition, by using a clock in which a part of the phases are overlapped when selecting two input terminals, it is possible to prevent the amplifier input terminal from being completely turned off so that the amplifier can operate stably.

FIG. 6 conceptually shows separation of a reference voltage driving circuit of a pipelined ADC according to an embodiment of the present invention, and FIG. 7 illustrates a reference voltage generating circuit and a reference current generating circuit in which a voltage driving circuit is separated.

The reference voltage used in the SAR operation and the reference voltage used in the amplification operation of the amplifier may be separated from each other. The reference voltage used in the SAR operation and the reference voltage used in the amplification operation may be divided into a reference voltage The circuit is shared, and the reference voltage driving circuit can be separated.

More specifically, since the SAR ADC and the residual voltage amplifier that internally operate at high speed and the MDAC of the second stage are mixed, when the same reference voltage is used as in the general pipeline structure, The reference voltage settling may become unstable. For the reference voltage used in the amplification operation of the residual voltage amplifier, the signal must be set within 12 bits of the 1/2 least significant bit (LSB) within the half period of the 80 MHz clock. However, at the same timing, the SAR ADC high-speed switching noise caused by the SAR operation makes the reference voltage used in the amplification operation unstable. 6 (b), the reference voltage used in the SAR operation and the reference voltage used in the amplification operation may be separated from each other to prevent mutual interference.

In this case, in order to minimize the mismatch between the reference voltages, only the reference voltage driving circuit which is shared to the reference voltage generating circuit and used for stable signal fixing can be separated as shown in FIG.

On the other hand, the required resolution for the reference voltage used in the SAR operation is as low as 4 bits, but due to the high operating speed of 320 MHz, a voltage driving circuit with a specification completely different from the reference voltage used in the amplification operation is required. Considering this situation, as shown in FIG. 7, a separate capacitor is added between the reft_sar node and the refc_sar node, and the size of the internal RC filter is reduced, thereby improving the area and power efficiency.

Figure 8 illustrates a pipelined ADC implemented on a chip according to an embodiment of the present invention, Figure 9 shows the measured DNL and INL of the ADC of Figure 8, Figure 10 shows the measured FFT spectrum of the ADC of Figure 8, , Figure 11 shows the measured dynamic performance of the ADC of Figure 8.

A pipelined ADC according to an embodiment of the present invention is a 12-bit 80 MS / s ADC manufactured in 0.11um CMOS process and uses a single power supply voltage of 1.1V. 8, and a MOS decoupling capacitor of about 500 pF was integrated in the idle space to stabilize the reference voltage and the power supply voltage.

The total chip area is 1.34mm ² , and the power consumed at an operating speed of 80MS / s is 20.9mW. Also, the measured differential non-linearity (DNL) and integral non-linearity (INL) are 0.56 LSB and 1.35 LSB, respectively, as shown in FIG.

FIG. 10 shows a signal spectrum when a 4 MHz input frequency is applied at a sampling rate of 80 MS / s. From the measurement results, it can be seen that no performance degradation due to offset between channels and gain mismatch occurred. The digital output is downsampled using an internal on-chip divider to minimize the effects of noise on the measurement board due to high-speed operation during measurement. At this time, a clock of 80 MHz was divided by 1/5 so that each channel could be output alternately.

Figure 11 shows the measured dynamic performance according to the sampling and input frequency of the pipelined ADC of Figure 8. Figure 11 (a) shows the signal-to-noise-and-distortion ratio (SNDR) and the spurious-noise ratio (SNDR) measured as a differential input signal with a frequency of 4 MHz is applied when the operating speed of the prototype ADC varies up to 100 MS / SNDR and SFDR are 60.4dB and 66.5dB, respectively, at an operating speed of 80MS / s. 11 (b) shows the SNDR and SFDR when the input frequency is increased at the operating speed of 80 MS / s. The SNDR and SFDR measured when the input signal of the Nyquist frequency is applied show 57.4 dB and 63.9 dB, respectively.

Table 1 summarizes the performance of the measured pipelined ADCs. Table 2 compares the performance of the pipelined ADCs with the previously announced SAR ADCs and SHAs. The pipelined ADC according to the embodiment of the present invention is capable of high-speed high-speed operation compared to the conventional high-resolution SAR ADC and is superior in terms of power consumed in comparison with the pipelined ADC including the SHA. Also, the Nyquist input Show similar dynamic performance in the conditions.

The mobile display system according to an embodiment of the present invention may include the pipelined ADC. The pipeline ADC converts an analog signal including an RGB signal into a digital signal. The mobile display system can be used in portable electronic devices such as smart phones.

Claims (12)

Wherein the first stage is formed by two SAR ADCs implemented as dual channels and the other stage is formed by a first flash ADC and a second flash ADC implemented as a single channel. The method according to claim 1,
Each SAR ADC and MDAC share an amplifier,
Wherein the amplifier alternately performs the residual voltage amplification of the selected SAR ADC and the residual voltage amplification of the MDAC of the two SAR ADCs. 3. The method of claim 2,
Each of the SAR ADCs performs sampling for half a period of the clock, performs an SAR operation for the next one period, repeats performing the residual voltage amplification for the next half period,
The MDAC repeats sampling for half a period of the clock and performing amplification for the next half period,
Wherein each SAR ADC performs the sampling and amplification during one period when another SAR ADC performs the SAR operation. 3. The method of claim 2,
Wherein one of the two input stages of the amplifier is shared by the two SAR ADCs and the other input stage is connected to the MDAC. 5. The method of claim 4,
Wherein a SAR ADC channel coupled to an input stage used by the two SAR ADCs is selected by a CMOS switch external to the amplifier. 5. The method of claim 4,
Wherein the two input stages are selected by a clock in which a portion of the phase is superimposed. 3. The method of claim 2,
Wherein the two SAR ADCs share a feedback capacitor. 3. The method of claim 2,
Wherein the reference voltage used in the SAR operation of the SAR ADC and the reference voltage used in the operation of amplifying the residual voltage of the amplifier are separated from each other. 9. The method of claim 8,
Wherein the reference voltage used in the SAR operation and the reference voltage used in the amplification operation are shared by the reference voltage generation circuit, and the reference voltage drive circuit is separated from the reference voltage generation circuit. The method according to claim 1,
Wherein the first and second flashes reduce the number of preamplifiers using an interpolation technique. The method according to claim 1,
Wherein the second flash ADC is implemented in a two stage structure that first determines the most significant bit and determines the least significant bit. A mobile display system comprising a pipelined ADC according to any one of claims 1 to 11.

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