KR20160109997A - Semiconductor device comprising Analog Digital conveters sharing reference capacitor and System on Chip comprising the same - Google Patents

Abstract

Provided are a semiconductor device having a reduced size, and a system on chip (SoC) comprising the semiconductor device. The semiconductor device comprises: a reference capacitor which receives a reference voltage from a reference voltage generator; a first successive approximation register analog-to-digital converter (SAR ADC) which converts a first analog signal into a first digital signal by using a first sampling capacitor adapted to have a first capacitance and to be connected to the reference capacitor via a first switching element, and a second sampling capacitor adapted to have a second capacitance lower than the first capacitance and to be connected to the reference capacitor via a second switching element; a second SAR ADC which converts a second analog signal into a second digital signal by using a third sampling capacitor adapted to have a third capacitance and to be connected to the reference capacitor via a third switching element, and a fourth sampling capacitor adapted to have a fourth capacitance lower than the third capacitance and to be connected to the reference capacitor via a fourth switching element; and a controller which connects the first switching element and the third switching element to the reference capacitor at different times.

Description

A semiconductor device including a plurality of analog-to-digital converters sharing a reference capacitor, and a SoC including the analog-digital converters sharing a reference capacitor and a system-on-chip (SoC)

The present invention relates to a semiconductor device including an analog-to-digital converter sharing a reference capacitor and an SoC including the same.

An analog-to-digital converter (ADC) is used to generate a sequence of digital codes representing the respective signal levels of an analog signal.

In recent years, a sucessive approximation method has been used in which digital-analog conversion is repeatedly performed to compare data and bits of a digital code are determined.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a reduced size semiconductor device.

Another aspect of the present invention is to provide a system-on-chip (SoC) with reduced size.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device including a reference capacitor for receiving a reference voltage from a reference voltage generator, a first capacitor having a first capacitance, And a second sampling capacitor having a second capacitance less than the first capacitance and connected to the reference capacitor through a second switching element, the first sampling capacitor being connected to the reference capacitor through a second switching element, A third sampling capacitor having a third capacitance and sharing a reference capacitor through a third switching device; and a second sampling capacitor, Using a fourth sampling capacitor having a fourth capacitance that is less than the first capacitance and shares the reference capacitor through the fourth switching device 2 and a second SAR ADC, and the first switching device and a controller connected to the reference capacitor to the switching device 3 different times for converting an analog signal into a second digital signal.

In some embodiments, the first sampling capacitor is used to determine the most significant bit (MSB) of the first digital signal, and the third sampling capacitor may be used to determine the MSB of the second digital signal.

In some embodiments, the capacitance of the reference capacitor may be greater than the capacitance of the first sampling capacitor, and the capacitance of the reference capacitor may be greater than the capacitance of the second sampling capacitor.

In some embodiments, the first analog signal comprises an In phase signal and the second analog signal may comprise a Quadrature phase signal.

In some embodiments, the controller may sequentially connect the first to fourth switching elements to the reference capacitor.

In some embodiments, the controller may connect the third switching element to the reference capacitor while connecting the second switching element to the reference capacitor.

In some embodiments, the controller may include a delay line for providing a control signal to the first switching device and the third switching device.

In some embodiments, a third SAR ADC sharing the reference capacitor with the first and second SAR ADCs, converts the third analog signal to a third digital signal using the reference capacitor and a plurality of third sampling capacitors, And a fourth SAR ADC sharing a reference capacitor with the first through third SAR ADCs, wherein the fourth SAR ADC uses the reference capacitor and the plurality of fourth sampling capacitors to convert the fourth analog signal into a fourth digital signal To a second SAR ADC.

In some embodiments, the first analog signal and the second analog signal include an in-phase signal, and the third analog signal and the fourth analog signal may comprise a quadrature signal.

In some embodiments, a fifth sampling capacitor having a fifth capacitance and sharing the reference capacitor through a fifth switching element, a sixth sampling capacitor having a sixth capacitance less than the fifth capacitance, A third SAR ADC for converting a third analog input signal to a third digital signal using a sixth sampling capacitor sharing the reference capacitor, and a third SAR ADC having a seventh capacitance and for converting the reference capacitor through a seventh switching element Sharing a fourth analog input signal with an eighth sampling capacitor having an eighth capacitance smaller than the seventh capacitance and sharing the reference capacitor through an eighth switching element, Further comprising a fourth SAR ADC for converting the first SAR device, the third switch device, the fifth switch device, and the fourth SAR ADC into a digital signal, Seventh can be connected to the reference capacitor, the switching device at different times.

In some embodiments, the controller may connect the fifth switching element to the reference capacitor while connecting the second switching element to the reference capacitor.

In some embodiments, the controller may connect the seventh switching element to the reference capacitor while connecting the fourth switching element to the reference capacitor.

According to another aspect of the present invention, there is provided a semiconductor device including a reference capacitor provided with a reference voltage from a reference voltage generator, a reference capacitor, and a plurality of first sampling capacitors having different capacitances, A first SAR ADC that converts a first analog signal to a first digital signal; a second SAR ADC that shares the first SAR ADC with the reference capacitor, the second SAR ADC sharing a reference capacitor and a plurality of capacitors having different capacitances, A second SAR ADC for converting a second analog signal to a second digital signal using a second sampling capacitor and a third sampling capacitor having the largest capacitance among the plurality of first sampling capacitors at a first time, And a fourth sampling capacitor having the largest capacitance among the plurality of second sampling capacitors, And a controller for connecting the reference capacitor to the reference capacitor at a second time other than the first time.

In some embodiments, the controller may not connect the fourth sampling capacitor to the reference capacitor while the third sampling capacitor is connected to the reference capacitor.

In some embodiments, the capacitance of the reference capacitor may be greater than the capacitance of the third sampling capacitor, and the capacitance of the reference capacitor may be greater than the capacitance of the fourth sampling capacitor.

In some embodiments, third and fourth SAR ADCs sharing the reference capacitor with the first and second SAR ADCs, using a plurality of fifth sampling capacitors having the reference capacitors and different capacitances, A third SAR ADC for converting a third analog signal to a third digital signal and a fourth SAR converter for converting the fourth analog signal to a fourth digital signal using the reference capacitor and a plurality of sixth sampling capacitors having different capacitances, Wherein the controller connects the sampling capacitor having the largest capacitance among the plurality of fifth sampling capacitors to the reference capacitor at a third time later than the second time, A sampling capacitor having the largest capacitance among the sixth sampling capacitors may be connected to the reference capacitor at a fourth time later than the third time The.

According to another aspect of the present invention, there is provided a semiconductor device including a first input terminal receiving a first analog signal while a sampling signal is at a first level, A first SAR ADC for converting the input first analog signal into a first digital signal using a reference capacitor and a plurality of first sampling capacitors during a first sampling period while receiving a second analog signal while the sampling signal is at the first level Converting the input second analog signal into a second digital signal using the reference capacitor and a plurality of second sampling capacitors shared by the first SAR ADC while the sampling signal is at the second level, SAR ADC and the timing at which the MSB of the first digital signal is determined and the timing at which the MSB of the second digital signal is determined are different from each other And a controller that controls the first and the 2 SAR ADC.

In some embodiments, the controller controls the timing at which the MSB of the first digital signal is determined and the timing at which the MSB of the second digital signal is determined, taking into consideration the length of the interval in which the sampling signal is the second level can do.

In some embodiments, the controller is further configured to determine the LSB (Least Significant Bit) of the second digital signal before the sampling signal is switched from the second level to the first level, Can be controlled.

According to another aspect of the present invention, there is provided a SoC according to an embodiment of the present invention. The SoC includes a receiving unit for receiving first and second analog signals, a first digital converter for converting the first analog signal into a first digital signal using a plurality of first sampling capacitors, A second SAR ADC for converting the second analog signal to a second digital signal using a plurality of second sampling capacitors, a second SAR ADC connected to the first and second SAR ADCs, Providing a voltage to a first sampling capacitor having a largest capacitance among the plurality of first sampling capacitors at a first time, and providing the reference voltage to a second one having the greatest capacitance among the plurality of second sampling capacitors, A reference capacitor providing a sampling capacitor at a second time different from the first time, and a digital signal processing for performing digital signal processing on the first and second digital signals It includes.

In some embodiments, the reference capacitor may be disposed within the SoC.

The details of other embodiments are included in the detailed description and drawings.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention.
2 is a detailed block diagram of the first SAR ADC of FIG.
3 is a block diagram of the timing controller of Fig.
4 is a timing chart for explaining the operation of the semiconductor device according to an embodiment of the present invention.
5 is a view for explaining an effect of a semiconductor device according to an embodiment of the present invention.
6 is a timing chart for explaining the operation of the semiconductor device according to another embodiment of the present invention.
7 is a block diagram of a semiconductor device according to another embodiment of the present invention.
8 is a timing chart for explaining the operation of the semiconductor device according to another embodiment of the present invention.
9 is a block diagram of a semiconductor device according to another embodiment of the present invention.
10 is a timing chart for explaining the operation of the semiconductor device according to still another embodiment of the present invention.
11 is a block diagram of an SoC in accordance with an embodiment of the present invention.
12 is a block diagram of an SoC in accordance with another embodiment of the present invention.
13 is a block diagram of a SoC in accordance with another embodiment of the present invention.
14 is a block diagram of an electronic system including a semiconductor device and SoC according to embodiments of the present invention.
15 to 17 are illustrative semiconductor systems to which a semiconductor device and SoC according to embodiments of the present invention can be applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of the components shown in the figures may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout the specification and "and / or" include each and every combination of one or more of the mentioned items.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms " comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements in addition to the stated element.

Although the first, second, etc. are used to describe various elements or components, it is needless to say that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, it is needless to say that the first element or the constituent element mentioned below may be the second element or constituent element within the technical spirit of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention. 2 is a detailed block diagram of the first SAR ADC of FIG. 3 is a block diagram of the timing controller of Fig.

1 to 3, the semiconductor device 1 includes a first SAR ADC 10, a second SAR ADC 20, a reference voltage generator 30, a timing controller (not shown) 40, and a reference capacitor Cref.

The first SAR ADC 10 and the second SAR ADC 20 can convert an analog signal to a digital signal through a Sucessive Approximation method.

Specifically, the first SAR ADC 10 receives the first analog signal Vin1 and determines each bit of the N-bit (where N is a natural number, for example) first digital signal Dout1 through a successive approximation method And then output it. The second SAR ADC 20 receives the second analog signal Vin2 and determines respective bits of an N-bit (where N is a natural number, for example) second digital signal Dout2 through a successive approximation method, Can be output.

The reference voltage generator 30 may generate a reference voltage required for the conversion operation of the first and second SAR ADCs 10 and 20. Thus, the reference voltage generated through the reference voltage generator 30 may be stored in the reference voltage capacitor Cref.

In this embodiment, the first and second SAR ADCs 10 and 20 may share the reference voltage capacitor Cref with each other. That is, the first and second SAR ADCs 10 and 20 may receive the reference voltage from the same reference voltage capacitor (Cref) and perform the analog-to-digital conversion operation.

This reference voltage is provided to the first and second SAR ADCs 10 and 20 via the reference voltage capacitor Cref so that the reference voltage generator 30 is connected directly to the first and second SAR ADCs 10 and 20, The operational stability of the first and second SAR ADCs 10 and 20 can be improved.

The timing controller 40 can control the timing of the conversion operation of the first and second SAR ADCs 10 and 20. [ Specifically, the timing controller 40 can control the timing at which the first and second SAR ADCs 10 and 20 start the conversion operation. More specifically, the timing controller 40 controls the first SAR ADC 10 and the second SAR ADC 20 so that the timing at which the first SAR ADC 10 starts the converting operation and the timing at which the second SAR ADC 20 starts the converting operation are different from each other. (10, 20). A more detailed description thereof will be described later.

The timing controller 40 receives the conversion operation start signal CS and provides the first timing signal TS1 to the first SAR ADC 10, for example, And to determine the conversion operation timing of the second SAR ADC 20 by providing the second timing signal TS2 to the second SAR ADC 20. [

The timing controller 40 can output the conversion operation end signal CE, for example, when the conversion operation of the first and second SAR ADCs 10 and 20 is completed.

However, this is merely an example for explaining the technical idea of the present invention, and the embodiments of the present invention are not limited to such a configuration.

For example, in some embodiments of the present invention, the timing controller 40 may be embodied in a form that is directly provided with a sampling signal (e.g., S in FIG. 4). In this case, the timing controller 40 can sense the level change of the sampling signal (for example, S in Fig. 4) to control the conversion operation of the first and second SAR ADCs 10 and 20. [

Although the timing controller 40 is shown separately from the first and second SAR ADCs 10 and 20 in FIG. 1 for the sake of convenience, the embodiments of the present invention are not limited thereto. In some embodiments, the timing controller 40 may be implemented within the first and second SAR ADCs 10, 20, for example. That is, these functions may be integrated and implemented in a controller (for example, 14 in FIG. 2) disposed inside the first and second SAR ADCs 10 and 20 to be described later.

Further, in some other embodiments, the timing controller 40 may be implemented as a software module for controlling a controller (e.g., 14 in FIG. 2) included within the first and second SAR ADCs 10, 20 It is possible. That is, the block classification shown in FIG. 1 is for convenience of understanding, and embodiments of the present invention are not limited to such block classification.

2, the first SAR ADC 10 includes a plurality of sampling capacitors C0 to C (N-1), a plurality of sampling switching devices SW0 to SW (N-1), a first switching device (SW), a first capacitor (CD), a second switching device (SWV), a comparator (12), and a controller (14).

The configuration of the second SAR ADC (20 in FIG. 1) may be substantially the same as that of the first SAR ADC 10 described below, and redundant description will be omitted.

Although the plurality of sampling switching elements SW0 to SW (N-1), the first switching element SWD and the second switching element SWV are shown in the form of switches in the drawing, various types of switching elements Device. For example, in some embodiments of the present invention, the plurality of sampling switching elements SW0 to SW (N-1) and the first switching element SWD may be implemented in the form of a multiplexer, Technological thought is not limited to this.

The second switching device SWV may be disposed between an input terminal to which the first sub analog signal Vin1_P is input and a plurality of sampling capacitors C0 to C (N-1). For example, the controller 14 can control the second switching device SWV so that the input terminal to which the first sub analog signal Vin1_P is inputted and the plurality of sampling capacitors C0 to C (N-1) have.

The plurality of sampling switching elements SW0 to SW (N-1) and the first switching element SWD are connected to a plurality of sampling capacitors C0 to C (N-1) and a first capacitor CD and a reference capacitor Cref As shown in FIG. The plurality of sampling switching elements SW0 to SW (N-1) and the first switching element SWD are connected between the plurality of sampling capacitors C0 to C (N-1) and the first capacitors CD and the ground electrodes As shown in FIG. For example, the controller 14 is configured to control the sampling of the plurality of sampling switching elements SW0 to SW (N-1) and the first switching element SWD to be connected to one of the reference capacitor Cref and the ground electrode The switching elements SW0 to SW (N-1) and the first switching element SWD can be controlled.

The plurality of sampling capacitors C0 to C (N-1) may have different capacitances. For example, the plurality of sampling capacitors C0 to C (N-1) according to the present embodiment may be a bianary weighted capacitor. Specifically, when the capacitance of the sampling capacitor C0 is 1C, the capacitance of the sampling capacitor C1 is 2C and the capacitance of the sampling capacitor C (N-1) is ^2N- 1C Lt; / RTI >

The capacitance of the reference capacitor Cref connected to the plurality of sampling capacitors C0 to C (N-1) according to the operation of the plurality of sampling switching elements SW0 to SW (N-1) (C0 to C (N-1)). That is, the capacitance of the reference capacitor Cref is larger than the capacitance of the sampling capacitor C (N-1) having the largest capacitance among the plurality of sampling capacitors C0 to C (N-1) . The reason why the capacitance of the reference capacitor Cref is very large is that the plurality of sampling capacitors C0 to C (N-1) in the analog-to-digital conversion operation using the successive approximation method to be described later share the reference capacitor Cref . Here, it is assumed that the capacitance of the reference capacitor (Cref) is 2 ^N C, but the embodiments of the present invention are not limited thereto.

On the other hand, the capacitance of the first capacitor CD may be 1C, which is the same as the capacitance of the sampling capacitor C0. This first capacitor CD may be necessary to keep the capacitance of the reference capacitor Cref equal to the sum of the capacitances of the plurality of sampling capacitors C0 to C (N-1). Thus, if the capacitances of the plurality of sampling capacitors C0 to C (N-1) are otherwise modified or the capacitances of the reference capacitors Cref are otherwise modified, the first capacitors CD and 1 switching element SWD may be omitted if necessary.

The comparator 12 can compare the voltage of the comparison node Q connected to one end and the second sub analog signal Vin1_N connected to the other end and output the result. In this embodiment, the second sub analog signal Vin1_N is directly inputted to the other terminal of the comparator 12 for convenience of explanation, but the embodiments of the present invention are not limited thereto.

In some other embodiments, a sample and hold circuit (not shown) may be connected to the other end of the comparator 12 for sampling and holding a first analog signal (Vin1 in Fig. 1). Further, in still another embodiment, the other end of the comparator 12 is charged with the second sub analog signal Vin1_N and has a configuration substantially similar to the plurality of sampling capacitors C0 to C (N-1) A plurality of comparison capacitors (not shown) may be connected.

On the other hand, in the present embodiment, the first analog signal (Vin1 in Fig. 1) is provided to the comparator 12 as the first sub analog signal Vin1_P which is a positive signal and the second sub analog signal Vin1_N which is a negative signal However, the embodiments of the present invention are not limited thereto.

The configurations of the plurality of sampling switching elements SW0 to SW (N-1), the first switching element SWD and the second switching element SWV are modified so that the first analog signal (Vin1 in Fig. 1) is provided and the other end of the comparator 12 is connected to the ground electrode, the configuration of the first SAR ADC 10 may be modified and implemented.

The controller 14 can control the plurality of sampling switching elements SW0 to SW (N-1), the first switching element SWD and the second switching element SWV. For example, the controller 14 controls the second switching element SWV to supply the first sub-analog signal Vin1_P at a timing required to sample a first analog signal (Vin1 in Fig. 1) provided from the outside Can be sampled. The controller 14 receives the first timing signal TS1 at the timing of converting the first analog signal (Vin1 in Fig. 1) into the first digital signal Dout1, for example, It is possible to control the elements SW0 to SW (N-1) and the first switching element SWD.

In some implementations, the controller 14 may include a register that sequentially stores the output of the comparator 12, which determines each bit of the first digital signal Dout1. The controller 14 may output the data stored in the register to the first digital signal Dout1.

Although the controller 14 is shown in Fig. 2 as including a register, the embodiments of the present invention are not limited thereto. If necessary, a register (specifically, SAR (Successive Approximation Register) may be implemented in a configuration separate from the controller 14.

3, the timing controller 40 includes a timing signal generator (not shown) for receiving a conversion start signal CS and outputting a first timing signal TS1 and a second timing signal TS2 at different timings 42). The timing signal generator 42 may include, for example, a delay line. However, this is only an example, and the timing signal generator 42 may include other configurations for outputting the first timing signal TS1 and the second timing signal TS2 at different timings.

4 is a timing chart for explaining the operation of the semiconductor device according to an embodiment of the present invention.

1 to 4, in an interval A where the signal level of the sampling signal S is a first level (for example, a logical high level), the first SAR ADC 10 outputs a first analog signal Vin1), and the second SAR ADC 20 may sample the second analog signal Vin2. In some embodiments of the present invention, for example, when the timing controller 40 outputs a conversion operation end signal CE, the first SAR ADC 10 samples the first analog signal Vin1, 2 SAR ADC 20 can sample the second analog signal Vin2.

The operation of the first SAR ADC 10 and the operation of the second SAR ADC 20 may be substantially identical, and only the detailed operation of the first SAR ADC 10 will be described below.

The controller 14 includes a plurality of sampling switching elements SW0 to SW (N-1) and a first switching element SWD for sampling the first analog signal Vin1 by the first SAR ADC 10 It can be connected to the ground electrode, and the second switching device SWV can be turned on. Thereby, the first sub-analog signal Vin1_P is charged in the plurality of sampling capacitors C0 to C (N-1) and the first capacitor CD so that the voltage level of the comparison node Q becomes the first analog signal Vin1). ≪ / RTI >

Next, in a period B where the signal level of the sampling signal S is a second level (for example, a logic low level), the timing controller 40 supplies the first timing signal TS1 to the first SAR ADC 10 As shown in Fig. In some embodiments of the present invention, for example, when the timing controller 40 is provided with the conversion start signal CS, the timing controller 40 determines whether the conversion operation of the first SAR ADC 10 is at a first time The first timing signal TS1 may be output to the first SAR ADC 10 so as to be started at the first timing T1.

The controller 14 provided with the first timing signal TS1 can control the sampling switching element SW (N-1) to connect the sampling capacitor C (N-1) to the reference capacitor Cref have. Accordingly, the voltage level of the comparison node Q can be changed. In some embodiments, in this case, the voltage level of the comparison node Q may be, for example, half the level of the reference voltage.

The comparator 12 can compare the voltage level of the comparative node Q thus fluctuated with the second sub analog signal Vin1_N. If the voltage level of the comparison node Q is larger than the second sub analog signal Vin1_N, the controller 14 controls the sampling switching element SW (N-1) ) May be connected to the ground electrode, and the result output from the comparator 12 may be stored in the register.

Alternatively, when the voltage level of the comparison node Q is smaller than the second sub analog signal Vin1_N, the controller 14 controls the sampling switching element SW (N-1) 1) may be connected to the reference capacitor Cref, and the result output from the comparator 12 may be stored in the register.

By this operation, the MSB (Most Significant Bit, S11 in Fig. 4) of the first digital signal Dout1 can be determined.

Subsequently, the controller 14 sequentially controls the remaining sampling switching elements SW0 to SW (N-2) in the same manner to select the remaining bits of the first digital signal Dout1 (S12 to S1N in Fig. 4 Can be determined. The LSB (Least Significant Bit, S1N in FIG. 4) of the first digital signal Dout1 can be determined last. The analog-to-digital conversion method using the successive approximation method will be understood by those skilled in the art, so that a detailed description thereof will be omitted.

Referring again to FIG. 4, after the timing controller 40 outputs the first timing signal TS1 to the first SAR ADC 10, the conversion operation of the second SAR ADC 20 proceeds to the second time T2, The second timing signal TS2 may be output to the second SAR ADC 20 so that the second timing signal TS2 can be started. The second SAR ADC 20 receiving the second timing signal TS2 can convert the second analog signal Vin2 into the second digital signal Dout2 in the same manner as the first SAR ADC 20 described above have.

Here, the second time T2 may be different from the first time T1. The timing at which the MSB S11 of the first digital signal Dout1 is determined by the first SAR ADC 10 and the timing at which the MSB S21 of the second digital signal Dout2 by the second SAR ADC 20 May be different from each other. Specifically, the second time T2 may be later than the first time T1. The timing at which the MSB S11 of the first digital signal Dout1 is determined by the first SAR ADC 10 is determined by the second SAR ADC 20 by the MSB S21 of the second digital signal Dout2, May be earlier than the timing at which it is determined.

In this embodiment, the timing at which the bits S11 to S1N of the first digital data Dout1 are determined and the timing at which the bits S21 to S2N of the second digital data Dout2 are determined may be different from each other . That is, the timing at which the plurality of sampling switching elements SW0 to SW (N-1) included in the first SAR ADC 10 are controlled and the timing at which the plurality of sampling switching elements SW0 To SW (N-1) may not be overlapped with each other.

5 is a view for explaining an effect of a semiconductor device according to an embodiment of the present invention. 5 is a graph showing the current consumption of a section during which the SAR ADC performs a successive approximation conversion operation.

As described above, the capacitance of the reference capacitor Cref is much larger than the capacitance of the plurality of sampling capacitors C0 to C (N-1). Accordingly, the area occupied by the reference capacitor Cref in the semiconductor device or the semiconductor chip is very large. Therefore, when the first and second SAR ADCs 10 and 20 share the reference capacitor Cref as in the above-described embodiment, the size of the semiconductor device or the semiconductor chip can be greatly reduced. Furthermore, when a plurality of SAR ADCs share a reference capacitor (Cref), the size of the semiconductor device or the semiconductor chip can be further drastically reduced.

Referring to FIG. 5, it can be seen that current consumption peaks P1 to PN occur in a section B in which the SAR ADC performs a successive approximation conversion operation, unlike the sampling section A. FIG. Here, each of the current consumption peaks P1 to PN is the timing at which each bit of the digital data is determined. At the timing when the MSB is determined, the current consumption is the most significant (see current consumption peak P1).

Therefore, if, in the above-described embodiment, the first and second SAR ADCs 10 and 20 share the reference capacitor Cref and the MSBs of the first and second digital signals Dout1 and Dout2 are the same timing , The current consumption peak PX will be formed. Such current consumption may adversely affect the operation characteristics of the semiconductor device or the semiconductor device. Therefore, in this embodiment, the timing at which the MSB is determined by the first and second SAR ADCs 10 and 20 is different, and the current consumption peak PX that can adversely affect the operation characteristics of the semiconductor device or the semiconductor device is Can be prevented.

6 is a timing chart for explaining the operation of the semiconductor device according to another embodiment of the present invention. Hereinafter, differences from the embodiments described above will be mainly described.

Referring to Figures 1, 2 and 6, the timing controller 40 of the semiconductor device 2 is connected to the second SAR ADC 20 at a third time T3 different from the second time (T2 in Figure 4) The third timing signal TS3 may be output to the second SAR ADC 20 so that the second SAR ADC 20 can start the analog-to-digital conversion operation.

Thus, in the embodiment described above, the timing at which each bit S11 to S1N of the first digital data Dout1 is determined and the timing at which each bit S21 to S2N of the second digital data Dout2 is determined The timing at which some bits S12 to S1N of the first digital data Dout1 are determined and the timing at which some bits S21 to S2 (N-1) of the second digital data Dout2 are determined Lt; / RTI >

Specifically, in the above-described embodiment, a plurality of sampling capacitors C0 to C (N-1) included in the first SAR ADC 10 and a plurality of sampling capacitors C0 C (N-2)) of the sampling capacitors included in the first SAR ADC 10 are connected to the reference capacitor Cref through the reference capacitor Cref, A portion (C1 to C (N-1) of the sampling capacitors included in the second SAR ADC 20) may be connected to the reference capacitor Cref. That is, the control timing of the plurality of sampling switching elements SW0 to SW (N-1) of the controller 14 may be different from the above-described embodiment.

7 is a block diagram of a semiconductor device according to another embodiment of the present invention. Hereinafter, differences from the above-described embodiments will be mainly described. 8 is a timing chart for explaining the operation of the semiconductor device according to another embodiment of the present invention.

Referring to Figs. 7 and 8, the timing controller 50 of the semiconductor device 3 may include a timing adjuster 56. Fig.

The timing adjuster 56 starts the conversion operation of the first SAR ADC 10 in consideration of the length (CP) of the section in which the analog-digital conversion operation is performed in the first and second SAR ADCs 10 and 20 Timing and the timing at which the conversion operation of the second SAR ADC 20 is started can be determined.

For example, the timing adjuster 56 may generate a plurality of timing signals and may use the first and second (e.g., logic low level) It is possible to select the fifth and sixth timing signals TS5 and TS6 in which the SAR ADCs 10 and 20 can complete the analog-to-digital conversion operation. That is, the timing adjuster 56 switches the sampling signal S from the second level (for example, the logic low level) to the first level (for example, the logic high level) among the plurality of generated timing signals The fifth and sixth timing signals TS5 and TS6, from which the LSB of the second digital signal Dout2 can be determined, can be selected.

The fifth and sixth timing signals TS5 and TS6 selected by the timing adjuster 56 are provided to the first and second SAR ADCs 10 and 20 by the timing controller 50 so that the first and second SAR The operation of the ADCs 10 and 20 can be controlled. Thus, when the first and second SAR ADCs 10 and 20 are controlled by the fifth and sixth timing signals TS5 and TS6, the analog-to-digital conversion operation can be performed while using the given resources as efficiently as possible. have.

9 is a block diagram of a semiconductor device according to another embodiment of the present invention. 10 is a timing chart for explaining the operation of the semiconductor device according to still another embodiment of the present invention. Hereinafter, differences from the above-described embodiments will be mainly described.

9 and 10, the semiconductor device 4 includes first to fourth SAR ADCs 110, 120, 150 and 160, a reference voltage generator 130, a timing controller 140, And a reference capacitor (Cref) shared by four SAR ADCs 110, 120, 150,

The first to fourth SAR ADCs 110, 120, 150, and 160 may convert an analog signal to a digital signal through a successive approximation method. Specifically, the first and second SAR ADCs 110 and 120 may receive an in-phase signal Vin_I and output a corresponding digital signal Dout_I. The third and fourth SAR ADCs 150 and 160 may receive a quadrature phase signal Vin_Q and output a corresponding digital signal Dout_Q.

In FIG. 9, the first and second SAR ADCs 110 and 120 output a digital signal Dout_I including, for example, 12 bits, and the third and fourth SAR ADCs 150 and 160, for example, , And 12-bit digital signal Dout_Q. However, the embodiments of the present invention are not limited to these examples.

The first SAR ADC 110 and the third SAR ADC 150 may be placed in a first path and the second SAR ADC 120 and the fourth SAR ADC 160 may be placed in a second path Path).

The timing controller 140 may control the operation timing of the first to fourth SAR ADCs 110, 120, 150, Specifically, referring to FIG. 10, in the analog-to-digital conversion operation of the first to fourth SAR ADCs 110, 120, 150, and 160, the timing controller 140 controls the first To fourth SAR ADCs (110, 120, 150, 160). Accordingly, the timing at which the MSBs of the digital signals Dout_I and Dout_Q, which are the outputs of the first to fourth SAR ADCs 110, 120, 150 and 160, are determined may be all different.

11 is a block diagram of an SoC in accordance with an embodiment of the present invention. Hereinafter, differences from the above-described embodiments will be mainly described.

Referring to FIG. 11, the SoC (System on Chip) 5 may include, for example, a modem device 200.

The modem device 200 may include a receiving end 210, a plurality of SAR ADCs 221 to 22m, a reference capacitor Cref, and a digital signal processor 230.

The receiving end 210 can receive the analog signal AS. In some embodiments, the receiving end 210 may receive a plurality of analog signals AS.

The plurality of SAR ADCs 221 to 22m can convert the analog signal AS provided from the receiving end 210 into a digital signal DS using a successive approximation method. As shown, a plurality of SAR ADCs 221-22m may share a reference capacitor (Cref). Although all of the SAR ADCs 221 to 22m share one reference capacitor (Cref) in the drawing, the embodiments of the present invention are not limited thereto. In some other embodiments, a plurality of SAR ADCs 221-22m may be grouped into several groups, and the invention may be modified and implemented such that each grouped group shares one reference capacitor (Cref).

The plurality of SAR ADCs 221 to 22m can start the digital signal conversion operation at different timings. Specifically, the timing at which the MSB of the digital signal DS output from the plurality of SAR ADCs 221 to 22m is determined may be all different.

The digital signal processor 230 may perform a digital operation by receiving the digital signals DS output from the plurality of SAR ADCs 221 to 22m.

Since the plurality of SAR ADCs 221 to 22m share the reference capacitor Cref, the area occupied by the reference capacitor Cref may be very small. Thus, as shown, the reference capacitor Cref may be placed inside the SoC 5 rather than outside the SoC 5.

12 is a block diagram of an SoC in accordance with another embodiment of the present invention.

12, the SoC 6 includes a pixel array 310, a row driver 304, a column driver 308 control module 312, a digital correlation double sampling module 324, an image processor 322, .

The pixel array 310 may have a plurality of pixels arranged in a predetermined number of rows / columns.

Specifically, the pixels located in the row of the pixel array 310 are simultaneously turned on by the row select line, and the pixel signals of each column can be selectively provided to the output line by the column select line. A plurality of row / column select lines may be provided for the entire pixel array 310.

The row driver 304 may selectively activate the row lines in response to the row address decoder 302. The column driver 308 may also selectively activate column select lines in response to the column address decoder 306. Thus, a row / column address may be provided for each pixel of the pixel array 310. [

The control module 312 may control the row address decoder 302 and the column address decoder 306 to select the appropriate row / column select lines for pixel readout.

In particular, the control module 312 may control the row driver 304 and the column driver 308, which apply the driving voltage to each drive transistor of the selected row / column select lines.

The digital correlation double sampling module 324 may perform a digital correlated double sampling process using pixel reset signals and pixel image signals for selected pixels of each column of the pixel array 310. [

The digital correlation dual sampling module 324 includes a sample and hold (S / H) module 314, an amplifier (AMP) module 316, a successive approximation analog-to- digital converter < / RTI > module 318 and an operational memory module 320.

The S / H module 314 is associated with the column driver 308 and may include n S / H devices. In addition, each S / H device may sample and hold a pixel reset signal and a pixel image signal for selected pixels of the pixel array 310. Where n may comprise an integer and may represent the number of columns or a portion thereof.

The amplifier module 316 includes n amplifiers and can amplify the sample and held pixel reset signal and the pixel image signal.

The successive approximation type analog-to-digital conversion device 318 includes n successive approximation analog-to-digital conversion devices 318a, each successive approximation type analog- Can be converted into a digital signal by using the successive approximation method.

The n consecutive approximation analog-to-digital converters 318a may share a reference capacitor Cref. The timing at which the MSB of the digital signal is determined in the n successive approximation analog-to-digital converter 318a may be all different, for example.

The arithmetic memory module 320 includes n arithmetic memories and each arithmetic memory stores a digital pixel reset (MSB) using a most-significant-bit-first calculation The difference between the signal and the digital pixel image signal can be effectively obtained and a digital difference signal can be generated. Here, the MSB preference calculation may include addition or subtraction operations including binary operations.

The image processor 322 processes the digital difference signal provided from the operational memory module 320 to generate an output image color reproduction of the image captured by the plurality of pixels of the pixel array 310 to provide.

In particular, the image processor 322 performs a variety of operations including, for example, positional gain adjustment, defect correction, noise reduction, optical crosstalk reduction, Demosaicing, resizing, sharpening, and the like, but the embodiments of the present invention are not limited thereto.

13 is a block diagram of a SoC in accordance with another embodiment of the present invention.

Referring to FIG. 13, the SoC 1000 may include an application processor 1001 and a DRAM 1060.

The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a multilevel connection bus 1030, a memory system 1040, and a peripheral circuit 1050.

The central processing unit 1010 can perform operations necessary for driving the SoC 1000. [ In some embodiments of the invention, the central processing unit 1010 may be configured in a multicore environment that includes a plurality of cores.

The multimedia system 1020 may be used in the SoC system 1000 to perform various multimedia functions. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like .

The multilevel connection bus 1030 can be used for data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the invention, such a multi-level connection bus 1030 may have a multi-layer structure. For example, a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced Extensible Interface (AXI) may be used as the multi-level connection bus 1030. However, It is not.

The memory system 1040 can be connected to an external memory (for example, DRAM 1060) by the application processor 1001 to provide an environment necessary for high-speed operation. In some embodiments of the invention, the memory system 1040 may include a separate controller (e.g., a DRAM controller) for controlling an external memory (e.g., DRAM 1060).

The peripheral circuit 1050 can provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (e.g., a main board). Accordingly, the peripheral circuit 1050 may include various interfaces for allowing an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as an operation memory required for the application processor 1001 to operate. In some embodiments of the invention, the DRAM 1060 may be located external to the application processor 1001 as shown. Specifically, the DRAM 1060 can be packaged in an application processor 1001 and a package on package (PoP).

At least one of the components of the SoC 1000 may employ any one of the semiconductor device or the SoC according to the embodiments of the present invention described above.

14 is a block diagram of an electronic system including a semiconductor device and SoC according to embodiments of the present invention.

14, an electronic system 1100 includes a controller 1110, an I / O device 1120, a memory device 1130, an interface 1140, and a bus 1150 (bus) . The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

 The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver.

Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an SRAM.

Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

At least one of the components of the electronic system 1100 may employ either the semiconductor device or the SoC according to the embodiments of the present invention described above.

15 to 17 are illustrative semiconductor systems to which a semiconductor device and SoC according to embodiments of the present invention can be applied.

Fig. 15 is a diagram showing a tablet PC 1200, Fig. 16 is a diagram showing a notebook 1300, and Fig. 17 is a diagram showing a smartphone 1400. Fig. At least one of the semiconductor device or the SoC according to the embodiments of the present invention may be used in such a tablet PC 1200, the notebook 1300, the smart phone 1400, and the like.

It will also be apparent to those skilled in the art that the semiconductor device according to some embodiments of the present invention may also be applied to other integrated circuit devices not illustrated. That is, although only the tablet PC 1200, the notebook computer 1300, and the smartphone 1400 have been described as examples of the semiconductor system according to the present embodiment, examples of the semiconductor system according to the present embodiment are not limited thereto. In some embodiments of the invention, the semiconductor system may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a wireless phone, A mobile phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, A digital audio recorder, a digital audio recorder, a digital picture recorder, a digital picture player, a digital video recorder, ), A digital video player, or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10, 20: SAR ADC
Cref: reference capacitor

Claims (20)

A reference capacitor that receives a reference voltage from a reference voltage generator;
A first sampling capacitor having a first capacitance and connected to the reference capacitor through a first switching element and a second capacitor having a second capacitance less than the first capacitance and connected to the reference capacitor via a second switching element, A first SAR ADC (Successive Approximation Registor Analog to Digital Converter) for converting a first analog signal to a first digital signal using a second sampling capacitor connected thereto;
A third sampling capacitor having a third capacitance and sharing the reference capacitor through a third switching element, a third sampling capacitor having a fourth capacitance less than the third capacitance, A second SAR ADC for converting a second analog signal to a second digital signal using a shared fourth sampling capacitor; And
And a controller for connecting the first switching element and the third switching element to the reference capacitor at different times. The method according to claim 1,
Wherein the first sampling capacitor is used to determine the most significant bit (MSB) of the first digital signal and the third sampling capacitor is used to determine the MSB of the second digital signal. The method according to claim 1,
Wherein the capacitance of the reference capacitor is greater than the capacitance of the first sampling capacitor,
Wherein the capacitance of the reference capacitor is greater than the capacitance of the second sampling capacitor. The method according to claim 1,
Wherein the first analog signal comprises an in-phase signal,
Wherein the second analog signal comprises a quadrature phase signal. The method according to claim 1,
Wherein the controller sequentially connects the first to fourth switching elements to the reference capacitor. The method according to claim 1,
The controller connects the third switching element to the reference capacitor while connecting the second switching element to the reference capacitor. The method according to claim 1,
Wherein the controller includes a delay line for providing a control signal to the first switching element and the third switching element. The method according to claim 1,
A third SAR ADC sharing the reference capacitor with the first and second SAR ADCs, the third SAR ADC converting the third analog signal to a third digital signal using the reference capacitor and a plurality of third sampling capacitors, ; And
A fourth SAR ADC sharing the reference capacitor with the first through third SAR ADCs, the fourth SAR ADC converting the fourth analog signal into a fourth digital signal using the reference capacitor and a plurality of fourth sampling capacitors, Further comprising: 9. The method of claim 8,
Wherein the first analog signal and the second analog signal comprise an in-phase signal,
Wherein the third analog signal and the fourth analog signal comprise a quadrature signal. The method according to claim 1,
A fifth sampling capacitor having a fifth capacitance and sharing the reference capacitor through a fifth switching element and a fifth capacitor having a sixth capacitance less than the fifth capacitance and having the reference capacitor through a sixth switching element A third SAR ADC for converting a third analog input signal to a third digital signal using a shared sixth sampling capacitor; And
A seventh sampling capacitor having a seventh capacitance and sharing the reference capacitor through a seventh switching element, and a seventh sampling capacitor having an eighth capacitance smaller than the seventh capacitance and having the eighth switching element, Further comprising a fourth SAR ADC for converting a fourth analog input signal to a fourth digital signal using a shared eighth sampling capacitor,
Wherein the controller connects the first switching element, the third switching element, the fifth switching element, and the seventh switching element to the reference capacitor at different times. 11. The method of claim 10,
And the controller connects the fifth switching element to the reference capacitor while connecting the second switching element to the reference capacitor. 12. The method of claim 11,
And the controller connects the seventh switching element to the reference capacitor while connecting the fourth switching element to the reference capacitor. A reference capacitor receiving a reference voltage from the reference voltage generator;
A first SAR ADC converting the first analog signal to a first digital signal using the reference capacitor and a plurality of first sampling capacitors having different capacitances;
A second SAR ADC sharing the first SAR ADC and the reference capacitor, the second SAR ADC using the reference capacitor and a plurality of second sampling capacitors having different capacitances to convert the second analog signal into a second digital signal A second SAR ADC to convert; And
Connecting a third sampling capacitor having the largest capacitance among the plurality of first sampling capacitors to the reference capacitor at a first time, and connecting a fourth sampling capacitor having the largest capacitance among the plurality of second sampling capacitors to the first sampling capacitor, And connecting the reference capacitor to the reference capacitor at a second time different from the time. 14. The method of claim 13,
The controller does not connect the fourth sampling capacitor to the reference capacitor while the third sampling capacitor is connected to the reference capacitor. 15. The method of claim 14,
Wherein the capacitance of the reference capacitor is greater than the capacitance of the third sampling capacitor,
Wherein a capacitance of the reference capacitor is larger than a capacitance of the fourth sampling capacitor. 14. The method of claim 13,
Third and fourth SAR ADCs sharing the reference capacitor with the first and second SAR ADCs, wherein the third and fourth SAR ADCs use the reference capacitor and a plurality of fifth sampling capacitors having different capacitances, A fourth SAR ADC for converting the fourth analog signal to a fourth digital signal using the reference capacitor and a plurality of sixth sampling capacitors having different capacitances, Further comprising:
Wherein the controller connects the sampling capacitor having the largest capacitance among the plurality of fifth sampling capacitors to the reference capacitor at a third time later than the second time and outputs the sampling clock having the largest capacitance among the plurality of sixth sampling capacitors And a sampling capacitor is connected to the reference capacitor at a fourth time later than the third time. The first analog signal is input while the sampling signal is at the first level and the first analog signal is input to the reference capacitor and the plurality of first sampling capacitors while the sampling signal is at the second level different from the first level A first SAR ADC for converting the first digital signal into a first digital signal;
A reference capacitor for sharing the input second analog signal with the first SAR ADC while the sampling signal is at the second level, and a plurality of reference capacitors for sharing the second analog signal with the reference capacitor while the sampling signal is at the second level, A second SAR ADC for converting the second digital signal into a second digital signal using a second sampling capacitor of the second SAR ADC; And
And controls the first and second SAR ADCs so that the timing at which the MSB (Most Significant Bit) of the first digital signal is determined and the timing at which the MSB of the second digital signal is determined are different from each other. 18. The method of claim 17,
Wherein the controller takes into consideration the length of the section in which the sampling signal is the second level,
And controls the timing at which the MSB of the first digital signal is determined and the timing at which the MSB of the second digital signal is determined. A receiving end for receiving first and second analog signals;
A first SAR ADC for converting the first analog signal to a first digital signal using a plurality of first sampling capacitors;
A second SAR ADC for converting the second analog signal to a second digital signal using a plurality of second sampling capacitors;
Providing a reference voltage at a first time to a first sampling capacitor having a largest capacitance among the plurality of first sampling capacitors, the reference voltage being connected to the first and second SAR ADCs, A reference capacitor for providing a second sampling capacitor having the largest capacitance among the second sampling capacitors of the second sampling capacitor at a second time different from the first time; And
And a digital signal processor for performing digital signal processing on the first and second digital signals. 20. The method of claim 19,
The reference capacitor is disposed in the SoC.

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