CN107786206B - Pipeline SAR-ADC system - Google Patents
Pipeline SAR-ADC system Download PDFInfo
- Publication number
- CN107786206B CN107786206B CN201711228776.9A CN201711228776A CN107786206B CN 107786206 B CN107786206 B CN 107786206B CN 201711228776 A CN201711228776 A CN 201711228776A CN 107786206 B CN107786206 B CN 107786206B
- Authority
- CN
- China
- Prior art keywords
- digital
- successive approximation
- digital conversion
- analog
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 36
- 238000005070 sampling Methods 0.000 claims description 35
- BWSIKGOGLDNQBZ-LURJTMIESA-N (2s)-2-(methoxymethyl)pyrrolidin-1-amine Chemical compound COC[C@@H]1CCCN1N BWSIKGOGLDNQBZ-LURJTMIESA-N 0.000 claims description 20
- 238000003491 array Methods 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a Pipeline SAR-ADC system, which comprises successive approximation type analog-to-digital conversion modules and a register, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the successive approximation type analog-to-digital conversion modules of the N blocks are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register. The successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output. The invention has the advantages of fewer components and parts, is convenient to realize, has low cost, the output rate and the resolution can be improved when the method is applied.
Description
Technical Field
The present invention relates to integration in the technical field of the circuit, the method comprises the steps of, in particular to a Pipeline SAR-ADC system.
Background
Analog-to-digital converters (ADCs) serve as key devices for converting analog signals to digital signals, playing a vital role in the fields of aerospace and defense, automotive applications, software radio, consumer electronics, video surveillance and image acquisition, radar communication, and the like. With the continuous development of modern technology, the requirements of these fields on speed and resolution are continuously raised, and the requirements of an analog-to-digital converter are also higher and higher.
Conventional analog-to-digital converters often employ both a Pipeline-ADC and a SAR-ADC architecture, which suffers from the following drawbacks when applied: the first, pipeline-ADC is greatly affected by capacitance mismatch, which results in a very limited Pipeline-ADC resolution; second, the Pipeline-ADC needs to be equipped with an error correction module, which increases the power consumption and area of the ADC, and limits its application in the field of industrial control and the like. The following disadvantages exist when the SAR-ADC architecture is applied: the SAR-ADC adopts a gradual approximation type voltage comparison method, so that the SAR-ADC cannot be applied to a high-speed environment, namely, the sampling rate of the SAR-ADC is low.
Disclosure of Invention
The invention aims to solve the problems of low resolution and low sampling rate of the traditional analog-to-digital converter, and provides a Pipeline SAR-ADC system which has the advantages of Pipeline and SAR-ADC structure combination and can improve the output rate and the resolution.
The invention solves the problems mainly by the following technical proposal: the Pipeline SAR-ADC system comprises successive approximation type analog-to-digital conversion modules and a register, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the successive approximation type analog-to-digital conversion modules of the N blocks are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register; wherein,
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register;
the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output.
Further, the successive approximation type analog-to-digital conversion module comprises sampling switches, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the number of the sampling switches and the number of the capacitor array are two, the two sampling switches are correspondingly connected with the input ends of the two capacitor arrays one by one, and the output ends of the two capacitor arrays are respectively connected with the in-phase input end and the anti-phase input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
Furthermore, a signal amplifying circuit is arranged on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
In summary, the invention has the following beneficial effects: (1) The invention has the advantages of simple integral structure, few components and parts are used, the implementation is convenient, the cost is low, the invention combines SAR-ADC circuit structure and Pipeline operation mode, which can effectively improve ADC output rate.
(2) The invention adopts a full differential structure, and can reduce noise and interference of capacitance mismatch.
(3) When the invention is applied, the gradual range division is carried out, the full range can be divided from the largest (first stage) to the smallest (N stage), each stage carries out SAR-ADC conversion, and then a Pipeline form recombination output is formed, so that the resolution of the final output is greatly improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a block diagram of one embodiment of the present invention;
FIG. 2 is a block diagram of a successive approximation analog-to-digital conversion module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the overall voltage simulation results according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a partial voltage simulation result according to an embodiment of the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1:
as shown in FIG. 1, the Pipeline SAR-ADC system comprises successive approximation type analog-to-digital conversion modules and registers, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, and the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N steps. In this embodiment, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of the input signals in all the successive approximation type analog-to-digital conversion modules, and the order of the input signals of the N successive approximation type analog-to-digital conversion modules is as follows: the first-order successive approximation type analog-to-digital conversion module, the second-order successive approximation type analog-to-digital conversion module, … … and the Nth-order successive approximation type analog-to-digital conversion module. In the specific setting of this embodiment, signal amplifying circuits are arranged on the lines between any two adjacent successive approximation analog-to-digital conversion modules.
The architecture of fig. 1 shows that the system can significantly increase the analog-to-digital conversion speed compared with a conventional successive approximation digital-to-analog converter by operating N successive approximation digital-to-analog conversion modules in a pipelined manner. Fig. 2 shows that the system is of a differential structure, and compared with a traditional successive approximation type digital-to-analog converter, the differential input differential comparison structure can effectively inhibit the influence of input noise on an output result. In addition, the differential structure can effectively reduce the influence of signal common mode errors on output.
The digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register, and the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the digital signal and transmitting the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output.
When the embodiment is applied, the analog input signal V in Enter first order successive approximation a module for the analog-to-digital conversion, converting analog signal into N by first-order successive approximation analog-to-digital conversion module 1 Bit digital signal D 1 Store to a register. Residual voltage V output by first-order successive approximation type analog-to-digital conversion module o1 Amplified by a signal amplifying circuit to a voltage V i2 Voltage V i2 Converting the analog signal into N by a second-order successive approximation analog-to-digital conversion module 2 Bit digital signal D 2 The residual voltage is stored in a register and output by a second-order successive approximation type analog-digital conversion moduleV o2 Amplified by a signal amplifying circuit to a voltage V i3 . And so on, in the last order of input signal V iN After entering an Nth order successive approximation type analog-to-digital conversion module, converting an analog signal into N n Bit digital signal D n . Finally D 1 ，D 2 …D n In Pipeline form to form an output (N 1 +N 2 +…+N n ) Bit digital signal D out 。
Example 2:
as shown in fig. 2, this embodiment is further defined on the basis of embodiment 1 as follows: the successive approximation type analog-to-digital conversion module of the embodiment comprises a sampling switch, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the capacitor array is provided with IN, OUT, G, H, L and C 1-N Pin, logic control module is provided with IN, OUT, CLK, C 1(1-N) C (C) 2(1-N) Pins. In this embodiment, the number of sampling switches and capacitor arrays is two, and the two sampling switches are sampling switch SAMP respectively 1 And sampling switch SAMP 2 Sampling switch SAMP 1 And sampling switch SAMP 2 Respectively connected with the IN input ends of the two capacitor arrays IN one-to-one correspondence, and inputs voltage V ip(t) By sampling switch SAMP 1 Input, input voltage V in(t) By sampling switch SAMP 2 And (5) inputting. The OUT output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator. The output end of the comparator is connected with the IN input end of the logic control module, and the C of the logic control module 1(1-N) Digital control output end and C of capacitor array 1-N The digital bit control input end is connected with the C of the logic control module 2(1-N) C of digital control output end and another capacitor array 1-N The digital bit control input end is connected, and the OUT output end of the logic control module is connected with the input end of the output buffer module.
When the embodiment is applied, the H ends of the two capacitor arrays are input with reference high voltage V refH L ends of the two capacitor arrays are input with reference low voltage V refL G ends of the two capacitor arrays are input with ground voltage GND, and logic control is performedThe CLK Clock input of the module inputs the Clock signal. Sampling switch SAMP during sampling phase 1 SAMP of sampling switch 2 Closing, differential positive input voltage V ip(t) By sampling switch SAMP 1 Form V ip(z) Enters a capacitor array, and the negative end inputs voltage V in(t) By sampling switch SAMP 2 Form V in(z) Into another capacitor array. During the comparison phase, sampling switch SAMP 1 SAMP of sampling switch 2 The comparator CMP compares the output voltages V of the two capacitive arrays p And V n To determine the output logic D of the comparator CMP cmp Input to the logic control module. According to the output voltage value, the input end of IN of the logic control module is input to the logic control module, and the logic control module is connected with the input end of IN of the logic control module from C 1(1-N) Output control signal of corresponding digital position to control port C of a capacitor array 1-N And from C 2(1-N) Output control signal of corresponding digital position to control port C of another capacitor array 1-N And further eliminating the charges stored in the two capacitor arrays corresponding to the digital positions, and simultaneously recording the corresponding digital data of the digital positions. After completing the comparison procedure, the logic control module sequentially and circularly eliminates the charges stored in the capacitor array in the same way to complete the output data of all digital positions, and finally outputs the final digital data D in the form of pipeline out . The output buffer module can be selectively added to output the buffer signal D according to specific requirements bout 。
The present embodiment applies and implements a 16-bit Pipeline SAR-ADC system with a sampling rate of 33kHz, a reference voltage of 2.5V, and an input signal varying from 0V to 2.5V. The output result is that the significant bit number (ENOB) reaches 16 bits, the Integral Nonlinearity (INL) is less than 0.5LSB, and the Differential Nonlinearity (DNL) is less than 0.5LSB. Fig. 3 and 4 are simulation diagrams of one example application of the circuit. The simulation method is that the output digital signal of the 16-bit Pipeline SAR-ADC system passes through an ideal DAC, and the analog signal output by the DAC is compared with the input analog signal. Wherein the upper line in the coordinate system shown in fig. 3 is the voltage input signal varying from 0V to 2.5V and the lower line is the analog signal converted by the circuit from the output digital signal. As can be seen from fig. 3, the voltage output signal of the circuit varies linearly and substantially coincides with the voltage input signal. Fig. 4 is a graph of the results of a partial voltage simulation, with flatter lines being the input analog signals and more tortuous lines being the analog signals converted from the output digital signals. As can be seen from the figure, the analog signal converted from the output digital signal is substantially stepped, in accordance with expectations.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (1)
1. The Pipeline SAR-ADC system is characterized by comprising successive approximation analog-to-digital conversion modules, a signal amplifying circuit and a register, wherein the number of the successive approximation analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation analog-to-digital conversion modules are sequentially connected to form N steps, the order of each successive approximation analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation analog-to-digital conversion modules, and the digital output end of each successive approximation analog-to-digital conversion module is connected with the input end of the register; a signal amplifying circuit is arranged on a line between any two adjacent successive approximation type analog-to-digital conversion modules; wherein,
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register;
the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output;
analog input signal V in Enter a first-order successive approximation type analog-to-digital conversion moduleThe analog signal is converted into N by a first-order successive approximation type analog-to-digital conversion module 1 Bit digital signal D 1 Storing the data in a register; residual voltage V output by first-order successive approximation type analog-digital conversion module o1 Amplified by a signal amplifying circuit to a voltage V i2 Voltage V i2 Converting the analog signal into N by a second-order successive approximation analog-to-digital conversion module 2 Bit digital signal D 2 The residual voltage V output by the second-order successive approximation type analog-digital conversion module is stored in a register o2 Amplified by a signal amplifying circuit to a voltage V i3 And so on, the Nth-order successive approximation type analog-to-digital conversion module converts the analog signal into N n Bit digital signal D n Storing the data in a register; the register combines the digital signals output by the N-order successive approximation type analog-to-digital conversion module to output a digital signal D in a Pipeline form out ，D out Altogether N 1 +N 2 +…+N n ) A bit;
the successive approximation type analog-to-digital conversion module comprises sampling switches, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the number of the sampling switches and the number of the capacitor array are two, the two sampling switches are connected with the input ends of the two capacitor arrays in a one-to-one correspondence manner, and the output ends of the two capacitor arrays are respectively connected with the in-phase input end and the anti-phase input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module;
capacitor array is provided with IN, OUT, G, H, L and C 1-N Pin, logic control module is provided with IN, OUT, CLK, C 1(1-N) C (C) 2(1-N) Pins; the two sampling switches are sampling switch SAMP respectively 1 And sampling switch SAMP 2 ；
H-end input reference high voltage V of two capacitor arrays refH L ends of the two capacitor arrays are input with reference low voltage V refL The G ends of the two capacitor arrays are input with ground voltage GND, and the CLK clock input of the logic control moduleThe input end inputs a Clock signal; sampling switch SAMP during sampling phase 1 SAMP of sampling switch 2 Closing, differential positive input voltage V ip（t） By sampling switch SAMP 1 Form V ip（z） Enters a capacitor array, and the negative end inputs voltage V in(t) By sampling switch SAMP 2 Form V in（z） Entering another capacitor array; during the comparison phase, sampling switch SAMP 1 SAMP of sampling switch 2 The comparator CMP compares the output voltages V of the two capacitive arrays p And V n To determine the output logic D of the comparator CMP cmp Inputting the data to a logic control module; according to the output voltage value, the input end of IN of the logic control module is input to the logic control module, and the logic control module is connected with the input end of IN of the logic control module from C 1(1-N) Output control signal of corresponding digital position to control port C of a capacitor array 1-N And from C 2(1-N) Output control signal of corresponding digital position to control port C of another capacitor array 1-N Further eliminating charges stored in the two capacitor arrays corresponding to the digital position, and simultaneously recording corresponding digital data of the digital position; after the comparison procedure is completed, the logic control module sequentially and circularly eliminates the charges stored in the capacitor array in the same way to complete the output data of all digital positions, and finally outputs the final digital data D in the form of pipeline out 。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711228776.9A CN107786206B (en) | 2017-11-29 | 2017-11-29 | Pipeline SAR-ADC system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711228776.9A CN107786206B (en) | 2017-11-29 | 2017-11-29 | Pipeline SAR-ADC system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107786206A CN107786206A (en) | 2018-03-09 |
| CN107786206B true CN107786206B (en) | 2024-02-02 |
Family
ID=61431308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711228776.9A Active CN107786206B (en) | 2017-11-29 | 2017-11-29 | Pipeline SAR-ADC system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107786206B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995268B (en) * | 2019-12-24 | 2023-06-20 | 中山大学 | Multi-order successive approximation type n bit analog-to-digital converter |
| CN115328386B (en) * | 2022-08-26 | 2023-08-01 | 无锡众享科技有限公司 | ADC module control architecture based on time slot control |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8659461B1 (en) * | 2012-11-13 | 2014-02-25 | University Of Macau | Analog to digital converter circuit |
| US8749412B1 (en) * | 2013-03-06 | 2014-06-10 | Jin-Shy Tsai | Anti-noise successive approximation analog to digital conversion method |
| CN103888141A (en) * | 2014-04-09 | 2014-06-25 | 华为技术有限公司 | Assembly line successive approximation type analog-digital converter self-calibration method and device |
| CN104124971A (en) * | 2013-11-08 | 2014-10-29 | 西安电子科技大学 | Two-stage pipelined analog-digital converter based on successive approximation principle |
| CN104168025A (en) * | 2014-08-25 | 2014-11-26 | 西安交通大学 | Charge type assembly line successive approximation register analog to digital converter |
| CN104320141A (en) * | 2014-10-21 | 2015-01-28 | 华南理工大学 | Low-power-consumption 12-bit assembly line successive approximation analog-digital converter |
| US9219492B1 (en) * | 2014-09-19 | 2015-12-22 | Hong Kong Applied Science & Technology Research Institute Company, Limited | Loading-free multi-stage SAR-assisted pipeline ADC that eliminates amplifier load by re-using second-stage switched capacitors as amplifier feedback capacitor |
| CN105897272A (en) * | 2016-03-30 | 2016-08-24 | 豪威科技(上海)有限公司 | Successive approximation register analog-to-digital converter and control method thereof |
| CN106209102A (en) * | 2016-06-27 | 2016-12-07 | 合肥工业大学 | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter |
| CN207410329U (en) * | 2017-11-29 | 2018-05-25 | 四川知微传感技术有限公司 | Pipeline SAR-ADC device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017137078A1 (en) * | 2016-02-10 | 2017-08-17 | Telefonaktiebolaget Lm Ericsson (Publ) | Leakage compensation for a successive approximation analog-to-digital converter |
-
2017
- 2017-11-29 CN CN201711228776.9A patent/CN107786206B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8659461B1 (en) * | 2012-11-13 | 2014-02-25 | University Of Macau | Analog to digital converter circuit |
| US8749412B1 (en) * | 2013-03-06 | 2014-06-10 | Jin-Shy Tsai | Anti-noise successive approximation analog to digital conversion method |
| CN104124971A (en) * | 2013-11-08 | 2014-10-29 | 西安电子科技大学 | Two-stage pipelined analog-digital converter based on successive approximation principle |
| CN103888141A (en) * | 2014-04-09 | 2014-06-25 | 华为技术有限公司 | Assembly line successive approximation type analog-digital converter self-calibration method and device |
| WO2015154671A1 (en) * | 2014-04-09 | 2015-10-15 | 华为技术有限公司 | Self-calibration method and device for pipeline successive approximation type analogue to digital convertor |
| CN104168025A (en) * | 2014-08-25 | 2014-11-26 | 西安交通大学 | Charge type assembly line successive approximation register analog to digital converter |
| US9219492B1 (en) * | 2014-09-19 | 2015-12-22 | Hong Kong Applied Science & Technology Research Institute Company, Limited | Loading-free multi-stage SAR-assisted pipeline ADC that eliminates amplifier load by re-using second-stage switched capacitors as amplifier feedback capacitor |
| CN104320141A (en) * | 2014-10-21 | 2015-01-28 | 华南理工大学 | Low-power-consumption 12-bit assembly line successive approximation analog-digital converter |
| CN105897272A (en) * | 2016-03-30 | 2016-08-24 | 豪威科技(上海)有限公司 | Successive approximation register analog-to-digital converter and control method thereof |
| CN106209102A (en) * | 2016-06-27 | 2016-12-07 | 合肥工业大学 | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter |
| CN207410329U (en) * | 2017-11-29 | 2018-05-25 | 四川知微传感技术有限公司 | Pipeline SAR-ADC device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107786206A (en) | 2018-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10135457B2 (en) | Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter | |
| CN107769784B (en) | Oversampling type Pipeline SAR-ADC system | |
| CN102045067B (en) | Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC | |
| US8947286B2 (en) | Analog/digital converter | |
| TWI467924B (en) | Successive approximation register analog to digital converter and conversion method thereof | |
| US9219489B2 (en) | Successive approximation register analog-to-digital converter | |
| WO2016127824A1 (en) | Binary capacitor array applied to single-terminal sar adc and redundancy calibrating method therefor | |
| CN111654285B (en) | Digital background calibration method for capacitor mismatch and gain error of pipeline SAR ADC | |
| Fan et al. | High-resolution SAR ADC with enhanced linearity | |
| TWI788816B (en) | Signal conversion circuit utilizing switched capacitors | |
| EP3567720B1 (en) | Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage | |
| CN111034052B (en) | Method and apparatus for enabling a wide input common mode range in a SAR ADC without additional active circuitry | |
| CN104283562A (en) | Successive approximation type analog-to-digital conversion device | |
| JP2015171087A (en) | Analog/digital conversion circuit | |
| Cao et al. | A 91.0-dB SFDR single-coarse dual-fine pipelined-SAR ADC with split-based background calibration in 28-nm CMOS | |
| CN107786206B (en) | Pipeline SAR-ADC system | |
| CN104753533B (en) | One kind is classified shared binary channels flow-line modulus converter | |
| CN114978165A (en) | Time-interleaved pipelined successive approximation analog-to-digital converter | |
| CN110176930B (en) | Multi-position resolution sub-pipeline structure for measuring jump height of transmission curve | |
| CN207410329U (en) | Pipeline SAR-ADC device | |
| US20230208427A1 (en) | Successive approximation register analog-to-digital converter | |
| CN207504850U (en) | Oversampling type Pipeline SAR-ADC device | |
| TWI739722B (en) | Analog-to-digital converter and method of operating same | |
| CN108075778B (en) | Pipeline SAR-ADC circuit structure | |
| CN113037289A (en) | Assembly line analog-to-digital converter based on high-linearity low-power amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |