CN107769784B - Oversampling type Pipeline SAR-ADC system - Google Patents
Oversampling type Pipeline SAR-ADC system Download PDFInfo
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Abstract
The invention discloses an oversampling Pipeline SAR-ADC system, which comprises an oversampling switch, an analog-to-digital conversion system and a digital bit expansion system which are sequentially connected, wherein the analog-to-digital conversion system comprises successive approximation analog-to-digital conversion modules and a register, the number of the successive approximation analog-to-digital conversion modules is N, N is a positive integer which is more than or equal to 2, the N successive approximation analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation analog-to-digital conversion modules, and the digital output end of each successive approximation analog-to-digital conversion module is connected with the input end of the register. The digital bit expansion system comprises a digital bit increasing module and a clock control module, wherein the digital bit increasing module comprises a cascade integral comb filter and a moving average filter connected with the cascade integral comb filter. The invention has the advantages of fewer components, convenient realization, low cost and capability of improving the output rate and resolution ratio during application.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an oversampling Pipeline SAR-ADC system.
Background
Analog-to-digital converters (ADCs) serve as key devices for converting analog signals to digital signals, playing a vital role in the fields of aerospace and defense, automotive applications, software radio, consumer electronics, video surveillance and image acquisition, radar communication, and the like. With the continuous development of modern technology, the requirements of these fields on speed and resolution are continuously raised, and the requirements of an analog-to-digital converter are also higher and higher.
Conventional analog-to-digital converters often employ both a Pipeline-ADC and a SAR-ADC architecture, which suffers from the following drawbacks when applied: the first, pipeline-ADC is greatly affected by capacitance mismatch, which results in a very limited Pipeline-ADC resolution; second, the Pipeline-ADC needs to be equipped with an error correction module, which increases the power consumption and area of the ADC, and limits its application in the field of industrial control and the like. The following disadvantages exist when the SAR-ADC architecture is applied: the SAR-ADC adopts a gradual approximation type voltage comparison method, so that the SAR-ADC cannot be applied to a high-speed environment, namely, the sampling rate of the SAR-ADC is low.
Disclosure of Invention
The invention aims to solve the problems of low resolution and low sampling rate of the traditional analog-to-digital converter, and provides an oversampling Pipeline SAR-ADC system which has the advantage of combining Pipeline and SAR-ADC structures and can improve the output rate and the resolution.
The invention solves the problems mainly by the following technical proposal: the over-sampling Pipeline SAR-ADC system comprises an over-sampling switch, an analog-to-digital conversion system and a digital bit-expansion system which are sequentially connected, wherein the analog-to-digital conversion system comprises successive approximation analog-to-digital conversion modules and a register, the number of the successive approximation analog-to-digital conversion modules is N, N is a positive integer which is more than or equal to 2, the N successive approximation analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation analog-to-digital conversion modules, and the digital output end of each successive approximation analog-to-digital conversion module is connected with the input end of the register; the digital bit expansion system comprises a digital bit addition module and a clock control module, wherein the digital bit addition module comprises a cascade integral comb filter and a moving average filter connected with the cascade integral comb filter; wherein, the liquid crystal display device comprises a liquid crystal display device,
the oversampling switch is used for inputting the analog signal and outputting the sampled analog signal;
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the digital signal and sending the digital signal to the register, wherein the signal input by the first-order successive approximation type analog-to-digital conversion module is a signal output by the oversampling switch;
the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output;
the clock control module is used for providing clock signals for the cascade integration comb filter and the moving average filter;
the cascade integration comb filter is used for receiving a clock signal sent by the clock control module, receiving a digital code output by the register when receiving a trigger start clock signal, then integrating and reducing frequency, and realizing increment of digits in the integration process;
and the moving average filter is used for receiving the clock signal sent by the clock control module, removing clock jitter and inherent noise of the output digital code of the cascade integral comb filter when receiving the trigger starting clock signal so as to realize smooth output.
When the invention is applied, the digital bit adding module and the clock control module are used for completing high-precision output. In practice, the process of accumulating the digital codes through the cascaded integrator-comb filters achieves an increase in the number of bits without requiring a large number of storage elements.
Further, the successive approximation type analog-to-digital conversion module comprises sampling switches, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the number of the sampling switches and the number of the capacitor array are two, the two sampling switches are correspondingly connected with the input ends of the two capacitor arrays one by one, and the output ends of the two capacitor arrays are respectively connected with the in-phase input end and the anti-phase input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
Furthermore, a signal amplifying circuit is arranged on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
Further, the cascade integrator-comb filter is formed by cascading a plurality of single-stage CIC filters.
Further, the CIC filter comprises an integrator, a decimator and a differentiator, which are connected in sequence.
In summary, the invention has the following beneficial effects: (1) The invention has simple integral structure, fewer used components, convenient realization and low cost, and can effectively improve the output rate of the ADC by combining the SAR-ADC circuit structure with a Pipeline operation mode.
(2) The invention adopts a full differential structure and a digital bit expansion technology, and can reduce noise and interference of capacitance mismatch.
(3) When the invention is applied, the gradual range division is carried out, the full range can be divided from the largest (first stage) to the smallest (N stage), each stage carries out SAR-ADC conversion, and then a Pipeline form recombination output is formed, so that the resolution of the final output is greatly improved.
(4) The invention is not influenced by the change of the power supply voltage while improving the resolution, and finally realizes the output with high resolution and high linearity, thereby being beneficial to popularization and application of the invention.
(5) The invention can be suitable for a plurality of bit widths with different inputs when in application, so that the invention is more convenient to popularize and apply when in application.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of an embodiment of the present invention;
FIG. 2 is a block diagram of an analog-to-digital conversion system in accordance with one embodiment of the present invention;
FIG. 3 is a block diagram of the successive approximation type analog-to-digital conversion module of FIG. 2;
FIG. 4 is a block diagram of the digital spreading system of FIG. 1;
FIG. 5 is a schematic diagram of the cascaded integrator-comb filter of FIG. 4;
FIG. 6 is a block diagram of a single stage CIC filter;
FIG. 7 is a block diagram of an application of an embodiment of the present invention;
fig. 8 is a simulation diagram of an embodiment of the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1:
as shown in fig. 1 and fig. 2, an oversampling Pipeline SAR-ADC system includes an oversampling switch, an analog-to-digital conversion system and a digital bit-expansion system which are sequentially connected, where the analog-to-digital conversion system includes a successive approximation analog-to-digital conversion module and a register, where the number of the successive approximation analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, and the N successive approximation analog-to-digital conversion modules are sequentially connected to form N orders. In this embodiment, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of the input signals in all the successive approximation type analog-to-digital conversion modules, and the order of the input signals of the N successive approximation type analog-to-digital conversion modules is as follows: the first-order successive approximation type analog-to-digital conversion module, the second-order successive approximation type analog-to-digital conversion module, … … and the Nth-order successive approximation type analog-to-digital conversion module. In the specific setting of this embodiment, signal amplifying circuits are arranged on the lines between any two adjacent successive approximation analog-to-digital conversion modules. The oversampling switch of the embodiment is used for inputting and outputting the analog signal after sampling, and the signal input by the first-order successive approximation type analog-digital conversion module is the signal output by the oversampling switch.
The Pipeline SAR-ADC system comprises successive approximation type analog-to-digital conversion modules and registers, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the successive approximation type analog-to-digital conversion modules of the N are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of each register; the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output.
The digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register, and the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the digital signal and transmitting the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output.
As shown in fig. 4 and 5, the digital bit expansion system of the present embodiment includes a digital bit adding module and a clock control module, where the digital bit adding module includes a cascaded integrator-comb filter and a moving average filter connected to the cascaded integrator-comb filter. The clocks of both the cascaded integrator-comb filter and the moving average filter of the present embodiment are connected to the clock signal terminal clk of the clock control module, which is configured to provide clock signals to both the cascaded integrator-comb filter and the moving average filter. The cascade integrating comb filter of the embodiment is used for receiving the clock signal sent by the clock control module, receiving the digital code output by the register when receiving the trigger start clock signal, then integrating and reducing frequency, and increasing the number of bits in the integrating process. The moving average filter of the embodiment is used for receiving the clock signal sent by the clock control module, and removing clock jitter and inherent noise of the output signal of the cascade integral comb filter when receiving the trigger start clock signal so as to realize smooth output.
The cascaded integrator-comb filter of this embodiment is formed by cascading a plurality of single-stage CIC filters, wherein the single-stage CIC filters are structured as shown in fig. 6. The CIC filter comprises an integrator, a decimator and a differentiator, which are connected in sequence.
The single stage CIC filter in this embodimentThe extraction multiple is D, the time domain expression of the integrator is y 1 (n)＝y 1 (n-1)+x 1 (n) the time domain expression of the differentiator is y 2 (n)＝x 2 (n)-x 2 (n-D) wherein x 1 (n) is the digital code input by the integrator, y 1 (n) is the digital code output by the integrator, x 2 (n) is the digital code input by the differentiator, y 2 And (n) is a digital code output by the differentiator. The cascade integral comb filter is to complete the integral and the down-conversion of single-stage CIC multi-stage cascade, and the integral process of each stage has increment of corresponding digits, and the increment digits areThe Q-stage CIC filters are connected in series to obtain the expression of the total output digital quantity and digit number as B out ＝Qlog 2 D+B in Wherein Q is the cascade number, and Bin is the bit width of the input signal. Thus, the expansion of the bit number is realized, and the output frequency is reduced by D times. The moving average filter of the embodiment is mainly used for improving the reliability and the precision of system output, reasonably removing errors caused by inherent noise of a circuit and clock jitter, ensuring that the accuracy of data is not reduced, improving the resolution and smoothing the output. The time domain expression of the moving average filter is +.>Where n is the size of the moving average window, y 3 And (n) is a digital code output by the moving average filter.
When the embodiment is applied, the input of the cascade integrator-comb filter is b 0 、……、b m Output ofThe output end of the moving average filter is +.>The final realized digital bit increase is (1/2+Qlog 2 D) Bits.
When the embodiment is applied, the analog input signal x (t) is oversampledThe mode (sampling frequency far away from the bandwidth of the signal) is sampled into x (z) through a switch OVERSAMP, the x (z) enters a first-order successive approximation type analog-to-digital conversion module, and the analog signal is converted into N through the first-order successive approximation type analog-to-digital conversion module 1 Bit digital signal D 1 Store to a register. Residual voltage V output by first-order successive approximation type analog-to-digital conversion module o1 Amplified by a signal amplifying circuit to a voltage V i2 Voltage V i2 Converting the analog signal into N by a second-order successive approximation analog-to-digital conversion module 2 Bit digital signal D 2 The residual voltage V is stored in a register and output by a second-order successive approximation type analog-digital conversion module o2 Amplified by a signal amplifying circuit to a voltage V i3 . And so on, in the last order of input signal V iN After entering an Nth order successive approximation type analog-to-digital conversion module, converting an analog signal into N n Bit digital signal D n . Finally, after the N-bit digital output signal x (N) enters the digital bit expansion system, the digital bit expansion system expands the N-bit digital signal x (N) into (N+M) bits, and finally outputs an (N+M) bit digital analog-to-digital conversion digital signal ADC (N).
As shown in fig. 7, the present embodiment applies and implements a 24-bit analog-to-digital converter (24-bit ADC). The analog input signal x (t) is sampled into x (z) by an oversampling switch and enters an analog-to-digital conversion system, the analog-to-digital conversion system converts the x (z) into a 16-bit digital signal, the 16-bit digital signal is lifted into a 24-bit digital signal by a digital bit expansion system, and finally the 24-bit digital analog-to-digital conversion digital signal is output. The 24 bit oversampling Pipeline SAR-ADC system samples 33kHz, the reference voltage is 2.5V, and the input signal is changed from 0V to 2.5V. The output result is that the significant bit number (ENOB) reaches 16 bits, the Integral Nonlinearity (INL) is less than 0.5LSB, and the Differential Nonlinearity (DNL) is less than 0.5LSB. The 24 bit oversampling Pipeline SAR-ADC system shown in fig. 8 is a simulation diagram, in which the output digital signal of the 24 bit oversampling Pipeline SAR-ADC system is passed through an ideal DAC, and the analog signal output from the DAC is compared with the input analog signal. Wherein the upper line in the coordinate system shown in fig. 8 is the voltage input signal varying from 0V to 2.5V and the lower line is the analog signal converted by the circuit from the output digital signal. As can be seen from fig. 8, the voltage output signal of the circuit varies linearly and substantially coincides with the voltage input signal.
Example 2:
this embodiment is further defined on the basis of embodiment 1 as follows: the successive approximation type analog-to-digital conversion module of the embodiment comprises a sampling switch, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the capacitor array is provided with IN, OUT, G, H, L and C 1-N Pin, logic control module is provided with IN, OUT, CLK, C 1(1-N) C (C) 2(1-N) Pins. In this embodiment, the number of sampling switches and capacitor arrays is two, and the two sampling switches are sampling switch SAMP respectively 1 And sampling switch SAMP 2 Sampling switch SAMP 1 And sampling switch SAMP 2 Respectively connected with the IN input ends of the two capacitor arrays IN one-to-one correspondence, and inputs voltage V ip(t) By sampling switch SAMP 1 Input, input voltage V in(t) By sampling switch SAMP 2 And (5) inputting. The OUT output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator. The output end of the comparator is connected with the IN input end of the logic control module, and the C of the logic control module 1(1-N) Digital control output end and C of capacitor array 1-N The digital bit control input end is connected with the C of the logic control module 2(1-N) C of digital control output end and another capacitor array 1-N The digital bit control input end is connected, and the OUT output end of the logic control module is connected with the input end of the output buffer module.
When the embodiment is applied, the H ends of the two capacitor arrays are input with reference high voltage V refH L ends of the two capacitor arrays are input with reference low voltage V refL The G ends of the two capacitor arrays are input with ground voltage GND, and the CLK Clock input end of the logic control module is input with Clock signal. Sampling switch SAMP during sampling phase 1 SAMP of sampling switch 2 Closing, differential positive input voltage V ip(t) By sampling switch SAMP 1 Form V ip(z) Enters a capacitor array, and the negative end inputs voltage V in(t) By samplingSwitch SAMP 2 Form V in(z) Into another capacitor array. During the comparison phase, sampling switch SAMP 1 SAMP of sampling switch 2 The comparator CMP compares the output voltages V of the two capacitive arrays p And V n To determine the output logic D of the comparator CMP cmp Input to the logic control module. According to the output voltage value, the input end of IN of the logic control module is input to the logic control module, and the logic control module is connected with the input end of IN of the logic control module from C 1(1-N) Output control signal of corresponding digital position to control port C of a capacitor array 1-N And from C 2(1-N) Output control signal of corresponding digital position to control port C of another capacitor array 1-N And further eliminating the charges stored in the two capacitor arrays corresponding to the digital positions, and simultaneously recording the corresponding digital data of the digital positions. After completing the comparison procedure, the logic control module sequentially and circularly eliminates the charges stored in the capacitor array in the same way to complete the output data of all digital positions, and finally outputs the final digital data D in the form of pipeline out . The output buffer module can be selectively added to output the buffer signal D according to specific requirements bout 。
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (5)
1. The oversampling Pipeline SAR-ADC system is characterized by comprising an oversampling switch, an analog-to-digital conversion system and a digital bit expansion system which are sequentially connected, wherein the analog-to-digital conversion system comprises successive approximation analog-to-digital conversion modules and registers, the number of the successive approximation analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation analog-to-digital conversion module corresponds to the order of input signals in all the successive approximation analog-to-digital conversion modules, and the digital output end of each successive approximation analog-to-digital conversion module is connected with the input end of each register; the digital bit expansion system comprises a digital bit addition module and a clock control module, wherein the digital bit addition module comprises a cascade integral comb filter and a moving average filter connected with the cascade integral comb filter; wherein, the liquid crystal display device comprises a liquid crystal display device,
the oversampling switch is used for inputting the analog signal and outputting the sampled analog signal;
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the digital signal and sending the digital signal to the register, wherein the signal input by the first-order successive approximation type analog-to-digital conversion module is a signal output by the oversampling switch;
the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form to be output;
the clock control module is used for providing clock signals for the cascade integration comb filter and the moving average filter;
the cascade integration comb filter is used for receiving a clock signal sent by the clock control module, receiving a digital code output by the register when receiving a trigger start clock signal, then integrating and reducing frequency, and realizing increment of digits in the integration process;
and the moving average filter is used for receiving the clock signal sent by the clock control module, removing clock jitter and inherent noise of the output digital code of the cascade integral comb filter when receiving the trigger starting clock signal so as to realize smooth output.
2. The oversampling Pipeline SAR-ADC system according to claim 1, wherein the successive approximation analog-to-digital conversion module comprises two sampling switches, two capacitor arrays, a comparator, a logic control module and an output buffer module, the two sampling switches are connected with the input ends of the two capacitor arrays in one-to-one correspondence, and the output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
3. The oversampling Pipeline SAR-ADC system of claim 1, wherein a signal amplifying circuit is provided on the line between any two adjacent successive approximation analog-to-digital conversion modules.
4. An oversampling Pipeline SAR-ADC system according to any of claims 1 to 3, wherein said cascaded integrator-comb filter is formed by a cascade of single stage CIC filters.
5. The oversampling Pipeline SAR-ADC system of claim 4, wherein the CIC filter comprises an integrator, a decimator, and a differentiator, connected in sequence.
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| CN108494404B (en) | 2018-03-27 | 2020-06-02 | 中国电子科技集团公司第二十四研究所 | Capacitance voltage coefficient calibration method of high-precision successive approximation type analog-to-digital converter |
| CN111970006B (en) * | 2020-08-05 | 2022-06-03 | 北京航空航天大学 | Cyclic analog-to-digital converter |
| CN112152630A (en) * | 2020-10-23 | 2020-12-29 | 成都鸿驰远科技有限公司 | System for optimally designing conversion time of sensor reading circuit |
| CN112383311A (en) * | 2020-11-19 | 2021-02-19 | 珠海零边界集成电路有限公司 | Successive approximation type analog-digital converter and data conversion method thereof |
| CN113325215B (en) * | 2021-04-28 | 2022-04-26 | 哈尔滨工业大学 | Design method of optical fiber current transformer output controller based on multistage comb filtering |
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