CN115328386B - ADC module control architecture based on time slot control - Google Patents
ADC module control architecture based on time slot control Download PDFInfo
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- CN115328386B CN115328386B CN202211032911.3A CN202211032911A CN115328386B CN 115328386 B CN115328386 B CN 115328386B CN 202211032911 A CN202211032911 A CN 202211032911A CN 115328386 B CN115328386 B CN 115328386B
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- time slot
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- successive approximation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
- H03M1/1225—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages using time-division multiplexing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses an ADC module control architecture based on time slot control, which comprises a multiplexer, a voltage comparator, a D/A converter, a successive approximation register and a time division multiplexing control state machine; the input of the multiplexer is at least one path of analog signal, the output and the output of the D/A converter are respectively connected to the input end of the comparator, and the output end of the comparator is connected to the successive approximation register; the successive approximation register is electrically connected with the time division multiplexing control state; the time division multiplexing control state machine is a time sequence control circuit; the multiplexing output end of the D/A converter is a reference analog output end; the multiplexing output end of the comparator is a comparison output end; the output of the successive approximation register is the digital output. The scheme can fully utilize the D/A converter and the comparator of the ADC module, more logic devices can be omitted in the complex logic circuit and the MCU, the space is saved, the integration level is improved, and the resource utilization rate of the module can be improved.
Description
Technical Field
The embodiment of the application relates to the field of power electronics, in particular to an ADC module control architecture based on time slot control.
Background
The ADC module is an indispensable conversion unit in all MCU chips and electronic circuits, and is mainly used for collecting analog quantity data and realizing conversion from analog quantity to digital quantity so as to ensure the normal operation of the digital circuit.
In the existing MCU chip, the ADC, the comparator and the DAC are generally implemented independently, that is, the three functions are implemented by three independent units, that is, the ADC module is only used for signal conversion, the comparator is only used for relatively large and small, the DAC is only used for analog-to-digital conversion, or the ADC function is only provided without the functions of the comparator and the DAC.
The performance is best for MCU which independently realizes ADC, CMP and DAC functions, but the chip area is large, the functions are independent, and the cost performance is not high. In a chip with only ADC function, the MCU does not support CMP and DAC, and the MCU obviously lacks these important specifications, which is not beneficial to popularization. Also, although the functions of ADC, CMP and DAC can be realized, they cannot exist at the same time, and the time division multiplexing is needed, so that the processing efficiency is low.
Disclosure of Invention
The embodiment of the application provides an ADC module control architecture based on time slot control, which solves the problem of low resource utilization rate of an ADC module, and comprises a multiplexer, a voltage comparator, a D/A converter, a successive approximation register and a time division multiplexing control state machine;
the input of the multiplexer is at least one path of analog signal, the output of the multiplexer and the output of the D/A converter are respectively connected to the input end of the comparator, and the output end of the comparator is connected to the successive approximation register; the successive approximation register is electrically connected with the time division multiplexing control state and controls the D/A converter to output a reference analog signal; the time division multiplexing control state machine is a time sequence control circuit and is used for controlling the working time slots and the working sequence of each module;
the multiplexing output end of the D/A converter is a reference analog output end; the multiplexing output end of the comparator is a comparison output end; the output end of the successive approximation register is a digital quantity output end.
Specifically, the D/a converter is a T-type resistor voltage divider network, and the successive approximation register is n-bit detection and conversion precision.
Specifically, the reference analog output terminal is connected with a grounding capacitor for filtering and maintaining voltage.
Specifically, the control time sequence of the time division multiplexing control state machine comprises a CMP comparator time slot, an ADC time slot and a DAC time slot;
in the CMP time slot, the time division multiplexing control state machine controls the comparator and the multiplexer to be enabled, controls the D/A converter and the successive approximation register to be disabled, and the comparison output end outputs a comparison result;
in the DAC time slot, the time division multiplexing control state machine controls the D/A converter to be enabled, controls the comparator, the multiplexer and the successive approximation register to be disabled, and the reference analog output end outputs a reference analog signal;
in the ADC time slot, the time division multiplexing control state machine controls the comparator, the multiplexer, the successive approximation register and the D/A converter to be enabled, and the digital quantity output end outputs a digital signal.
Specifically, the ADC time slot and the CMP time slot are fixed clock periods, and the DAC time slot is a configurable clock period.
Specifically, the control time sequence of the time division multiplexing control state machine further comprises an IDLE standby time slot; within the IDLE slot, the time division multiplexing control state machine controls the D/a converter, the comparator, the successive approximation register, the multiplexer not to be enabled.
Specifically, in the DAC time slot, the reference analog output end of the D/A converter is connected with a DC-DC converter to provide a reference voltage;
in the CMP time slot, the comparison output end of the comparator is externally connected with a logic circuit for the comparison operation of the logic circuit and outputting the result.
The beneficial effects that technical scheme that this application embodiment provided include at least: the multiplexing output end of the D/A converter is additionally arranged as a reference analog output end, and the multiplexing output end of the comparator is additionally arranged as a comparison output end; the working state of the ADC module is controlled and switched through the time division multiplexing control state machine, so that the corresponding data are output by each output end of the ADC module in a wheel flow mode, and specific tasks are executed by matching with an external logic circuit. The mode can fully utilize the D/A converter and the comparator of the ADC module, serve as specific components in an external logic circuit and realize the functions of the specific components, and in a complex logic circuit and an MCU chip, the ADC module control architecture can omit more logic components, save space and improve the integration level, and can improve the resource utilization rate of the ADC module.
Drawings
Fig. 1 is a block diagram of a successive approximation ADC module in the related art according to an embodiment of the present application;
fig. 2 is a block diagram of an ADC module control architecture based on slot control according to an embodiment of the application;
fig. 3 is a time slot state diagram of a time division multiplexing state machine provided in an embodiment of the present application;
FIG. 4 is a timing diagram of DAC time slots and ADC time slots provided by an embodiment of the present application;
fig. 5 is a timing diagram of DAC slots, CMP slots, and ADC slots provided by an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
ADC modules are commonly found in electronic circuits and MCU chips, the nature of which is to achieve conversion of analog signals to digital signals, but in most MCUs and circuit structures, ADC modules are used only as conversion and not to multiplex other functions. For example, the schematic structure of the successive approximation ADC module in fig. 1 mainly comprises a successive approximation register, a D/a converter, a voltage comparator, and a multiplexer MUX, wherein the input of the multiplexer is an analog signal input port, and the output port of the successive approximation register is a converted digital signal output port, i.e. an ADC output. The basic principle is that the highest position 1 of the successive approximation register is sent to the D/A converter when the conversion starts, the analog Vo generated after the D/A conversion is sent to the comparator and compared with the analog Vi to be converted sent to the comparator, if Vo < Vi, the bit 1 is reserved, otherwise, the bit 1 is cleared. Then the next high order of the successive approximation register is set to be 1, new digital quantity in the register is sent to the D/A converter, the output Vo is compared with Vi, if Vo < Vi, the bit 1 is reserved, otherwise, the bit 1 is cleared. The process is repeated until the least significant bit of the register is approximated, and finally the output of the digital quantity is obtained.
The above process is controlled by a logic circuit and a clock, and the matching of a comparator and a D/a converter is needed in the whole conversion process, but for a complex logic control circuit or MCU chip, the ADC module is integrally used, and when a comparison operation or voltage output is needed, the comparator or voltage control module needs to be additionally configured, which definitely increases the volume of the logic circuit or MCU, and the devices inside the ADC module are not fully utilized.
Fig. 2 is a schematic diagram of an ADC module control architecture based on slot control according to an embodiment of the present application, which is mainly directed to an ADC module including a D/a converter and a comparator. On the basis of the original ADC module, a time division multiplexing control state machine is added, and replaces the original time sequence control logic circuit to realize independent control of each module unit. As shown in fig. 2 in particular, the control architecture includes a multiplexer, a voltage comparator, a D/a converter, a successive approximation register, and a time division multiplexed control state machine. The input of the multiplexer is at least one path of analog signal, the output of the multiplexer and the output of the D/A converter are respectively connected to the input end of the comparator, and the output end of the comparator is connected to the successive approximation register. The successive approximation register is electrically connected with the time division multiplexing control state and controls the D/A converter to output a reference analog signal. The time division multiplexing control state machine is a time sequence control circuit and is used for controlling the working time slot and the working sequence of each module. The time division multiplexing control result can multiplex the output of each module, so that a plurality of output ports are added on the basis of the original ADC module, and the multiplexing output end of the D/A converter is a reference analog output end; the multiplexing output end of the comparator is a comparison output end; the output end of the successive approximation register is a digital quantity output end, and each module can work or work cooperatively under the control of the time division multiplexing control state machine, so that the resource utilization rate of the module is increased.
The D/A converter in the scheme adopts a T-type resistor voltage division network, keeps the same detection and conversion precision with the successive approximation register, is mainly used for generating reference voltage according to the output control of a comparator, and the corresponding reference analog output end is additionally connected with a grounding capacitor, and the specific resistance is determined according to actual conditions.
The scheme is to discover the functions of the D/A converter and the comparator, control the successive approximation register by using a time division multiplexing technology, and simultaneously achieve the aim of simultaneously working three functions of an ADC, a CMP and a DAC by using the characteristic that the voltage of a grounding capacitor cannot be suddenly changed through time slot control.
In the scheme, the control time sequence of the time division multiplexing control state machine comprises a CMP comparator time slot, an ADC time slot and a DAC time slot. In the CMP time slot, the time division multiplexing control state machine controls the comparator and the multiplexer to be enabled, controls the D/A converter and the successive approximation register not to be enabled, and the comparison output end outputs the comparison result. In the DAC time slot, the time division multiplexing control state machine controls the D/A converter to be enabled, controls the comparator, the multiplexer and the successive approximation register to be disabled, and the reference analog output end outputs a reference analog signal. In ADC time slot, the time division multiplexing control state machine controls the comparator, multiplexer, successive approximation register and D/A converter to enable, and the digital output end outputs digital signal. That is, the state machine controls the corresponding module to operate or not to operate through the control signal, so as to realize the independent operation or the cooperative operation of the modules. Besides the three working time slots, an IDLE standby time slot is also arranged, and in the IDLE time slot, the time division multiplexing control state machine controls the D/A converter, the comparator, the successive approximation register and the multiplexer not to be enabled, namely, all ports are not output, and the ADC module enters a standby state.
Fig. 3 is a slot state diagram of a time division multiplexed state machine. The state machine can control the switching between any two working time slots, namely, the conversion of the working state of the ADC module. The clock cycle of the ADC analog-to-digital conversion is fixed, for example, the ADC function with 10bit precision can be completed by only 13 clock cycles, that is, the time required for completing the corresponding task is fixed. The corresponding precision comparator then needs 4 cycles to complete. The working time slot of the DAC in the scheme can be configured arbitrarily. As shown in fig. 3, between the DAC time slot and the CMP time slot, the D/a converter jumps to the DAC time slot after waiting for 4 cycles of the CMP time slot, and controls the reference analog output terminal to output; and between the ADC time slot and the CMP time slot, the comparator jumps to the CMP time slot after waiting 13 cycles, controls the output of the comparison output end, and correspondingly, to realize the analog-to-digital conversion, the comparator needs to wait 4 cycles of the CMP and execute the output of the digital quantity output end. And entering an IDLE time slot indicates that the ADC module has no work task and enters a standby power saving state.
In one possible embodiment, when it is desired to control the lamp brightness by means of the ADC module to implement the DC-DC converter, the reference analog output of the D/a converter is connected to the DC-DC converter, which is connected to the lamp. Since the DC-DC converter requires a stable reference voltage to ensure a stable converted output, the circuit and the MCU chip require a built-in voltage stabilizing circuit and a power management module to modulate the reference voltage, and the output of the D/a converter in the ADC module can just output a stable voltage output. So the DAC time slot can be matched with the reference voltage of the DC-DC converter, and the accurate adjustment of the brightness of the bulb can be realized. The timing chart can be shown as shown in fig. 4, and also taking 10bit precision as an example, when the ADC module needs to perform analog-to-digital conversion and control the bulb brightness, DAC time slots can be inserted in the ADC time slot stage to control the bulb brightness, the clock period of the DAC time slots can be set arbitrarily according to the application scenario, and the interval between adjacent DAC time slots is only 13 cycles. The reference analog output end is connected with a grounding capacitor, the brightness of the bulb is maintained by utilizing the characteristic that the voltage cannot be suddenly changed (the grounding capacitor can also be used for filtering and removing interference), the interval time of 13 cycles is lower than the visual observation range, and the brightness is ensured to be continuous on the sensitization. After bulb control and analog-to-digital conversion are performed, an IDLE time slot is entered, and the whole ADC module enters a power saving mode. In addition, the DC-DC converter can also be used for controlling other voltage output occasions, and is not limited to lamp brightness control.
In another possible real-time manner, when the comparison and voltage output functions are needed to be realized by means of the comparator and the D/a converter of the ADC module, as shown in fig. 5, on the basis of the original comparison output end of the comparator, an external logic circuit is connected, and the working time of the single comparator is 4 cycles, that is, 4 cycles are occupied on the basis of the analog-to-digital conversion, and as shown in fig. 4, three state switching operations of the ADC mode, the DAC mode and the comparator mode are realized by elongating the time interval between the ADC time slots, and the three multiplexing output ends switch and output the corresponding data. And when analog-to-digital conversion is carried out, the bulb brightness and the comparator are controlled to participate in external logic operation, so that the time division multiplexing control of the ADC module is realized, and the utilization rate of the whole resources is improved. In addition, the high and low levels generated by the CMP time slot can also be used as control switch signals of an external circuit for driving the MOS tube to be turned on and off.
The control of the DAC time slot and the CMP time slot in the process is alternated in the ADC time slot process, the output of the digital quantity output end of the successive approximation register in the ADC time slot process is not greatly influenced, and the simultaneous operation of all parts is realized.
It should be noted that, when analog-to-digital conversion is not required, the ADC module may be directly set to be a single DAC slot, or a single CMP slot, or a DAC slot and a CMP slot, that is, a single DAC output control, or a single comparator output control, or a time division multiplexing output of the DAC and the comparator.
In summary, according to the ADC module control architecture based on time slot control provided in the present disclosure, a time division multiplexing control state machine is added on the basis of an original ADC module, and multiplexing output ends of each internal module are set at the same time, and corresponding data is output through corresponding multiplexing output ends controlled by different working time slots of the state machine, so as to implement other functions of the ADC module except analog-digital conversion.
For the scene and the road requiring the comparator and the reference voltage, the control mode can be directly introduced and realized by utilizing the existing ADC module, more logic devices can be omitted in MCU chips and circuit structures with higher integration level, the space is saved, the integration level is improved, and the resource utilization rate of the ADC module can be improved.
The foregoing describes preferred embodiments of the present invention; it is to be understood that the invention is not limited to the specific embodiments described above, wherein devices and structures not described in detail are to be understood as being implemented in a manner common in the art; any person skilled in the art will make many possible variations and modifications, or adaptations to equivalent embodiments without departing from the technical solution of the present invention, which do not affect the essential content of the present invention; therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (5)
1. The ADC module control architecture based on time slot control is characterized by comprising a multiplexer, a voltage comparator, a D/A converter, a successive approximation register and a time division multiplexing control state machine;
the input of the multiplexer is at least one path of analog signal, the output of the multiplexer and the output of the D/A converter are respectively connected to the input end of the comparator, and the output end of the comparator is connected to the successive approximation register; the successive approximation register is electrically connected with the time division multiplexing control state and controls the D/A converter to output a reference analog signal; the time division multiplexing control state machine is a time sequence control circuit and is used for controlling the working time slots and the working sequence of each module; the control time sequence of the time division multiplexing control state machine comprises a CMP comparator time slot, an ADC time slot and a DAC time slot;
in the time slot of the CMP comparator, the time division multiplexing control state machine controls the comparator and the multiplexer to be enabled, controls the D/A converter and the successive approximation register to be disabled, and the comparison output end outputs a comparison result;
in the DAC time slot, the time division multiplexing control state machine controls the D/A converter to be enabled, controls the comparator, the multiplexer and the successive approximation register to be disabled, and outputs a reference analog signal by a reference analog output end;
in the ADC time slot, the time division multiplexing control state machine controls the comparator, the multiplexer, the successive approximation register and the D/A converter to enable, and a digital quantity output end outputs a digital signal;
the multiplexing output end of the D/A converter is a reference analog output end, and the reference analog output end is connected with a grounding capacitor for filtering and maintaining voltage; the multiplexing output end of the comparator is a comparison output end; the output end of the successive approximation register is a digital quantity output end.
2. The control architecture of claim 1, wherein the D/a converter is a T-type resistor divider network and the successive approximation register is n-bit detection and conversion precision.
3. The control architecture of claim 2, wherein the ADC time slot and the CMP comparator time slot are fixed clock cycles, and the DAC time slot is a configurable clock cycle.
4. The control architecture of claim 3, wherein the control timing of the time division multiplexed control state machine further comprises an IDLE standby time slot; within the IDLE standby time slot, the time division multiplexing control state machine controls the D/a converter, the comparator, the successive approximation register and the multiplexer not to be enabled.
5. The control architecture of claim 4, wherein the reference analog output of the D/a converter is coupled to a DC-DC converter during a DAC time slot to provide a reference voltage;
in the time slot of the CMP comparator, the comparison output end of the comparator is externally connected with a logic circuit for the comparison operation of the logic circuit and outputting the result.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008294761A (en) * | 2007-05-24 | 2008-12-04 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
| CN202364114U (en) * | 2011-10-28 | 2012-08-01 | 东南大学 | Digital power factor correction controller based on time division multiplex analog-to-digital converter |
| CN103138758A (en) * | 2011-11-30 | 2013-06-05 | 禾瑞亚科技股份有限公司 | Integration and analog to digital conversion circuit with common capacitors and operating method thereof |
| JP2014057244A (en) * | 2012-09-13 | 2014-03-27 | Renesas Electronics Corp | Ad converter and ad conversion method |
| CN107786206A (en) * | 2017-11-29 | 2018-03-09 | 四川知微传感技术有限公司 | A kind of Pipeline SAR ADC systems |
| CN207399180U (en) * | 2017-11-01 | 2018-05-22 | 无锡华润矽科微电子有限公司 | Reference voltage adaptive circuit structure and related device |
| CN110034766A (en) * | 2019-04-24 | 2019-07-19 | 深圳市汇春科技股份有限公司 | A kind of comparator circuit and comparator circuit control method |
| CN113489493A (en) * | 2021-07-28 | 2021-10-08 | 江苏集萃智能集成电路设计技术研究所有限公司 | Time-sharing multiplexing control system and time-sharing multiplexing method for analog-to-digital converter |
| CN215420236U (en) * | 2021-04-07 | 2022-01-04 | 苏州市灵矽微系统有限公司 | Quantizer circuit for SAR ADC |
-
2022
- 2022-08-26 CN CN202211032911.3A patent/CN115328386B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008294761A (en) * | 2007-05-24 | 2008-12-04 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
| CN202364114U (en) * | 2011-10-28 | 2012-08-01 | 东南大学 | Digital power factor correction controller based on time division multiplex analog-to-digital converter |
| CN103138758A (en) * | 2011-11-30 | 2013-06-05 | 禾瑞亚科技股份有限公司 | Integration and analog to digital conversion circuit with common capacitors and operating method thereof |
| JP2014057244A (en) * | 2012-09-13 | 2014-03-27 | Renesas Electronics Corp | Ad converter and ad conversion method |
| CN207399180U (en) * | 2017-11-01 | 2018-05-22 | 无锡华润矽科微电子有限公司 | Reference voltage adaptive circuit structure and related device |
| CN107786206A (en) * | 2017-11-29 | 2018-03-09 | 四川知微传感技术有限公司 | A kind of Pipeline SAR ADC systems |
| CN110034766A (en) * | 2019-04-24 | 2019-07-19 | 深圳市汇春科技股份有限公司 | A kind of comparator circuit and comparator circuit control method |
| CN215420236U (en) * | 2021-04-07 | 2022-01-04 | 苏州市灵矽微系统有限公司 | Quantizer circuit for SAR ADC |
| CN113489493A (en) * | 2021-07-28 | 2021-10-08 | 江苏集萃智能集成电路设计技术研究所有限公司 | Time-sharing multiplexing control system and time-sharing multiplexing method for analog-to-digital converter |
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