CN202364114U - Digital power factor correction controller based on time division multiplex analog-to-digital converter - Google Patents
Digital power factor correction controller based on time division multiplex analog-to-digital converter Download PDFInfo
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- CN202364114U CN202364114U CN201120421845XU CN201120421845U CN202364114U CN 202364114 U CN202364114 U CN 202364114U CN 201120421845X U CN201120421845X U CN 201120421845XU CN 201120421845 U CN201120421845 U CN 201120421845U CN 202364114 U CN202364114 U CN 202364114U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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Abstract
The utility model discloses a digital power factor correction controller based on a time division multiplex analog-to-digital converter. The digital power factor correction controller is provided with an analog-to-digital conversion circuit, a compensation algorithm logic circuit, a pulse width modulator circuit and a power factor correction basic topological circuit. The analog-to-digital conversion circuit comprises a frequency divider, a state machine, a counter, a decoder, an AND gate, a set-reset (SR) latch, an A/D conversion circuit, a subtracter, a first transmission gate, a second transmission gate, a third transmission gate and a first shift register, a second shift register and a third shift register. The first shift register, the second shift register and the third shift register are formed by serially connecting a first trigger, a second trigger and a third trigger. The analog-to-digital conversion of the signals of three circuits is realized by using a time division multiplexer of one analog-to-digital converter instead of three analog-to-digital converters in the existing digital power factor correction controller. In each controlling and processing period, three times of conversion is performed, and the analog-to-digital converters do not work during the remaining time, so the circuit design of the power factor correction converters is simplified, the size of chips is reduced effectively, and the power consumption is reduced.
Description
Technical field
The utility model relates to a kind of digital power factor correcting controller based on the time-sharing multiplex analog to digital converter, belongs to IC design, is subordinate to electronic technology field.
Background technology
Power factor correction controller can reduce the harmonic pollution that power electronic equipment such as Switching Power Supply produces electrical network; To guarantee the reliability of power grid quality, raising electrical network; And continuous intensification along with the world energy sources crisis; Various countries are strict just day by day to the power factor (PF) examination relevant regulations of power consumption equipment, and power factor is required to uprise, and the occasion of power factor correcting controller also will enlarge.
Because digital power factor correcting controller can significantly reduce cost, simplified design improves precision, and can realize various complicated algorithm, and the susceptibility that external condition is changed is also lower.Based on above advantage, digital power factor correcting controller is becoming another research focus that people pay close attention to.
Usually in the design of digital power factor correcting controller, need sample to multiple signals (input voltage, input current and output voltage), and be converted into digital quantity.Existing solution is to use a plurality of analog to digital converters that each road signal is changed.And in fact, a plurality of analog to digital converters are not continuous firing in the cycle a control and treatment, do not play one's part to the full.
Summary of the invention
The utility model provides a kind of digital power factor correcting controller based on the time-sharing multiplex analog to digital converter; Adopt time-sharing multiplex to replace three analog to digital converters in the existing digital power factor correcting controller to an analog to digital converter; Can effectively reduce chip area; Reduce power consumption, and reduce the design complexities of power factor correction controller.Simplified the circuit structure of digital power factor correcting controller.
The technical scheme that the utility model adopts is: a kind of digital power factor correcting controller based on the time-sharing multiplex analog to digital converter; Be provided with analog to digital conversion circuit, backoff algorithm logical circuit, pulse-width modulation circuit and the basic topological circuit of power factor correction; It is characterized in that: analog to digital conversion circuit comprise frequency divider, state machine, counter, decoder, with door, SR latch, A/D change-over circuit, subtracter, first, second,, the 33 transmission gate and first, second, third 3 shift registers being followed in series to form by first, second, third 3 identical d type flip flops, the in-phase output end of previous stage d type flip flop links to each other with the D input of back one-level d type flip flop; The input of frequency divider is connected with external clock, and frequency divider is provided with first, second, third, fourth and the 55 output, and first output of frequency divider links to each other with the clock end of state machine; Second output links to each other with the set end of SR latch; The 3rd output is connected with the clock end of A/D change-over circuit, and the 4th output is connected with the clock end of backoff algorithm logical circuit, and the 5th output links to each other with the clock end of pulse-width modulation circuit; The output of state machine produces the clock marking signal and is connected with the clock end of the clock end of counter and first, second, third 3 shift registers respectively; An output of counter connect respectively decoder and with the door an input, another output of counter connect respectively decoder and with the door another input; Decoder is provided with 3 outputs; The switching signal input that connects first, second, third transmission gate respectively; Output voltage, input current, input voltage that the input of first, second, third transmission gate connects respectively in the basic topological circuit of power factor correction are treated sampled signal, and the output of first, second, third transmission gate all connects the A/D change-over circuit; The reset terminal that is connected the SR latch with gate output terminal; The output of SR latch connects A/D change-over circuit enable signal end; The digital value output of A/D change-over circuit links to each other with the D input of first shift register; The in-phase output end of first shift register and second shift register also is connected respectively to 2 inputs in 3 inputs of backoff algorithm logical circuit; The output of the 3rd shift register connects the negative end of subtracter, and the in-phase input end of subtracter connects the reference signal, and the subtracter output connects the 3rd input of backoff algorithm logical circuit; The duty ratio instruction output end of backoff algorithm logical circuit links to each other with the input of pulse-width modulation circuit, and pulse-width modulation circuit output PWM control impuls is to the basic topological circuit of power factor correction.
Advantage of the utility model and beneficial effect: rely on time-sharing multiplex to replace three analog to digital converters in the existing digital power factor correcting controller, realize the analog-to-digital conversion of three road signals to an analog to digital converter.In each control and treatment cycle, only carry out three conversions, all the other time analog to digital converters are not worked.So, simplify the circuit design of power factor correction converter, can effectively reduce chip area, reduced power consumption, obtained a digital power factor correcting transducer of more optimizing, had certain versatility.
Description of drawings
Fig. 1 is the circuit diagram of the utility model;
Fig. 2 is the sequential chart of the multiplexing analog to digital converter time sharing sampling of the utility model three tunnel;
Fig. 3 is the structured flowchart of prior art digital power factor correcting controller circuitry;
Fig. 4 is the working timing figure of digital to analog converter in the prior art digital power factor correcting controller.
Embodiment
Referring to Fig. 1, the utility model comprises the basic topological circuit 4 of analog to digital conversion circuit 1, backoff algorithm logical circuit 2, pulse-width modulation circuit 3 and power factor correction.Fig. 3 compares with prior art, and just analog to digital conversion circuit 1 has adopted time-sharing multiplex, and remaining circuit is identical.Input voltage, input current and the output voltage of 1 pair of basic topological circuit 4 of power factor correction of analog to digital conversion circuit of the present invention are sampled and analog-to-digital conversion; And the digital value after will changing delivers to backoff algorithm logical circuit 2, analog to digital conversion circuit 1 comprise frequency divider 101, state machine 102, counter 103, decoder 104, first transmission gate 105, second transmission gate 106, the 3rd transmission gate 107, with door 108, SR latch 109, A/D change-over circuit 110, first shift register 111, second shift register 112, the 3rd shift register 113 and subtracter 114.The input of frequency divider 101 is connected with external clock clock, frequency divider 101 first output clk
StatemachineBe the work clock of state machine 102, the second output clk
SampleLink to each other the 3rd output clk with the set end of SR latch (109)
ADCBe the work clock of A/D change-over circuit 109, the 4th output clk
CompensatorBe connected the 5th output clk with the clock end of backoff algorithm logical circuit 2
PWMBe connected with the clock end of pulse-width modulation circuit 3.The output T of state machine 102
FinishedBe the clock marking signal, three high level pulses of each systematic sampling cycle output, each high level pulse sign one-off pattern number conversion is accomplished, T
FinishedBe connected with the clock end of counter 103 and the clock end of three shift registers.Counter 103 circulation outputs 00,01,11,10; Be connected with decoder 104, counter 103 was exported 00,01,11 o'clock successively, showed that A/D change-over circuit 110 changes three tunnel signals that collect just successively; When output becomes 10, show that three tunnel conversions finish.Decoder 104, when being input as 00, output 001,110 pairs of first via signals of expression A/D change-over circuit carry out analog-to-digital conversion; When being input as 01, output 010,110 pairs the second road signals of expression A/D change-over circuit carry out analog-to-digital conversion; When being input as 11, output 001,110 pairs of Third Road signals of expression A/D change-over circuit carry out analog-to-digital conversion; When being input as 10, be output as 100.Three transmission gates are received in the output of decoder 104 respectively, as switching signal.The input of first transmission gate 105 is connected to R in the basic topological circuit of power factor correction
O1With R
O2Between, be output voltage V to be sampled
o(t).The input of second transmission gate 106 is connected to R in the basic topological circuit of power factor correction
sWith R
FB2Between, be input current I to be sampled
In(t).The input of the 3rd transmission gate 107 is received R in the basic topological circuit of power factor correction in succession
FB1With R
FB2Between, be input voltage V to be sampled
In(t).The output of three transmission gates is all received A/D change-over circuit 110.Be connected with the output of counter 103 with the input of door 108, be connected to the reset terminal of SR latch 109, only when counter 103 outputs 10, with door 108 output high level with door 108 outputs.The output EN of SR latch 109
ADCBe connected EN with A/D change-over circuit 110
ADCFor the enable signal of A/D change-over circuit 110, at clk
SampleThe signal rising edge comes interim set, when three the tunnel convert, resets, and controls the work of A/D change-over circuit 110 thus.The digital value output of A/D change-over circuit 110 links to each other with the D input of said first shift register 111; Said first shift register 111, second shift register 112, the 3rd shift register 113 are that 3 identical d type flip flops polyphones constitute; The in-phase output end of previous stage d type flip flop links to each other with the D input of back one-level d type flip flop; The in-phase output end of first shift register 111 and second shift register 112 is also connected to said backoff algorithm logical circuit 2 simultaneously; The output of the 3rd shift register 113 is connected to the negative end of subtracter 114, and the clock end of all shift registers all is connected to the clock flag terminal T of said state machine 102
FinishedThe in-phase input end of subtracter 114 is connected with reference signal V
Ref, the output of subtracter 114 is connected to said backoff algorithm logical circuit 2.Backoff algorithm logical circuit 2 has clock end and three inputs, wherein, and the backoff algorithm logical circuit clock signal clk of clock end and the output of frequency divider 101 the 4th output
CompensatorLink to each other; First input end links to each other with first shift register, 111 in-phase output ends; Second input links to each other with the in-phase output end of the second shift register register 112; The 3rd input links to each other with the output of subtracter 114, and the duty ratio instruction output end of backoff algorithm logical circuit 2 links to each other with the input of pulse-width modulation circuit 3.The pulse-width modulation circuit clock signal clk of the clock end of pulse-width modulation circuit 3 and the output of frequency divider the 5th output
PWMConnect, input links to each other with the duty ratio instruction output end of backoff algorithm logical circuit 2, and output provides the PWM control impuls, and the PWM control impuls is given to the grid of metal-oxide-semiconductor in the basic topological circuit of power factor correction, and then realizes power factor emendation function.
Fig. 3 is the structured flowchart of prior art digital power factor correcting controller circuitry, adopted three independently analog to digital converter carry out analog-to-digital conversion.Structured flowchart of the present invention in Fig. 1 is not difficult to find, adopts the power factor correction controller circuit structure of time-sharing multiplex analog to digital converter more simple, thereby has effectively reduced area of chip.
The operation principle of the utility model and the course of work:
Referring to Fig. 1 and Fig. 2, the present invention is a kind of digital power factor correcting controller that adopts the time-sharing multiplex analog to digital converter, and external clock produces T through frequency divider
Finished, clk
ADCAnd clk
Sample, clk
ADCBe the work clock of A/D change-over circuit, clk
SampleBe the sampling clock of system, T
FinishedIdentifying each time, analog-to-digital conversion finishes.As systematic sampling signal clk
SampleWhen rising edge arrived, the SR latch was put height, made A/D change-over circuit potential energy signal EN
ADCBe high level, the A/D change-over circuit is started working, and circuit at first will be to required input voltage V
In(t), input current I
In(t) and output voltage V
o(t) sample, the three tunnel treat that sampled signal receives three transmission gates respectively, and three transmission gates are opened successively; The time of at every turn opening is analog-to-digital time once, and the switching signal of transmission gate is from decoder circuit, and decoder is deciphered four kinds of states that counter produces; When counter exported 00, expression was sampled and analog-to-digital conversion to first via signal, decoder output 100; When counter exported 01, expression was sampled and analog-to-digital conversion to the second road signal, decoder output 010; When counter exported 11, expression was sampled and analog-to-digital conversion to the Third Road signal, decoder output 001; When counter exports 10, represent the completion of three tunnel conversion of signals, decoder output 100.And this moment, output 10 warps of counter reset with goalkeeper SR latch, EN
ADCBe low level, the A/D change-over circuit turn-offs.First shift register is received in the output of A/D change-over circuit, and three shift registers are three identical d type flip flops, and the in-phase output end of previous stage d type flip flop links to each other T with the D input of back one-level d type flip flop
FinishedSignal is connected to the clock end of shift register, and promptly each analog-to-digital conversion is accomplished, and shift register once is shifted, after accomplishing for three times, and the digital value V that is input voltage, input current and output voltage after the analog-to-digital conversion that preserves in three shift registers
In[n], i
L[n] and V
o[n].The backoff algorithm logical circuit reads digital value after three times convert, reference signal V
RefWith V
oIt is poor that [n] does, and delivers to the backoff algorithm logical circuit, V
In[n] and i
L[n] also is given to the backoff algorithm logical circuit; Backoff algorithm logical circuit output duty cycle instruction d [n] is given to pulse width modulator; Pulse width modulator output PWM control impuls, the PWM control impuls is given on the basic topological circuit of power factor correction, and then realizes power factor emendation function.
Among Fig. 2, clk
SampleBe system sampling clock, clk
CompensatorFor analog-to-digital conversion result's control clock, T are read in compensation
FinishedBe each analog-to-digital conversion end mark signal, EN
ADCBe A/D change-over circuit enable signal, Sel_V
o(t), Sel_V
In(t) and Sel_I
In(t) be A/D change-over circuit input select signal, Shifit Register1, Shifit Register2 and Shifit Register3 are three shift registers.As can be seen from the figure; Each systematic sampling cycle; Respectively input voltage, input current and output voltage are carried out analog-to-digital conversion, and store in three shift registers, whenever convert three road signals after; Analog to digital conversion circuit is just no longer worked, and arrives up to next system sampling clock rising edge.By contrast, in Fig. 4 existing technical scheme, use three independently analog to digital converter respectively input voltage, input current and output voltage are carried out analog-to-digital conversion, after compensation was read, three analog to digital converters were still at the work of not stopping work, and this is unnecessary.Therefore, the present invention has reduced the power consumption of system effectively.
Claims (1)
1. the digital power factor correcting controller based on the time-sharing multiplex analog to digital converter is provided with analog to digital conversion circuit, backoff algorithm logical circuit, pulse-width modulation circuit and the basic topological circuit of power factor correction, it is characterized in that:
Analog to digital conversion circuit comprise frequency divider, state machine, counter, decoder, with door,
SRLatch,
A/DChange-over circuit, subtracter, first, second,, the 33 transmission gate and identical by first, second, third 3
DFirst, second, third 3 shift registers that trigger is followed in series to form, previous stage
DThe in-phase output end of trigger and back one-level
DTrigger
DInput links to each other; , the input of frequency divider is connected with external clock, frequency divider is provided with first, second, third, fourth and the 55 output, first output of frequency divider links to each other with the clock end of state machine, second output with
SRThe set end of latch links to each other, the 3rd output with
A/DThe clock end of change-over circuit connects, and the 4th output is connected with the clock end of backoff algorithm logical circuit, and the 5th output links to each other with the clock end of pulse-width modulation circuit; The output of state machine produces the clock marking signal and is connected with the clock end of the clock end of counter and first, second, third 3 shift registers respectively; An output of counter connect respectively decoder and with the door an input, another output of counter connect respectively decoder and with the door another input; Decoder is provided with 3 outputs; The switching signal input that connects first, second, third transmission gate respectively; Output voltage, input current, input voltage that the input of first, second, third transmission gate connects respectively in the basic topological circuit of power factor correction are treated sampled signal, and the output of first, second, third transmission gate all connects
A/DChange-over circuit; Be connected with gate output terminal
SRThe reset terminal of latch,
SRThe output of latch connects
A/DChange-over circuit enable signal end,
A/DThe digital value output of change-over circuit and first shift register
DInput links to each other; The in-phase output end of first shift register and second shift register also is connected respectively to 2 inputs in 3 inputs of backoff algorithm logical circuit; The output of the 3rd shift register connects the negative end of subtracter; The in-phase input end of subtracter connects the reference signal, and the subtracter output connects the 3rd input of backoff algorithm logical circuit; The duty ratio instruction output end of backoff algorithm logical circuit links to each other with the input of pulse-width modulation circuit, pulse-width modulation circuit output
PWMThe basic topological circuit of control impuls to power factor correction.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201120421845XU CN202364114U (en) | 2011-10-28 | 2011-10-28 | Digital power factor correction controller based on time division multiplex analog-to-digital converter |
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| CN201120421845XU CN202364114U (en) | 2011-10-28 | 2011-10-28 | Digital power factor correction controller based on time division multiplex analog-to-digital converter |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102510209A (en) * | 2011-10-28 | 2012-06-20 | 东南大学 | Digital power factor correction controller adopting time division multiplex analog-to-digital (A/D) converter |
| CN102891600A (en) * | 2012-10-09 | 2013-01-23 | 西安交通大学 | DVS-Buck converter used for digitally controlling output voltage and provided with timed self-calibration function |
| CN104993690A (en) * | 2015-08-10 | 2015-10-21 | 电子科技大学 | Full digit single period power factor correction circuit based on triangular wave pulse modulation |
| CN115328386A (en) * | 2022-08-26 | 2022-11-11 | 无锡众享科技有限公司 | ADC module control framework based on time slot control |
-
2011
- 2011-10-28 CN CN201120421845XU patent/CN202364114U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102510209A (en) * | 2011-10-28 | 2012-06-20 | 东南大学 | Digital power factor correction controller adopting time division multiplex analog-to-digital (A/D) converter |
| CN102510209B (en) * | 2011-10-28 | 2013-10-30 | 东南大学 | Digital power factor correction controller adopting time division multiplex analog-to-digital (A/D) converter |
| CN102891600A (en) * | 2012-10-09 | 2013-01-23 | 西安交通大学 | DVS-Buck converter used for digitally controlling output voltage and provided with timed self-calibration function |
| CN102891600B (en) * | 2012-10-09 | 2014-09-03 | 西安交通大学 | DVS-Buck converter used for digitally controlling output voltage and provided with timed self-calibration function |
| CN104993690A (en) * | 2015-08-10 | 2015-10-21 | 电子科技大学 | Full digit single period power factor correction circuit based on triangular wave pulse modulation |
| CN104993690B (en) * | 2015-08-10 | 2017-12-19 | 电子科技大学 | Digital Single-period power factor correction circuit based on triangular pulse modulation |
| CN115328386A (en) * | 2022-08-26 | 2022-11-11 | 无锡众享科技有限公司 | ADC module control framework based on time slot control |
| CN115328386B (en) * | 2022-08-26 | 2023-08-01 | 无锡众享科技有限公司 | ADC module control architecture based on time slot control |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120801 Termination date: 20131028 |