CN104124858B - A kind of suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition - Google Patents

Abstract

The invention discloses the suppressing method of a kind of Sinusoidal Pulse Width Modulation PWM logic competition, in this suppressing method within the rising half period and decline half period of triangle carrier signal, the only upset when modulated signal is with triangle carrier signal friendship section for the first time of PWM level, in i.e. one triangle carrier signal cycle, PWM only drives semiconductor power device to open, close once, the logic that can effectively inhibit SPWM is competed, the occasion of phase-shifted SPWM modulation strategy is especially used at high-power cascaded multilevel inverter, compared with the conventional method, the inventive method can reduce the switching damage of power device, do not introduce time delay simultaneously, Overlay without interference with many level, the aberration rate exporting many level can be reduced.

Description

A kind of suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition

Technical field

The invention belongs to signal modulation technique field, be specifically related to a kind of Sinusoidal Pulse Width Modulation PWM logic The suppressing method of competition.

Background technology

Along with the progress of microelectric technique, PLD gradually instead of digital integrated electronic circuit；And show Field programmable gate array (FPGA) logical device, because of its ultra-large integrated, at a high speed, the advantage such as low-power consumption Obtain paying close attention to the most widely and applying.

As the key technology in mesohigh, high-power electric and electronic application, the realization of multi-electrical level inverter needs Want complicated modulator approach and multichannel independence pwm control signal that the switching device in multilevel system is entered Row controls.The TMS320F2812 (DSP) of at present conventional digital signal processor such as TI company is to multipotency 16 road independent sinusoidal pulse width modulations (Sinusoidal Pulse Width Modulation, SPWM) are provided Pwm signal, independent use cannot meet requirement in a lot of occasions.DSP and FPGA combines to be made With then having powerful advantage: flexible structure, there is stronger versatility, hardware need not be revised and can realize not Same algorithm；Be suitable to blocking design, improve efficiency of algorithm；Its construction cycle is shorter simultaneously, and system is prone to Maintenance and expansion, it is adaptable to real time signal processing.

(i.e. switch additionally, the switching frequency of the switching device of high-power cascaded multilevel inverter is the highest Cycle is longer), and in order to ensure the control accuracy of system, sample frequency is the highest, even above derailing switch 2 times of part switching frequency, now, each carrier cycle internal modulation signal can update repeatedly, so can cause Logic is competed.It is in the rising half period as Fig. 1 (a) and Fig. 1 (b) show triangular carrier and declines half cycle The principle schematic of Sinusoidal Pulse Width Modulation (SPWM) PWM logic competition during the phase, as each FPGA When clock cycle all updates the pwm signal of modulated signal the output of real-time update CPS-SPWM generator, One carrier cycle internal modulation signal u_s(t) and triangle carrier signal u_cT () may hand over to cut and repeatedly (there is multiple friendship Point), corresponding pwm signal can overturn repeatedly, then the semiconductor switch device of power model is at default list In switch periods, repeatedly, Fig. 1 (c) and Fig. 1 (d) sets forth triangular carrier and is in rising in meeting open and close The experimental waveform of logic competition when half period and decline half period, in figure, the burst pulse of PWM about 5us, is more than Switching device sets up dead band value, can drive switching device action.Logic warfare can increase output level and become Change number of times, increase the switching loss of switching device, disturb many level Overlay, introduce extra harmonic wave and contain Amount, impact controls effect.

When system sampling frequency is higher than 2 times of carrier frequency, according to traditional at carrier wave trough point and ripple The method updating modulation wave number at peak dot, can introduce bigger time delay, it is impossible to be applied to designed pulse generation Device.In addition in entitled numeral SPWM method, on the impact of system delay, (power automation sets in Liu Chun happiness etc. Standby, 2013 (6), the 75-80 page) middle employing addition burst pulse detection, every width in FPGA Delete without exception less than the burst pulse setting threshold value, but the Breadth Maximum of burst pulse is not when system closed loop control Fixing, thus the selection of burst pulse detection threshold value is more difficult, increasing burst pulse detection in addition can be PWM introduces intrinsic time delay when upset updates, mutual due to phase shift carrier wave for the bigger system of cascade number The phase place staggered is the least, and phase-shifted SPWM is adjusted by the inherent delay directly related with detection threshold value The interference of system is the biggest, it is difficult to accept.

Summary of the invention

For the above-mentioned technological deficiency existing for prior art, the invention provides a kind of sinusoid pulse width modulation and adjust The suppressing method of PWM logic processed competition.

A kind of suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition, each at triangle carrier signal In rising the half period and declining the half period, PWM level is only handed over triangle carrier signal for the first time in modulated signal Upset when cutting, when within the rising half period, friendship cuts for the first time, then PWM is low level by high level upset, When declining half period interior friendship section for the first time, then PWM is high level by low level upset.

Modulated signal in the present invention and triangle carrier signal are handed over to cut and are referred to that modulated signal corresponding data carries with triangle The count value that ripple signal is corresponding is equal.

In the suppressing method of the logic competition of the present invention, one of triangle carrier signal rising half period or under In the fall half period, the level of pwm signal respectively overturns once, PWM in i.e. one triangle carrier signal cycle Drive semiconductor power device open and close once, and then effectively inhibit the logic of SPWM to compete (can to use Occasion is modulated in one pole frequency multiplication phase-shifted SPWM), and do not introduce time delay, it is possible to realize semiconductor power The high accuracy of device, high reliability drive and control.

Described Sinusoidal Pulse Width Modulation realizes based on DSP and FPGA, and modulated signal is passed through number by DSP FPGA is write according to bus.

The frequency of writing of described modulated signal is more than 2 times of described triangle carrier signal frequency.

Described triangle carrier signal is the signal being repeated cyclically, FPGA use continuous up-down counter Simulation, each FPGA clock cycle, the value of enumerator increases by one or reduces one, and enumerator increases from zero to Counts peaks, then it is gradually reduced to zero, it is gradually increased afterwards, moves in circles, wherein counts peaks Peak root Calculate according to below equation:

$Peak=\frac{T_{sw}}{2T_{clk}},$

T_clkFor the clock cycle of FPGA, T_swFor the switch periods of switching device, with the triangle carrier signal cycle Equal.

One pole frequency multiplication phase-shifted SPWM strategy needs multichannel phase shift triangle carrier signal, many with cascade respectively Concatenated power module one_to_one corresponding during electrical level inverter is single-phase, the amplitude of the most each road triangle carrier signal, Frequency is the most identical, and simply phase place is different, and the phase contrast of adjacent two-way triangle carrier signal is corresponding time difference T_shiftFor:

$T_{shift}=\frac{T_{sw}}{2N},$

T_swFor the switch periods of power device, equal with the triangle carrier signal cycle, N is the total of phase shift carrier wave Way is equal with single-phase concatenated power number of modules.

Multichannel phase shift carrier wave realize in FPGA be by arrange the counting direction of each carrier wave correspondence enumerator, Count initial value and obtain

Using the peak value moment of the 1st road triangle carrier signal as counting starting point, Bing Linggai road phase shift carrier wave Inceptive direction is for subtracting counting, and the inceptive direction of remaining carrier wave at different levels is and adds counting.

Determine the counting initial value u of kth road phase shift carrier wave by the following method₀(k):

$u_0\left(k\right)=\frac{N-k+1}{N}\×Peak$

Wherein, 1≤k≤N.

Described suppressing method include arranging one for the state variable representing enumerator, when enumerator is in When increasing counting, this state variable is set to 1, otherwise this state variable is set to 0 when enumerator is in and subtracts counting.

When enumerator increases counting, triangle carrier signal is in rising half period, when enumerator subtracts counting, three Angle carrier signal is in the decline half period, and therefore state variable actually represents the state of triangle carrier signal.

Described suppressing method includes arranging two flag bits, respectively with the rising half of described triangle carrier signal Cycle is corresponding with declining the half period, and this flag bit of initial time in each half period is 0, at PWM level For the first time during upset, it is 1 by corresponding mark position.

In utilizing flag bit record to rise the half period or decline the half period, whether PWM level overturns.

Described suppressing method includes:

(1) for each FPGA clock cycle, when modulated signal and triangle carrier signal are handed over and are cut, according to Described state variable determines the state of triangle carrier signal corresponding to this clock cycle:

If state variable is 0, then corresponding triangle carrier signal is in the rising half period,

Otherwise, corresponding triangle carrier signal is in the decline half period；

(2) judge corresponding flag bit according to the result of step (1) and proceed as follows:

If the flag bit of correspondence is zero, then carries out PWM level upset, and be 1 by mark position；

If the flag bit of correspondence is 1, then PWM level does not overturns；

At the end of half period, this flag bit is set to zero again.

Actually also needed to through initialization procedure, defined in this initialization procedure one before step (1) Individual state variable, and two flag bits, a rising half period corresponding to triangle carrier signal, one Corresponding to the decline half period of triangle carrier signal, under initial situation, state variable and two flag bits are equal It is zero.For the occasion of multichannel triangle carrier signal, then it is required for definition for each road triangle carrier signal One state variable and two flag bits.

Same at triangle carrier signal of suppressing method of the Sinusoidal Pulse Width Modulation signal logic competition of the present invention One rises the half period or declines in the half period, and PWM level is only at modulated signal and triangle carrier signal first Overturn when secondary friendship cuts, can effectively suppress PWM logic to compete, reduce the switching loss of power device.Especially exist High-power cascaded multilevel inverter uses the occasion of phase-shifted SPWM modulation, competes with existing logic Suppressing method compares, and the inventive method is more thorough to the inhibition of PWM, and does not introduce time delay, Bu Huigan Disturb the Overlay of many level, the aberration rate exporting many level can be reduced.

Accompanying drawing explanation

Fig. 1 (a) is that triangular carrier is in the principle schematic of logic competition when rising the half period；

Fig. 1 (b) is that triangular carrier is in the principle schematic of logic competition when declining the half period；

Fig. 1 (c) is that triangular carrier is in the oscillogram of logic competition when rising the half period；

Fig. 1 (d) is that triangular carrier is in the oscillogram of logic competition when declining the half period；

Fig. 2 is the phase three-wire three Y-connection H bridge cascade connection multi-level DSTATCOM schematic diagram of the present embodiment；

Fig. 3 is the structural representation of CPS-SPWM generator based on the inventive method；

Fig. 4 (a) is that asynchronous serial sends Frame schematic diagram；

When Fig. 4 (b) is for enabling block, asynchronous serial sends Frame oscillogram；

When Fig. 4 (c) is for enabling open, asynchronous serial sends Frame oscillogram；

Fig. 5 (a) is single channel triangle carrier signal principle schematic；

Fig. 5 (b) is multichannel phase shift carrier wave principle schematic；

Fig. 6 is the algorithm flow chart of the suppressing method of the logic competition of the present embodiment；

Fig. 7 (a) is that the suppressing method intermediate cam carrier signal of the logic competition of the present embodiment is in rising half cycle The principle schematic during phase；

Fig. 7 (b) is that the suppressing method intermediate cam carrier signal of the logic competition of the present embodiment is in decline half cycle The principle schematic during phase；

Fig. 8 (a) is unloaded adjacent two the concatenated power module ACs when voltage stabilizing of DSTATCOM device Output voltage waveform；

Fig. 8 (b) is the time shaft enlarged drawing of the waveform of Fig. 8 (a)；

DSTATCOM device when Fig. 8 (c) is for using traditional burst pulse detection to eliminate logic competing method Unloaded from voltage stabilizing output many level phase voltage waveform figure；

Fig. 8 (d) is the time shaft enlarged drawing of the waveform of Fig. 8 (c)；

Fig. 8 (e) is that the DSTATCOM of the present embodiment is unloaded from voltage stabilizing output many level phase voltage waveform figure；

Fig. 8 (f) is the time shaft enlarged drawing of the waveform of Fig. 8 (e)；

Output when Fig. 9 (a) is the DSTATCOM compensation 10kV/2Mvar capacity reactive load of the present embodiment Voltage, current waveform figure；

Output when Fig. 9 (b) is the DSTATCOM compensation 10kV/2Mvar capacity reactive load of the present embodiment The low-frequency range harmonic content analysis result figure of electric current.

Detailed description of the invention

Below in conjunction with the drawings and the specific embodiments, the present invention is described in detail.

The present embodiment Sinusoidal Pulse Width Modulation signal logic competition suppressing method be applied to DSP and CPS-SPWM (the one pole frequency multiplication phase-shifted SPWM) generator of FPGA, and CPS-SPWM occurs The CPS-SPWM signal of the suppression logic competition of device output is then for driving three-phase three-wire system as shown in Figure 2 The semiconductor power device of Y-connection H bridge cascade connection multi-level DSTATCOM, makes DSTATCOM to electricity Net injecting compensating electric current, compensates the reactive current that load is consumed, and improves the power factor (PF) of network system.Level Join many level DSTATCOM and mainly include main circuit and master control system two parts:

Main circuit is mainly made up of current transformer, filter inductance L and equivalent resistance R, and current transformer is by H bridge merit (H bridge power cascade module, each power H bridge power model has power model controller to rate module, control Coremaking sheet is CPLD) cascade composition, access electrical network by filter inductance, single-phase containing 12 power models (the present embodiment is H bridge concatenated power module, each power model include four switching device S1, S2, S3 and S4), each power model DC side is independent, the electricity at the electric capacity two ends of DC side in the most each power model Pressure (DC voltage U_dc) independent, a total of 36 road DC voltages, DSTATCOM exports three-phase electricity Pressure is respectively u_ca, u_cbAnd u_cc, output three-phase compensates electric current and is respectively i_ca, i_cbAnd i_cc。u_ca1、u_ca2、……、u_caN It is respectively the A phase first order of DSTATCOM, the second level ..., the friendship of N level concatenated power module Stream side output voltage.

Master control system mainly by one piece of DSP (digital signal processor, the TMS320F2812 of TI company), One piece of FPGA (field programmable gate array, ALTERA company EP3C family chip) and some voltages, The peripheral circuit such as current sensor composition, the line voltage that is used for sampling, load current, compensation circuit and each DC voltage (36 tunnel), and construct pwm signal with to DSTATCOM unsteady flow according to these signals Semiconductor switch device in device is controlled.Based on DSP and FPGA suppression logic competition CPS-SPWM generator is the core of control system.

The concrete structure of CPS-SPWM generator is as it is shown on figure 3, mainly include DSP and FPGA, DSP It is connected by electric signal with FPGA, specially 10 address bus (A0～A9), 16 single data buses (D0～D9), holding wire (S0～S3), sheet selects (CS) and reads (RD), writes (WE) holding wire.

DSP is Master control chip, for sampling, reduce the line voltage of DSTATCOM, load current with And respectively cascade power model DC bus-bar voltage and compensate electric current, and it is the most electric to construct cascade according to collection result The modulated signal of each H bridge power model of flat inverter (the number phase of modulated signal way and power model With), and write FPGA by data/address bus respectively；

FPGA is used for receiving modulated signal, generates phase shift triangle carrier signal, Bing Jiangge road modulated signal and phase The triangle carrier signal answered compares pwm control signal (the i.e. one pole frequency multiplication producing each power model CPS-SPWM signal).FPGA is divided by function loading and includes: caching ram cell, phase shift carrier wave Signal generating unit, the one pole frequency multiplication CPS-SPWM signal generating unit of suppression logic competition (arranges one mutually, divides Wei A phase one pole frequency multiplication CPS-SPWM signal generating unit, B phase one pole frequency multiplication CPS-SPWM signal generating unit With C phase one pole frequency multiplication CPS-SPWM signal generating unit), encode with issue unit (arrange one mutually, point Not Wei A phase encode with issue unit, B phase encodes and issues unit and C phase encodes and issues unit).

Caching ram cell, is used for storing modulated signal, when FPGA receives modulated signal, to address wire Decode, according to decoding result, the data on data/address bus are stored in the corresponding memory element of caching RAM.

Phase shift carrier generation unit, is used for producing periodic multichannel phase shift triangle carrier signal, and FPGA uses Increase and decrease count mode generates triangle carrier signal continuously；

One pole frequency multiplication CPS-SPWM signal generating unit, for believing each road modulated signal with corresponding triangular carrier Number compare produce each power model pwm control signal (i.e. one pole frequency multiplication CPS-SPWM signal, SPWM signal).

Encode and issue unit, for SPWM signal being modulated coding and in asynchronous serial communication mode (UART) send to each power model through downlink optical fiber.Shown in data transmission frames form such as Fig. 4 (a): asynchronous When serial sends, every frame data last 4us, and totally 10 bit data, is 1 start bit respectively, 4 valid data, 1 systematic reset signal and 1 stopping position, remaining is idle condition and is high level.Start bit is low electricity Flat, stopping position is high level；4 valid data signals are followed successively by left brachium pontis and enable signal, left brachium pontis PWM Signal, right brachium pontis enable signal and left brachium pontis pwm signal.Enable signal and (include that left brachium pontis enables signal Signal is enabled with right brachium pontis) high level is open for enabling, and represents that system is normal, and power device can normal switch Work, low level then for enabling block, represents the system failure, blocks pwm control signal；Left brachium pontis PWM The most corresponding H bridge inverter left and right brachium pontis power device (switching device) of signal, right brachium pontis pwm signal Driving signal, high level (1) be upper pipe open down tube turn off, low level (0) is then that down tube is opened Pipe turns off；Quantity of state when reset signal low level is for removing fault latches.

The asynchronous serial that Fig. 4 (b), Fig. 4 (c) sets forth when PWM enables block and enables open sends Frame experimental waveform, wherein in Fig. 4 (b) and Fig. 4 (c), the waveform of lower section is in upper waveform in dotted line frame The time shaft enlarged drawing of part.Enabling signal position in Fig. 4 (b) is low level, the now system failure, all power Device is failure to actuate, and enabling signal position in 4 (c) is high level, represents that system is normal, all power devices according to PWM drive signal is operating normally.

In the present embodiment, DSP writes 5 times of the frequency that frequency is triangle carrier signal of modulated signal, quite Within a triangle carrier signal cycle, modulated signal updates 5 times, wherein triangle carrier signal frequency i.e. merit Rate devices switch frequency is that to write the frequency of modulated signal be 5kHz for 1kHz, DSP.

The present embodiment intermediate cam carrier signal, for being repeated cyclically signal, is used by FPGA and increases and decreases counting continuously Device is simulated, and as shown in Fig. 5 (a), each FPGA clock cycle, the value of enumerator increases by one or reduces one, Enumerator increases from zero to counts peaks, then is gradually reduced to zero, is gradually increased afterwards, moves in circles；With This simultaneously definition status variable updown, when enumerator adds counting, this state variable is set to 1, when enumerator subtracts During counting, this state variable is set to 0.

In the present embodiment, one pole frequency multiplication phase-shifted SPWM strategy needs multichannel phase shift triangle carrier signal, point Not and embodiment cascade connection multi-level DSTATCOM each single-phase in concatenated power module one_to_one corresponding, three-phase Sharing a set of phase shift carrier wave, the amplitude of the most each road triangle carrier signal, frequency are the most identical, simply phase place Difference, the phase contrast of adjacent two-way triangle carrier signal is corresponding time difference T_shiftFor:

$T_{shift}=\frac{T_{sw}}{2N},$

T_swFor the switch periods of power device, equal to the cycle of triangle carrier signal, N is the total of phase shift carrier wave Way, with cascade connection multi-level DSTATCOM single-phase concatenated power equal (the present embodiment of number of modules of embodiment Middle N=12).

In the present embodiment, multichannel phase shift carrier wave realizes by arranging each carrier wave correspondence enumerator in FPGA Counting direction, counting initial value and obtain:

Using the peak value moment of the 1st road triangle carrier signal as the starting point of counting, Bing Linggai road phase shift carrier wave Inceptive direction for subtracting counting, the inceptive direction of remaining carrier wave at different levels is and adds counting.

As shown in Fig. 5 (b), the counting initial value u of kth road phase shift carrier wave₀K () determines according to below equation:

$u_0\left(k\right)=\frac{N-k+1}{N}\×Peak$

Wherein, Peak is the counts peaks of triangle carrier signal, 1≤k≤N.Counts peaks Peak is according to following Formula calculates:

$Peak=\frac{T_{sw}}{2T_{clk}},$

T_clkClock cycle for FPGA.

Logic competition is suppressed to use and rises the half period each of triangle carrier signal and decline half by the present invention In cycle, the PWM level only method for turning when modulated signal is with triangle carrier signal friendship section for the first time, is rising Hand in half period when cutting for the first time, then PWM is low level by high level upset, in declining the half period first When secondary friendship cuts, then PWM is high level by low level upset, for each road triangle carrier signal, algorithm stream Journey is as shown in Figure 6: initialization procedure；

Defining state variable updown, this variable is using clock cycle of FPGA as the update cycle；Definition Two flag bits, correspond respectively to the rising half period of triangle carrier signal and whether decline half period PWM The judgement symbol position overturn, is designated as u_flag and d_flag respectively, in flag bit is the half period that 0 expression is corresponding Pwm signal does not overturns, and in the half period that flag bit is 1 expression correspondence, pwm signal is inverted.

The method of the logic Competitive assays of the present embodiment comprises the steps:

(1) for each FPGA clock cycle, when modulated signal and triangle carrier signal are handed over and are cut, according to Described state variable updown determines the state of triangle carrier signal corresponding to this clock cycle:

If state variable is 0, then corresponding triangle carrier signal is in the rising half period,

Otherwise, corresponding triangle carrier signal is in the decline half period；

(2) judge corresponding flag bit according to the result of step (1) and proceed as follows:

If the flag bit of correspondence is zero, then carries out PWM level upset, and be 1 by mark position；

If the flag bit of correspondence is 1, then PWM level does not overturns；

At the end of half period, this flag bit is set to zero again.

Fig. 7 (a) and Fig. 7 (b) gives the PWM principle schematic of logic Competitive assays, three in figure In the rising half period of angle carrier signal or decline half period, modulated signal is handed over triangle carrier signal and is cut repeatedly, But PWM level only overturns once, compete without logic.

Fig. 8 (a) and Fig. 8 (b) is that the suppressing method DSTATCOM device zero load using the present embodiment is from voltage stabilizing Time A phase in adjacent two concatenated power modules (first concatenated power module and second concatenated power module) AC output voltage waveforms, the waveform that the waveform during wherein Fig. 8 (b) is Fig. 8 (a) amplifies through time shaft, The phase contrast of two-stage voltage waveform is approximately 45us, coincide with design load, illustrates CPS-SPWM generator The CPS-SPWM degree of accuracy produced is high, and the most single power model unit output SPWM waveform does not exist patrols Volume competition, it was demonstrated that the reliability of logic Competitive assays method used by the present invention.Fig. 8 (c) and Fig. 8 (d) is for adopting When eliminating logic competing method with traditional burst pulse detection, DSTATCOM device is unloaded the most electric from voltage stabilizing output Flat SPWM phase voltage waveform, the waveform that the waveform during wherein Fig. 8 (d) is Fig. 8 (c) amplifies through time shaft. When Fig. 8 (e) and Fig. 8 (f) uses present implementation, DSTATCOM device is unloaded exports many level from voltage stabilizing SPWM phase voltage waveform, has more error level to go out on level step when using traditional method as seen from the figure Existing, fft analysis shows that its total harmonic distortion factor is 2.15%, mainly due to intrinsic the prolonging of detection introducing Time belong to the same order of magnitude with the phase shift width of 12 grades of phase-shifting carrier wave adjacent carriers, level many to output voltage Overlay interference is the biggest.And when using present implementation, on level step, substantially do not have error level to occur, Fft analysis shows that its total harmonic distortion factor is only 0.91%, sine degree is more preferable, it was demonstrated that present implementation is just Really property, superiority.

Fig. 9 (a) for use present embodiment time DSTATCOM compensate 10kV/2Mvar capacity reactive load time Output phase voltage u_caWith compensation electric current i_caWaveform, Fig. 9 (b) for output electric current i_caLow-frequency range harmonic content analyze Result.Wherein output electric current i_caTotal harmonic distortion factor (THD) be only 1.18%, far below relevant criterion Required value, effect is satisfactory.

In the present embodiment in all oscillograms, not making specified otherwise, transverse axis is time shaft, and the longitudinal axis is amplitude, / div represents every lattice.With u in Fig. 8 (b)_ca-2kV/div, as a example by 500 μ s/div, represents phase voltage u_caThe vertical seat of place figure Being designated as the every lattice of 2kV, abscissa is the 500 every lattice of μ s.

The specific embodiment being only the present invention disclosed above, but protection scope of the present invention is not limited to This, any those of ordinary skill in the art can carry out various change and modification without deviating from this to the present invention The spirit and scope of invention, all should contain within the protection domain of this practicality invention.

Claims (7)

1. the suppressing method of a Sinusoidal Pulse Width Modulation PWM logic competition, it is characterised in that at triangle In each rising half period of carrier signal and decline half period, PWM level only carries with triangle in modulated signal The friendship for the first time of ripple signal overturns when cutting, and when within the rising half period, friendship cuts for the first time, then PWM is turned over by high level Transferring low level to, when declining friendship section for the first time in the half period, then PWM is high level by low level upset.

2. the suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition as claimed in claim 1, it is special Levying and be, described Sinusoidal Pulse Width Modulation realizes based on DSP and FPGA, and modulated signal is write by DSP Enter FPGA.

3. the suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition as claimed in claim 2, it is special Levying and be, the frequency of writing of described modulated signal is more than 2 times of described triangle carrier signal frequency.

4. the Sinusoidal Pulse Width Modulation PWM logic as described in any one claim in claims 1 to 3 The suppressing method of competition, it is characterised in that described triangle carrier signal is the signal being repeated cyclically, by FPGA uses the simulation of continuous up-down counter, each FPGA clock cycle, and the value of enumerator increases by one or subtracts Few one, enumerator increases from zero to counts peaks, then is gradually reduced to zero, is gradually increased afterwards, circulates past Multiple.

5. the suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition as claimed in claim 4, it is special Levy and be, described suppressing method include arranging one for the state variable representing counter counts number state, When enumerator is in increase counting, this state variable is set to 1, on the contrary this state when enumerator is in and subtracts counting Variable is set to 0.

6. the suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition as claimed in claim 5, it is special Levying and be, described suppressing method includes arranging two flag bits, respectively upper with described triangle carrier signal The liter half period is corresponding with declining the half period, and this flag bit of initial time in each half period is 0, at PWM During level monitoring once inside out, it is 1 by corresponding mark position.

7. the suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition as claimed in claim 6, it is special Levy and be, including:

(1) for each FPGA clock cycle, when modulated signal and triangle carrier signal are handed over and are cut, according to Described state variable determines the state of triangle carrier signal corresponding to this clock cycle:

If state variable is 0, then corresponding triangle carrier signal is in the rising half period,

Otherwise, corresponding triangle carrier signal is in the decline half period；

(2) judge corresponding flag bit according to the result of step (1) and proceed as follows:

If the flag bit of correspondence is zero, then carries out PWM level upset, and be 1 by mark position；

If the flag bit of correspondence is 1, then PWM level does not overturns；

At the end of half period, this flag bit is set to zero again.