CN102118103A - Smooth narrow pulse compensating method of FPGA in frequency converter - Google Patents
Smooth narrow pulse compensating method of FPGA in frequency converter Download PDFInfo
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- CN102118103A CN102118103A CN2011100056785A CN201110005678A CN102118103A CN 102118103 A CN102118103 A CN 102118103A CN 2011100056785 A CN2011100056785 A CN 2011100056785A CN 201110005678 A CN201110005678 A CN 201110005678A CN 102118103 A CN102118103 A CN 102118103A
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Abstract
The invention discloses a smooth narrow pulse compensating method of an FPGA (field programmable gate array) in a frequency converter, which comprises the steps as follows: judging whether an input modulating wave is a narrow pulse, if not, outputting the waveform, and if the value is stored in a narrow pulse register, not generating a waveform currently; inputting the modulating wave again, and judging whether the value is a narrow pulse, if not, outputting the waveform, if yes, accumulating the value; judging whether the sum of accumulated values is larger than or equal to the narrow pulse upper limit, if yes, outputting the waveform; and if the modulating wave is a narrow pulse, and the sum of accumulated values of the narrow pulse register is smaller than the narrow pulse upper limit, accumulating the current value in the narrow pulse register, and not outputting the wave. By taking the measure, an additional hardware circuit is not needed, thus being capable of guaranteeing smooth waveforms to be output at a position of a sinusoidal wave at which a narrow pulse is generated, effectively reducing the switching frequency of a power device, the heat generated by the device and harmonic content of the system, increasing the effective output level of the device, and improving the efficiency of the whole system.
Description
Technical field
The present invention relates to a kind of narrow pulse width compensation technique, is the compensation method that FPGA realizes level and smooth burst pulse in a kind of frequency converter specifically.
Background technology
The present invention relates to a kind of in middle pressure, in the powerful frequency converter drive system, because of there is burst pulse in electronic power switch device drive waveform, especially when low frequency, when promptly opening drive signal and also not making the complete conducting of device, turn-off drive signal and make its disconnection again, the switch power device just is operated in the amplification region like this, does not enter the operate in saturation district, causes switching loss to increase, cause device heating, and can not export significant level, when influencing device lifetime, introduce and disturb, cause greater impact to backward diode, cause the total harmonic distortion (THD) of output line voltage to increase, increase line voltage negative sequence component, cause the runnability variation of motor.
For fear of the generation of above problem, solution commonly used at present is directly to delete burst pulse.As not compensating, can cause output waveform seriously to distort when low frequency after the direct deletion burst pulse, the output starting torque reduces, voltage harmonic increases, and problems such as even-order harmonic appear in imbalance of three-phase voltage, these problems will have a strong impact on the runnability of system, reduce the efficient of system.
Summary of the invention
Goal of the invention: the technical problem to be solved in the present invention is, provides a kind of and guarantees that each drive waveforms can both make insulated gate bipolar transistor (IGBT) export effective waveform, and actual output waveform and reference value are consistent, and guarantees the level and smooth of motor torque.
FPGA realizes the compensation method of level and smooth burst pulse in a kind of frequency converter, and it comprises the steps:
(1) in FPGA inside, judges whether the value of input modulating wave is burst pulse: if the input modulating wave is not a burst pulse, then change step 105 over to, FPGA output PWM waveform; If the input modulating wave is a burst pulse, then change step 102 over to, FPGA is saved in the value of this input modulating wave in the burst pulse register, the current PWM waveform that do not produce;
(2) import modulating wave once more, be transferred to step 101, whether the value that rejudges this input modulating wave is burst pulse: if not, change step 105 over to, FPGA output PWM waveform; And the value of output modulating wave is the value of input modulating wave and the value sum in the burst pulse register, the zero clearing of burst pulse register;
If the input modulating wave is a burst pulse, then change step 102 over to, the input modulating wave is added in the burst pulse register; Change step 103 then over to, judge that accumulated value sum in the burst pulse register is whether more than or equal to the burst pulse higher limit: if the accumulated value sum is more than or equal to the burst pulse higher limit, then change step 104 over to, i.e. FPGA output width is the PWM waveform of burst pulse higher limit; Surplus value in the burst pulse register is that burst pulse register accumulated value sum deducts the burst pulse higher limit;
If the current input modulating wave of FPGA is a burst pulse, and, then current input modulation wave number is added in the burst pulse register during less than the burst pulse higher limit with the accumulated value sum of burst pulse register, export modulating wave this moment is zero, and FPGA does not export the PWM ripple.
Wherein, in the step (1), if the input modulating wave then is not a burst pulse more than or equal to the burst pulse higher limit; If the input modulating wave then is a burst pulse less than the burst pulse higher limit.
Wherein, described burst pulse higher limit is 3us.
In FPGA (field programmable gate array), produce a series of pwm pulse ripples (pulse width modulation ripple) by modulating wave and carrier wave ratio, FPGA judges the pwm pulse ripple of output, corresponding burst pulse is carried out appropriate processing.When FPGA judges when not being burst pulse, then directly export current waveform, when FPGA judges when being burst pulse, then wouldn't export current value, preserve the value of current burst pulse, the value of the burst pulse register of preserving as FPGA and current input modulating wave with, to can make the effective conducting of power device the time, FPGA exports this value, produces corresponding PWM waveform.But in order to export more level and smooth SPWM waveform, output PWM width will be done suitable processing, when guaranteeing to make the effective conducting of power device, for guaranteeing the level and smooth of motor current waveform, the PWM waveform of output is broadened suddenly, carry out certain restriction when output to the size of accumulated value, the size of this limits value is the burst pulse higher limit.
Beneficial effect: 1, in FPGA controller inside, the burst pulse that produces is carried out suitable adding up, then according to the requirement of effective impulse, export the drive signal of minimum effective impulse, to locate waveform more more level and smooth in Zheng Xianbo friendship like this, and the conducting number of times of device effectively reduces, and device heating reduces, and the harmonic content of output waveform reduces, and systematic function is significantly improved.2, take this burst pulse indemnifying measure, do not need extra hardware circuit, just can guarantee to occur the waveform of burst pulse place output smoothing at sine wave, effectively reduce the switching frequency of power device, reduce the heating of device, reduce the harmonic content of system, increase effective output level of device, improve overall system efficiency, system performance is significantly improved.
Description of drawings
Fig. 1 is a flow chart of the present invention.
Fig. 2 is the phase voltage and the phase current of existing frequency converter output.
Fig. 3 is for using the phase voltage and the phase current of method frequency converter output of the present invention.
Phase voltage and phase current that Fig. 4 amplifies for the part of existing frequency converter output.
Fig. 5 uses local phase voltage and the phase current that amplifies of method frequency converter output of the present invention.
Embodiment:
Below in conjunction with accompanying drawing the utility model is done further explanation.
As shown in Figure 1, FPGA realizes that the compensation method of level and smooth burst pulse comprises the steps: in the frequency converter of the present invention
Does 1, beginning in FPGA (field programmable gate array) inside, judge that the value of input modulating wave is a burst pulse? the higher limit of general burst pulse is 3us, if more than or equal to 3us, then is not burst pulse; If less than 3us, then be burst pulse.
If the input modulating wave is not a burst pulse, then change step 105 over to, FPGA output PWM waveform, the value of output modulating wave is the value of input modulating wave, a loop ends.If promptly the value of input modulating wave is 4us, then FPGA exports 4us PWM waveform; If the value of input modulating wave is 3us, then FPGA exports 3us PWM waveform.
If 2 input modulating waves are burst pulses, then change step 102 over to, FPGA is saved in the value of this input modulating wave in the burst pulse register, the current PWM drive waveforms that do not produce.The value of for example importing modulating wave is 2us, and then FPGA does not export the PWM waveform, and 2us is added in the burst pulse register.A loop ends.
3, to import modulating wave once more, be transferred to step 101, is the value that rejudges this current input modulating wave a burst pulse? if not, change step 105 over to, FPGA output PWM waveform; The value of output modulating wave is the value of current input modulating wave and the value sum in the burst pulse register, the zero clearing of burst pulse register.For example: if the value of input modulating wave is 4us, then FPGA exports the PWM waveform, and the value of output modulating wave is 6us, is the pulse value 2us sum that stores in current input modulating wave 4us and the burst pulse register.A loop ends.
If the input modulating wave is a burst pulse, then change step 102 over to, the input modulating wave is added in the burst pulse register.
Change step 103 over to, judge that input modulating wave accumulated value sum in the burst pulse register is more than or equal to the burst pulse higher limit? if the accumulated value sum more than or equal to the burst pulse higher limit, then changes step 104 over to, FPGA output width is the PWM waveform of 3us; Surplus value in the burst pulse register deducts the burst pulse higher limit for the accumulated value sum.For example importing modulating wave is 2us, then is added in the burst pulse register, adds up with the 2us of original accumulative total in the burst pulse register, and sum of the two is 4us, greater than the burst pulse higher limit, and FPGA output 3us PWM waveform then.Remaining value is 1us in the burst pulse register.A loop ends.
If the current input modulating wave of FPGA is a burst pulse, and, then current input modulating wave is added in the burst pulse register during less than the burst pulse higher limit with the accumulated value sum of burst pulse register, export modulating wave this moment is zero, and FPGA does not export the PWM ripple.If promptly the input modulating wave is less than the burst pulse higher limit, then FPGA does not export, and accumulated value in the burst pulse register and input modulating wave sum are more than or equal to the burst pulse higher limit, and then FPGA exports the pulse that pulse value is the burst pulse higher limit again; Remaining pulse value is the aggregate-value and input modulating wave sum in the burst pulse register in the burst pulse register, removes the burst pulse higher limit again.
For the effect of the inventive method and existing method relatively, Fig. 2 with Figure 3 shows that under all identical condition of used experiment condition, frequency converter operates in unloaded phase voltage, the phase current waveform of 1HZ.
Fig. 2 is the phase voltage and the phase current waveform of existing frequency converter output, when the PWM of output is burst pulse, directly delete burst pulse, because of when low frequency, major part all is a burst pulse, and only near the peak value of sine wave, the modulating wave reference value is during greater than the burst pulse higher limit, output is just arranged, the non-constant of current waveform smoothness at this moment.Fig. 4 is the local waveform amplification of Fig. 2.
Fig. 3 is for using phase voltage, the phase current waveform of method frequency converter output of the present invention, and burst pulse is carried out the output of PWM waveform also being arranged after the inventive method handles near the zero point of sine wave, and at this moment the smoothness of current waveform obviously improves.Fig. 5 is near Fig. 3 local waveform amplification zero point of sine wave.
Shown in Fig. 2 to Fig. 5 figure: 2.50A is the unit ordinate value of current waveform; 100V is the unit ordinate value of voltage waveform; 400ms, 800us and 10ms are the abscissa unit interval value of voltage current waveform; M time/second is oscillographic per second sampling number.
Claims (3)
1. FPGA realizes the compensation method of level and smooth burst pulse it is characterized in that it comprises the steps: in the frequency converter
(1) in FPGA inside, judges whether the value of input modulating wave is burst pulse: if the input modulating wave is not a burst pulse, then change step 105 over to, FPGA output PWM waveform; If the input modulating wave is a burst pulse, then change step 102 over to, FPGA is saved in the value of this input modulating wave in the burst pulse register, the current PWM waveform that do not produce;
(2) import modulating wave once more, be transferred to step 101, whether the value that rejudges this input modulating wave is burst pulse: if not, change step 105 over to, FPGA output PWM waveform; And the value of output modulating wave is the value of input modulating wave and the value sum in the burst pulse register, the zero clearing of burst pulse register;
If the input modulating wave is a burst pulse, then change step 102 over to, the input modulating wave is added in the burst pulse register; Change step 103 then over to, judge that accumulated value sum in the burst pulse register is whether more than or equal to the burst pulse higher limit: if the accumulated value sum is more than or equal to the burst pulse higher limit, then change step 104 over to, i.e. FPGA output width is the PWM waveform of burst pulse higher limit; Surplus value in the burst pulse register is that burst pulse register accumulated value sum deducts the burst pulse higher limit;
If the current input modulating wave of FPGA is a burst pulse, and, then current input modulation wave number is added in the burst pulse register during less than the burst pulse higher limit with the accumulated value sum of burst pulse register, export modulating wave this moment is zero, and FPGA does not export the PWM ripple.
2. FPGA realizes the compensation method of level and smooth burst pulse in a kind of frequency converter according to claim 1, it is characterized in that, in the step (1), if the input modulating wave then is not a burst pulse more than or equal to the burst pulse higher limit; If the input modulating wave then is a burst pulse less than the burst pulse higher limit.
3. FPGA realizes the compensation method of level and smooth burst pulse in a kind of frequency converter according to claim 1 and 2, it is characterized in that, described burst pulse higher limit is 3us.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124858A (en) * | 2014-05-29 | 2014-10-29 | 浙江大学 | Sine pulse width modulation PWM (pulse-width modulator) logic competition inhibiting method |
| CN107741727A (en) * | 2017-11-16 | 2018-02-27 | 湖南工业大学 | books automatic sorting control system |
| CN107966926A (en) * | 2017-11-16 | 2018-04-27 | 湖南工业大学 | Books automatic sorting control device |
| CN110729892A (en) * | 2019-10-24 | 2020-01-24 | 苏州海鹏科技有限公司 | Boost controller based on PWM-PFM hybrid modulation and control method |
| CN111669104A (en) * | 2020-05-25 | 2020-09-15 | 深圳市兆威机电股份有限公司 | Motor driving method, device, terminal and storage medium |
Citations (1)
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| CN1094873A (en) * | 1993-02-04 | 1994-11-09 | 株式会社东芝 | Power converter control system |
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- 2011-01-12 CN CN2011100056785A patent/CN102118103A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1094873A (en) * | 1993-02-04 | 1994-11-09 | 株式会社东芝 | Power converter control system |
Non-Patent Citations (2)
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| 冉旺等: "基于零序电压注入的三电平逆变器窄脉冲补偿方法研究", 《2008中国电工技术学会电力电子学会第十一届学术年会论文集》, 31 December 2008 (2008-12-31), pages 1 - 6 * |
| 薄保中等: "三电平逆变器PWM控制窄脉冲补偿技术的研究", 《中国电机工程学报》, vol. 25, no. 10, 31 May 2005 (2005-05-31), pages 60 - 64 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124858A (en) * | 2014-05-29 | 2014-10-29 | 浙江大学 | Sine pulse width modulation PWM (pulse-width modulator) logic competition inhibiting method |
| CN104124858B (en) * | 2014-05-29 | 2017-01-04 | 浙江大学 | A kind of suppressing method of Sinusoidal Pulse Width Modulation PWM logic competition |
| CN107741727A (en) * | 2017-11-16 | 2018-02-27 | 湖南工业大学 | books automatic sorting control system |
| CN107966926A (en) * | 2017-11-16 | 2018-04-27 | 湖南工业大学 | Books automatic sorting control device |
| CN110729892A (en) * | 2019-10-24 | 2020-01-24 | 苏州海鹏科技有限公司 | Boost controller based on PWM-PFM hybrid modulation and control method |
| CN111669104A (en) * | 2020-05-25 | 2020-09-15 | 深圳市兆威机电股份有限公司 | Motor driving method, device, terminal and storage medium |
| CN111669104B (en) * | 2020-05-25 | 2021-11-23 | 深圳市兆威机电股份有限公司 | Motor driving method, device, terminal and storage medium |
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Application publication date: 20110706 |