CN218648885U - High-speed long-line-array CMOS detector imaging circuit - Google Patents

Abstract

The utility model discloses a high-speed long line CMOS detector imaging circuit, including image sensor, drive circuit and number transmission circuit, image sensor respectively with drive circuit and number transmission circuit electric connection, image sensor includes that inside contains the GL1608 chip of 128 registers, drive circuit includes detector peripheral circuit and requires to act on clock, reset, power enable and drive SPI bus driver according to CMOS detector start-up order in proper order and carries out register configuration, control CMOS detector frame frequency and the sequential circuit of total mark time to CMOS; the utility model discloses a data cache circuit and the high-speed signal transmission circuit of large capacity buffer memory have solved high-speed data output problem, satisfy high-resolution high speed detector's demand, use at high-resolution high-speed formation of image field for photosensitive element through the home-made CMOS image sensor who uses GL1608 chip.

Description

High-speed long-line-array CMOS detector imaging circuit

Technical Field

The utility model relates to a CMOS detector imaging circuit technical field specifically is a high-speed long line CMOS detector imaging circuit.

Background

The CMOS detector is a semiconductor device applied to visible light wave band imaging, and the device is integrated by a photodiode, an analog-to-digital converter, a signal amplifier, a row/column driving device and a signal transmission and control device. The CMOS detector has the advantages of high integration level, low power consumption, low cost, strong radiation resistance and the like. The high-resolution imaging system plays an important role in the fields of space remote sensing, industrial detection, medical imaging and the like. With the rapid development of semiconductor design and processing technology, the performances of the CMOS detector in the aspects of resolution, noise suppression, radiation resistance and the like are broken through. The CMOS detector further expands the application of the CMOS detector in high-end fields such as star sensors, earth observation, deep space exploration and the like.

In the field of space remote sensing, visible light imaging detection is an important component of space detection, and the visible light detection technology refers to a remote sensing technology with a sensor working in a 400-650nm waveband. At present, in order to acquire image data with higher resolution, the requirements on the resolution and the observation width of a remote sensing camera are higher and higher, and a visible light CMOS detector with a longer linear array or a photoetching and splicing mode of a plurality of detectors is needed to meet the requirements on the high resolution and the width.

At present, the total length of a single-chip long-linear-array visible light detector is generally 10cm-20cm, the number of pixels in a single row reaches 16K or 32K, the line scanning frequency tends to be ten thousand levels, the quantity of generated image data is rapidly increased, the transmission bandwidth is continuously increased, the acquisition rate is improved, and higher requirements on data acquisition, transmission and reliable storage technologies are provided.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a high-speed long line CMOS detector imaging circuit, through image sensor, drive circuit and data transmission circuit's cooperation, the data cache circuit and the high-speed signal transmission circuit that adopt large capacity buffer memory have solved high-speed data output problem, satisfy high-resolution high-speed detector's demand to solve the problem that proposes in the background art.

In order to achieve the above object, the utility model provides a following technical scheme: a high-speed long-linear-array CMOS detector imaging circuit comprises an image sensor, a driving circuit and a data transmission circuit, wherein the image sensor is electrically connected with the driving circuit and the data transmission circuit respectively, and comprises a GL1608 chip internally provided with a 128 register; the drive circuit comprises a detector peripheral circuit and a sequential circuit which sequentially acts on a clock, resets, enables a power supply and drives an SPI bus driver to perform register configuration on the CMOS and control the frame frequency and the integration time of the CMOS detector according to the starting sequence requirements of the CMOS detector, and the detector peripheral circuit is electrically connected with the sequential circuit; the data transmission circuit comprises a data cache circuit with a large-capacity cache, a digital image processing circuit and a high-speed signal transmission circuit, wherein the digital image processing circuit is electrically connected with the data cache circuit and the high-speed signal transmission circuit respectively.

Preferably, the sequential circuit includes an integration control circuit for performing logic calculation on the user input information, a frame frequency control circuit for controlling the scanning line frequency of the detector, and a register configuration circuit, and both the integration control circuit and the frame frequency control circuit are electrically connected to the register configuration circuit.

Preferably, the register configuration circuit includes a counter, a serial-parallel conversion circuit for continuously buffering a serial input 1-bit digital signal into a 12-bit shift register, a data alignment circuit for comparing serial-parallel converted data with correct data, a trigger pulse generation circuit for controlling the counter to keep or count, and a latch for storing an external signal in the internal register, the counter is electrically connected to the serial-parallel conversion circuit, the serial-parallel conversion circuit is electrically connected to the data alignment circuit, the data alignment circuit is electrically connected to the trigger pulse generation circuit, and the trigger pulse generation circuit is electrically connected to the latch.

Preferably, the peripheral circuit of the detector comprises a power circuit, a bias circuit and an external digital interface circuit, the power circuit is electrically connected with the image sensor and the bias circuit respectively, the bias circuit is electrically connected with the external digital interface circuit, and the external digital interface circuit is electrically connected with the sequential circuit.

Preferably, the power circuit comprises a power chip, the power chip is a TPS74801LDO power chip, a seven pin of the power chip is connected with CC2, CC1 is connected between one end of the CC2 and one pin of the power chip, RC2 is connected between six pins and eight pins of the power chip, RC1 is connected between eight pins and nine pins of the power chip, and CC3 is connected between eleven pins and nine pins of the power chip.

Preferably, the data cache circuit comprises a DDR3-SDRAM chip, and the DDR3-SDRAM chip comprises four 512MB memories and 32bit wide.

Preferably, the digital image processing circuit comprises an image processor with the model number of XC7Z035-FFG676-21, and the image processor is respectively connected with the image sensor and the DDR3-SDRAM chip.

Preferably, the high-speed signal transmission circuit comprises an ethernet transmitter and an upper computer, the ethernet transmitter is electrically connected with the upper computer, and the upper computer is connected with the data processor through an RS232 interface.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses mainly through image sensor, drive circuit and data transmission circuit's cooperation, the data cache circuit and the high-speed signal transmission circuit that adopt large capacity cache have solved high-speed data output problem, satisfy high-resolution high speed detector's demand.

Drawings

FIG. 1 is a schematic diagram of the hardware circuit architecture of the present invention;

FIG. 2 is a logic level division diagram of the sequential circuit of the present invention;

fig. 3 is an interface diagram of input/output data of the CMOS controller of the present invention;

fig. 4 is an input data interface diagram of the CMOS controller of the present invention;

fig. 5 is an output data interface diagram of the CMOS controller of the present invention;

FIG. 6 is a CMOS drive control module state machine of the present invention;

fig. 7 is a circuit diagram of the power chip of the present invention;

fig. 8 is a circuit diagram of a GL1608 chip of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.

Referring to fig. 1-8, the present invention provides a technical solution: a high-speed long-linear-array CMOS detector imaging circuit comprises an image sensor, a driving circuit and a data transmission circuit, wherein the image sensor is electrically connected with the driving circuit and the data transmission circuit respectively, and comprises a GL1608 chip internally provided with a 128 register; as shown in fig. 8, a GL1608 chip integrates a plurality of functional blocks such as a sampling circuit, an amplifying circuit, a digital-to-analog conversion circuit, a row-column pixel transfer, etc., each of which needs to provide a separate power supply and bias driving. The current commonly used power supply chip comprises a DC-DC power supply chip and an LDO power supply chip, and the characteristics and the differences of the two power supply chips are as follows: the DC-DC is a device for converting a direct current power supply with a fixed voltage range into other direct current power supplies with fixed voltage, and although the conversion efficiency of the switch-type power supply is obviously improved, the problem of large output ripple waves is also caused, so that the problems of noise, EMI (electro-magnetic interference), poor load response and the like are caused; the LDO is a low dropout regulator that can only be used in an application environment where the output voltage is less than the input voltage, and can provide a load current to ensure the output voltage to be stable. The advantages of such a voltage converter are low noise and small ripple. Compared with DC-DC, the LDO chip has smaller noise. Since the image sensor is very sensitive to noise, the increase of external noise will affect the CMOS imaging quality, so the TPS74801LDO power chip is used as the power source of the GL1608 chip. The corresponding input and output resistors are adjusted to output different voltages, and the shunt capacitor is added for decoupling. The control signals are composed of SPI _ CLK, SPI _ READ and SPI _ SYNC, thus defining the SPI data transmission protocol. The photoelectric conversion circuit in the GL1608 converts the collected optical signal into an analog electrical signal, converts the analog electrical signal into a digital signal through the ADC, and finally converts the digital signal into an LVDS signal through the level conversion circuit for output. Since the output signal of the single-ended I/O port of the ZYNQ-7035 is TTL level, the input control signal port of the detector can be directly connected to the bank4 pin. The 32 pairs of LVDS image data interfaces and the 1 pair of LVDS reference clock interfaces are directly connected to LVDS pins of HR-bank2 of ZYNQ-7035.

The drive circuit comprises a detector peripheral circuit and a sequential circuit which sequentially acts on a clock, resets, enables a power supply and drives an SPI bus driver to perform register configuration on the CMOS and control the frame frequency and the integration time of the CMOS detector according to the starting sequence requirements of the CMOS detector, and the detector peripheral circuit is electrically connected with the sequential circuit; the data transmission circuit comprises a data cache circuit with a large-capacity cache, a digital image processing circuit and a high-speed signal transmission circuit, wherein the digital image processing circuit is electrically connected with the data cache circuit and the high-speed signal transmission circuit respectively;

the time sequence circuit comprises an integral control circuit used for carrying out logic calculation on user input information, a frame frequency control circuit used for controlling the scanning line frequency of the detector and a register configuration circuit, wherein the integral control circuit and the frame frequency control circuit are both electrically connected with the register configuration circuit, the time sequence circuit needs to divide all functional modules into a plurality of secondary units, then divides all the secondary units into basic units of the next stage until the basic modules or IP cores can be used. And the input/output interface and resources of each module need to be evaluated, when the sub-modules are instantiated in the top-level file, the data transmission rate and data bit width of all interfaces need to be matched, and the logical level division is shown in fig. 2. The system consists of the following modules; the CMOS detector starting sequence requires to act on a clock, reset, power enable and drive an SPI bus driver in sequence to configure a register of the CMOS, and control the frame frequency and the integration time of the CMOS detector. The CMOS start-up sequence is shown in fig. 3. The sequential circuit mainly comprises functions of configuring a register, controlling integration, frame frequency, triggering control and the like. The input and output interface comprises a clock signal, a reset signal, an SPI interface signal, a time sequence control signal, a DDR3-SDRAM read-write control signal and an LVDS data channel. The method mainly realizes the startup of the CMOS detector and the receiving of image data in sequence through a main state machine. The input-output data interface of the CMOS controller and its meaning are shown in fig. 4 and 5. The CMOS drive control module state machine is shown in fig. 6, which is the main state machine of the core processing board ZYNQ. IDLE: an initial state. Reset enters POWER UP state. Power _ UP: the digital power supply, CLK _ CMOS, RST _ CMOS, analog power supply are sequentially changed. After these change, the REG _ CONFIG state is entered. REG _ CONFIG: and requesting configuration data to the upper computer, and after uploading the configuration data, performing read-write operation on the CMOS through the SPI bus. All registers enter the TRAINING state after they have been configured. TRAINING: after the configuration is completed, the CMOS image output channel transmits training data, and the training data is subjected to word alignment training. After the alignment is finished, the WORKING state is entered. WORKING: after the word alignment training is completed, the frame frequency and trigger control module starts to work to generate periodic trigger pulses. POWER _ DOWN: the CMOS register is set to a standby state and then the power is turned off in sequence.

The frame rate and trigger control design process is as follows, a counter starts to count up from 0 after the training data completes the word alignment. And resetting after counting a fixed number, then increasing automatically, and repeating the steps in a circulating way. One period represents a period of one frame. And the upper computer transmits a value through serial port configuration, and the value represents the integration time. When the counter is 0, a rising edge of the trigger signal is generated, and when the counter equals this value, a falling edge of the trigger signal is generated. In this way, a trigger signal can be generated that is in accordance with the frame rate and the integration time. This signal is passed to the CMOS detector, which can control its frame rate and integration time. Only after the word alignment training is completed, the counter starts a self-increment- > reset cycle. The trig _ out is 1 when the counter is 0, and is 0 when the upper 16 bits of the counter are equal to the length _ integration.

The register configuration circuit comprises a counter, a serial-parallel conversion circuit for continuously caching a 1-bit digital signal input in series into a 12-bit shift register, a data alignment circuit for comparing data obtained by serial-parallel conversion with correct data, a trigger pulse generation circuit for controlling the counter to keep or count, and a latch for storing an external signal in an internal register, wherein the counter is electrically connected with the serial-parallel conversion circuit, the serial-parallel conversion circuit is electrically connected with the data alignment circuit, the data alignment circuit is electrically connected with the trigger pulse generation circuit, and the trigger pulse generation circuit is electrically connected with the latch.

The frame frequency control circuit inputs information by a user, writes the information into an internal register of the CMOS detector through the SPI, and controls the detector to scan the line frequency; the integral control circuit is used for carrying out logic calculation on user input information, when an integral control instruction is issued, the integral time is calculated, the counter starts to count, when a specified count value is reached, the logic circuit sends an instruction, the counter is instructed to stop counting through a trigger pulse generated by the trigger pulse generating circuit, and the counter is cleared; the trigger pulse generating circuit comprises a switch array and a logic operation module, and a trigger pulse signal generated by the trigger pulse generating circuit is fed back to an enabling end of the counter to control the calculator to keep or count; the serial-parallel conversion circuit continuously buffers a 1-bit digital signal input in series into a 12-bit shift register. When the shift register is full, sending the value of the digital signal in the register to a data alignment circuit; after the data alignment circuit main state machine enters word alignment training, SYNC is pulled to be high, and then the detector output interface continuously outputs training words. Comparing the data obtained by serial conversion and the correct data in the training process, and if the data is incorrect, moving a sampling window until the correct data is obtained; and a latch for holding the external signal in the internal register under the control of the PULSE signal when the external signal is temporarily received.

The detector peripheral circuit comprises a power supply circuit, a bias circuit and an external digital interface circuit, wherein the power supply circuit is electrically connected with the image sensor and the bias circuit respectively, the bias circuit is electrically connected with the external digital interface circuit, and the external digital interface circuit is electrically connected with the sequential circuit.

The power circuit comprises a power chip, as shown in fig. 7, the power chip is a TPS74801LDO power chip, a seven pin of the power chip is connected with a CC2, a CC1 is connected between one end of the CC2 and one pin of the power chip, an RC2 is connected between six pins and eight pins of the power chip, an RC1 is connected between eight pins and nine pins of the power chip, and a CC3 is connected between eleven pins and nine pins of the power chip.

The data cache circuit comprises a DDR3-SDRAM chip, the DDR3-SDRAM chip comprises four memories of 512MB and 32bit wide, when a frame trigger signal has a falling edge, representing the end of a CMOS integration stage, each channel outputs 1024 bytes of image data outwards. Correspondingly, the external circuit writes the image data into the DDR 3-SDRAM. And simultaneously, giving correct addresses to the data, wherein each pixel point has three coordinate values, namely a line and a channel, and a pixel in the channel in the line. As the address bits of the DDR3-SDRAM are known to have 16 bits, the concatenation of three coordinate values (counter) of (cnt _ line, cnt _ channel, cnt _ pix _ in _ line) can be used as the address. And carrying out data processing after buffering one frame, and waiting for the arrival of the next frame of data.

The digital image processing circuit comprises an image processor with the model number of XC7Z035-FFG676-21, the image processor is respectively connected with the image sensor and the DDR3-SDRAM chip, the digital image processing circuit adopts a linear interpolation algorithm to restore RGB, the color component of an inserted pixel value is in a linear relation with adjacent pixels around the pixel, the used linear sensor uses two columns of pixels, and each column of pixels is divided into 16 columns to read LVDS; taking a 2 × 2sub-module as an example, in order to make the values in the four shift registers stored by the 2 × 2sub-module at the same time, shift registers are added as buffers, the length of the shift registers being equal to the number of pixels contained in a row of the sensor image. 4 8-bit registers line11, line12, line21 and line22 are defined to respectively store data of two input ports. The digital image processing circuit outputs RGB value of each pixel as the sum of three components of R, G and B after linear interpolation is carried out on input Bayer data, and the gray level pixels are converted into true color by a linear interpolation method and are sent to the high-speed signal transmission circuit.

The high-speed signal transmission circuit comprises an Ethernet transmitter with more than ten thousand megabytes and an upper computer, the Ethernet transmitter is electrically connected with the upper computer, the upper computer is connected with the data processor through an RS232 interface, the high-speed signal transmission circuit takes the SFP + optical module as a data transmission interface, and due to the fact that control options of the UDP protocol are few, delay in the data transmission process is small, and data transmission efficiency is high. The high-speed signal transmission circuit has the functions of realizing the communication between the hardware platform and the upper computer, sending uncompressed image data to the upper computer and receiving instructions of the upper computer for corresponding processing. Because the data is transmitted in a single direction, the data volume is large, and the reliability requirement is not high, a UDP transmission protocol is adopted.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (8)

1. A high-speed long-line-array CMOS detector imaging circuit comprises an image sensor, a driving circuit and a data transmission circuit, and is characterized in that: the image sensor is respectively electrically connected with the driving circuit and the digital transmission circuit, and comprises a GL1608 chip internally provided with a 128 register;

the drive circuit comprises a detector peripheral circuit and a time sequence circuit, and the detector peripheral circuit is electrically connected with the time sequence circuit;

the data transmission circuit comprises a data cache circuit with a large capacity cache, a digital image processing circuit and a high-speed signal transmission circuit, wherein the digital image processing circuit is electrically connected with the data cache circuit and the high-speed signal transmission circuit respectively.

2. The imaging circuit of claim 1, wherein: the sequential circuit includes:

integral control circuit for performing logical calculation on user input information, and

a frame frequency control circuit and a register configuration circuit for controlling the scanning line frequency of the detector; the integral control circuit and the frame frequency control circuit are both electrically connected with the register configuration circuit.

3. A high speed long line column CMOS detector imaging circuit according to claim 2, wherein: the register configuration circuit includes:

a counter;

the serial-parallel conversion circuit is electrically connected to the counter;

a data alignment circuit electrically connected to the serial-to-parallel conversion circuit, an

A trigger pulse generating circuit for controlling the holding or counting of the counter and a latch for storing an external signal in an internal register; the data alignment circuit is electrically connected with the trigger pulse generating circuit, and the trigger pulse generating circuit is electrically connected with the latch.

4. A high speed long line column CMOS detector imaging circuit according to claim 1, wherein: the detector peripheral circuit includes: the circuit comprises a power supply circuit, a bias circuit and an external digital interface circuit; the power circuit is electrically connected with the image sensor and the bias circuit respectively, the bias circuit is electrically connected with the external digital interface circuit, and the external digital interface circuit is electrically connected with the sequential circuit.

5. The high speed long line column CMOS detector imaging circuit of claim 4, wherein: the power supply circuit comprises a power supply chip;

the seven feet of the power chip are connected with CC2, CC1 is connected between one end of the CC2 and one foot of the power chip, RC2 is connected between the six feet and the eight feet of the power chip, RC1 is connected between the eight feet and the nine feet of the power chip, and CC3 is connected between the eleven feet and the nine feet of the power chip.

6. The imaging circuit of claim 1, wherein: the data cache circuit comprises a DDR3-SDRAM chip, and the DDR3-SDRAM chip comprises four memories of 512MB and 32bit wide.

7. A high speed long line column CMOS detector imaging circuit according to claim 1, wherein: the digital image processing circuit includes:

and the image processor is respectively connected with the image sensor and the DDR3-SDRAM chip.

8. A high speed long line column CMOS detector imaging circuit according to claim 1, wherein: the high-speed signal transmission circuit includes: the system comprises an Ethernet transmitter and an upper computer; the Ethernet transmitter is electrically connected with an upper computer, and the upper computer is connected with the data processor through an RS232 interface.

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