CN105897272A - Successive approximation register analog-to-digital converter and control method thereof - Google Patents
Successive approximation register analog-to-digital converter and control method thereof Download PDFInfo
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- CN105897272A CN105897272A CN201610193030.8A CN201610193030A CN105897272A CN 105897272 A CN105897272 A CN 105897272A CN 201610193030 A CN201610193030 A CN 201610193030A CN 105897272 A CN105897272 A CN 105897272A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention provides a successive approximation register analog-to-digital converter (SAR-ADC) and a control method thereof. The SAR-ADC comprises two capacitor arrays, two groups of switches, a reference voltage buffer, and a comparator. Each group of switches includes a sampling switch array, a reference voltage array, and a ground switch array. The top electrode board of each capacitor array is connected with one input end of the comparator. The bottom electrode board of each capacitor array is connected with one sampling switch array. The two input ends of the comparator are selectively connected with the reference voltage buffer. The two ground switch arrays are both connected to ground. The two reference voltage arrays are both connected with the reference voltage buffer. The SAR-ADC enables the capacitor arrays connected with the input ends of the comparator to be insensitive to parasitic capacitance and charge injection by using a bottom electrode board sampling way, thereby increasing result precision. The SAR-ADC just employs one reference voltage buffer so as to be increased in power consumption and area.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly to a kind of successive approximation analog-digital converter
And control method.
Background technology
Trend in IC design in recent years, for more low-power consumption, higher performance and less one-tenth
Originally there is the most harsh requirement, and in the middle of the design of analog front circuit, an efficient simulation number
Word transducer (analog-to-digital converter is called for short ADC) can make system general performance be greatly improved,
ADC is responsible for being converted to the analogue signal of reception digital signal, and is supplied to the Digital Signal Processing list of rear end
Unit operates, therefore its dynamic range, resolution, degree of accuracy, the linearity, sample rate, power consumption, defeated
Enter level characteristics etc., all become the important step affecting system general performance, also become assessment transducer itself
The important parameter of performance.
The framework of existing ADC is of a great variety, such as pipe line analog-digital converter (pipeline analog-
To-digital converter, is called for short pipeline ADC) and successive approximation analog-digital converter (successiv
E approximation register analog-to-digital converter, be called for short SAR-ADC) etc. be all existing
Framework conventional in technical field.Wherein, under same specification demands, SAR-ADC is compared to pipeli
Ne ADC can have lower power consumption and the advantage of less chip area, the most therefore, for SAR-ADC frame
The technological development of structure, is the most gradually paid attention to by industry.
Under the framework of existing SAR-ADC, it typically can include digital analog converter (digital-to-
Analog converter, is called for short DAC), the part such as comparator and SAR logic control circuit.Concrete and
Speech, in the Analog-digital Converter operating process of tradition SAR-ADC, DAC typically can be first with a reference
Analog input signal is sampled keeping (sample-and-hold), the thereafter control of SAR logic by voltage as benchmark
Circuit processed can control the digital simulation of DAC with binary search algorithm (binary search algorithm) and turn
Changing, to make DAC produce corresponding comparison signal, wherein said comparison signal is associated with corresponding Different Logic shape
The analog voltage of state and the voltage difference of analog input signal.Then, comparator can be made with described reference voltage
On the basis of compare with described comparison signal, thus make SAR logic control circuit ratio based on comparator
Relatively result and determine each logic state of digital output signal one by one.
At present, SAR ADC is designed primarily to reversely merge switch (Inverted merged capacitor swi
Tching, IMCS) and dull switch (Monotonic switching, MS) both structures.Refer to
Fig. 1, it is the structural representation of SAR ADC of 10 of IMCS structure, as shown in Figure 1, IMCS
The SAR ADC of structure uses bottom crown Sampling techniques, thus it to DAC outfan to parasitic capacitance and defeated
The electric charge entering sampling switch injects insensitive；Refer to Fig. 2, it is the SAR AD of 10 of MS structure
The structural representation of C, as shown in Figure 2, MS structure is to use top crown Sampling techniques, so it is to DA
The electric charge of the parasitic capacitance of C outfan and input sample switch injects extremely sensitive.Secondly, IMCS structure needs
Want Voltage Reference Buffer (Vrefp buffer) and two, common mode reference voltage buffer (VCM buffer)
Voltage buffer and two groups of switches, often group switch includes a sampling switch array, the ginseng being sequentially connected with
Examine voltage switch array, common mode reference voltage switch arrays and switch arrays over the ground, described switch over the ground
Array ground, described reference voltage switch arrays are connected with described Voltage Reference Buffer, described common-mode reference
Voltage switch array is connected with described common mode reference voltage buffer；And MS structure has only to one with reference to electricity
Compression buffer and two groups of switches, often group switch includes a sampling switch array, the reference being sequentially connected with
Voltage switch array and one switch arrays over the ground, described switch arrays ground connection over the ground, described reference voltage switchs
Array is connected with described Voltage Reference Buffer, and IMCS structure is more complicated than MS structure and power consumption is high.Therefore,
SAR ADC to expect that high precision, IMCS structure are first-selected, and power consumption to be reduced and complexity, then
MS structure to be selected.
For the problems referred to above, those skilled in the art always search for and design can meeting high accuracy with low simultaneously
The SAR ADC of power consumption demand.
Summary of the invention
It is an object of the invention to provide a kind of successive approximation analog-digital converter, with solve existing progressively
The problem that the structure of approximant analog-digital converter cannot meet high accuracy and low-power consumption simultaneously.
For solving above-mentioned technical problem, the present invention provides a kind of successive approximation analog-digital converter, described
Successive approximation analog-digital converter includes:
Two capacitor arrays, two groups of switches, a Voltage Reference Buffer and a comparator, often group is opened
Close sampling switch array, reference voltage switch arrays and the switch arrays over the ground including being sequentially connected with, wherein,
The top crown of each capacitor array is connected with an input of described comparator, the lower pole of each capacitor array
Plate and one group of sampling switch array connect, and two input selectivitys of described comparator are electric with described reference
Compression buffer connects, two groups of equal ground connection of switch arrays over the ground, two groups of reference voltage switch arrays all with described ginseng
Examine voltage buffer to connect.
Optionally, in described successive approximation analog-digital converter, the bottom crown of each capacitor array
When being connected with one group of sampling switch array, the bottom crown of each electric capacity in described capacitor array and described sampling
A sampling switch in switch arrays connects, and the sampling that in described capacitor array, each electric capacity is connected is opened
Close difference.
Optionally, in described successive approximation analog-digital converter, described capacitor array is stagewise
Binary weights capacitor array.
Optionally, in described successive approximation analog-digital converter, also include a SAR logic control
Circuit, described SAR logic control circuit is connected with the outfan of described comparator.
Optionally, in described successive approximation analog-digital converter, one of them capacitor array upper
Pole plate is connected with the positive input terminal of described comparator, the top crown of another capacitor array and described comparator
Negative input end connects.
The present invention also provides for the control method of a kind of successive approximation analog-digital converter, described Step wise approximation
The control method of formula analog-digital converter includes:
Sample phase, connects Voltage Reference Buffer, a capacitor array by the top crown of two capacitor arrays
Bottom crown access input signal, the bottom crown of another capacitor array accesses another input signal, with to two
Individual input signal is sampled；And
In the Approach by inchmeal stage, the top crown of two capacitor arrays is disconnected with Voltage Reference Buffer, and makes electricity
The bottom crown holding array connects Voltage Reference Buffer, so that the electric charge of two inputs of described comparator is again
Distribution, completes Approach by inchmeal process according to the output result of described comparator.
Optionally, in the control method of described successive approximation analog-digital converter, if described comparison
Device is output as height, then the electric capacity in precalculated position in the capacitor array that the positive input terminal with described comparator is connected
Bottom crown still connect Voltage Reference Buffer, in the capacitor array being connected with the negative input end of described comparator
The bottom crown ground connection of the electric capacity of same position；
If described comparator is output as low, then in the capacitor array that the negative input end with described comparator is connected
Voltage Reference Buffer still connected by the bottom crown of the electric capacity in precalculated position, connects with the positive input terminal of described comparator
The bottom crown ground connection of the electric capacity of same position in the capacitor array connect.
Optionally, in the control method of described successive approximation analog-digital converter, described progressively force
Nearly formula analog-digital converter also includes a SAR logic control circuit, is connected with the outfan of described comparator,
Utilize SAR logic control circuit output based on comparator result and determine one by one digital output signal each
Logic state.
Optionally, in the control method of described successive approximation analog-digital converter, described electric capacity battle array
It is classified as stagewise binary weights capacitor array.
Optionally, in the control method of described successive approximation analog-digital converter, each electric capacity battle array
Row bottom crown with one group switch connection time, the bottom crown of each electric capacity in described capacitor array with currently open
A sampling switch in the sampling switch array of pass group connects, and in described capacitor array, each electric capacity is connected
The sampling switch connect is different.
In successive approximation analog-digital converter provided by the present invention and control method thereof, described progressively
Approximant analog-digital converter include two capacitor arrays, two groups of switches, Voltage Reference Buffer with
And a comparator, often group switch includes sampling switch array, reference voltage switch arrays and switch arrays over the ground
Row, the top crown of each capacitor array is connected with comparator input, the lower pole of each capacitor array
Plate and one group of sampling switch array connect, and two input selectivitys of comparator and Voltage Reference Buffer
Connecting, two groups of equal ground connection of switch arrays over the ground, two groups of reference voltage switch arrays are all and Voltage Reference Buffer
Connect.The successive approximation analog-digital converter of the present invention uses bottom crown sample mode so that with compare
Capacitor array degree parasitic capacitance and electric charge that the input of device connects inject insensitive, improve the precision of result；
Only with a Voltage Reference Buffer in structure, reduce power consumption and the area of finished product.
Accompanying drawing explanation
Fig. 1 is the structural representation of the SAR ADC of 10 of IMCS structure；
Fig. 2 is the structural representation of the SAR ADC of 10 of MS structure；
Fig. 3 is the structural representation of the successive approximation analog-digital converter of 10 of one embodiment of the invention
Figure；
Fig. 4 is the flow chart of the control method of the successive approximation analog-digital converter of one embodiment of the invention；
Fig. 5 is that the switch switching of the successive approximation analog-digital converter of 3 of one embodiment of the invention is suitable
Sequence accompanying drawings.
In Fig. 3:
Capacitor array 10a, 10b；Voltage Reference Buffer 11；Comparator 12；Sampling switch array 13a,
13b；Reference voltage switch arrays 14a, 14b；Switch arrays 15a, 15b over the ground；SAR logic control electricity
Road 16.
Detailed description of the invention
The successive approximation analog-digital converter that the present invention proposed below in conjunction with the drawings and specific embodiments and
Its control method is described in further detail.According to following explanation and claims, advantages of the present invention and
Feature will be apparent from.It should be noted that, accompanying drawing all use the form simplified very much and all use non-accurately than
Example, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.
As the detailed description of the invention of the present invention, nonrestrictive enumerate, simulate with the successive approximations of 10
As a example by digital converter (SAR-ADC), the concrete structure to successive approximation analog-digital converter is carried out in detail
Illustrate.The structural representation of the successive approximation analog-digital converter of provide for the present embodiment 10 of Fig. 3.
As it is shown on figure 3, described successive approximation analog-digital converter includes: two capacitor arrays, two groups of switches,
One Voltage Reference Buffer 11 and a comparator 12.
Said two capacitor array is respectively capacitor array 10a and capacitor array 10b.Capacitor array 10a's is upper
Pole plate is connected, capacitor array with an input (for positive input terminal in the present embodiment) of described comparator 12
The top crown of 10b is connected with another input (for negative input end in the present embodiment) of described comparator 12,
And two input selectivitys of described comparator 12 are connected with described Voltage Reference Buffer 11.Described two
The bottom crown of individual capacitor array 10a, 10b is each connected with one group of switch.
Sampling switch array that often group switch includes being sequentially connected with, reference voltage switch arrays and switch arrays over the ground
Row.Wherein, one group of sampling switch array accesses input signal Vip, and another group sampling switch array accesses input
Signal Vin；Two groups of equal ground connection of switch arrays over the ground；Two groups of reference voltage switch arrays delay with same reference voltage
Rush device 11 to connect to access a reference voltage buffering signals Vrefp.
Detailed, is connected with capacitor array 10a one group switch include being sequentially connected with sampling switch array 13a,
Reference voltage switch arrays 14a and over the ground switch arrays 15a, the described 15a ground connection of switch arrays over the ground is described
Reference voltage switch arrays 14a is connected with described Voltage Reference Buffer 11；It is connected with capacitor array 10b
One group of switch includes the sampling switch array 13b being sequentially connected with, reference voltage switch arrays 14b and switchs over the ground
Array 15b, the described 15b ground connection of switch arrays over the ground, described reference voltage switch arrays 14b and described reference
Voltage buffer 11 connects.
As it has been described above, the successive approximation analog-digital converter of the present embodiment uses bottom crown sample mode i.e.
Sampled by the bottom crown of electric capacity in capacitor array, the electric capacity that therefore input with comparator 12 is connected
Parasitic capacitance and electric charge are injected insensitive by array, meanwhile, and the successive approximation simulation number of the present embodiment
Word transducer has only been used a Voltage Reference Buffer 11, thus needed for reducing power consumption and reducing finished product
Area.Additionally, often group switch includes that 3 kinds of switch arrays, relative IMCS structure often organize in switch few one
Planting switch arrays, structure is relatively easy.
Please continue to refer to Fig. 3, the bottom crown of each electric capacity in two groups of capacitor arrays 10a, 10b each connects
A sampling switch in sampling switch array, i.e. bottom crown one sampling switch of connection of an electric capacity, two
Person is relation one to one.In the present embodiment, described capacitor array is stagewise binary weights electric capacity battle array
Row, use stagewise binary weights capacitor array to compare the capacitive junctions using pure binary weight capacitor array
For structure, the matching performance of capacitor array domain is more preferable, and reason is stagewise binary capacitor weight array
There are two each Self Matching of capacitor array, and weight position span is less, be beneficial to do on domain mate；And it is pure
Binary weights capacitor array minimum capacity is too big to maximum capacitor value span, is therefore unfavorable for doing on domain
Coupling.
Further, described successive approximation analog-digital converter also includes a SAR logic control circuit 16,
It is connected with the outfan of described comparator 12, such that it is able to comparative result based on comparator 12 and one by one
Determine each logic state of digital output signal.Wherein, the outfan of SAR logic control circuit 16
EOC refers to the enable signal after every time the converting of SARADC transducer, D9～D0 is SARADC
10 Bit data output signals.
Additionally, described successive approximation analog-digital converter also includes a clock signal generator, at clock
Under the effect of clk, produce sampled clock signal sampclk and sampclka.
The present embodiment additionally provides the control method of a kind of successive approximation analog-digital converter.Such as Fig. 3 and
Shown in Fig. 4, the control method of the successive approximation analog-digital converter of the present embodiment includes:
Sample phase, makes the top crown of described capacitor array 10a, 10b connect Voltage Reference Buffer 11, electricity
The bottom crown holding array 10a accesses input signal Vip, and the bottom crown of capacitor array 10b accesses input signal
Vin, to sample to described input signal Vip, Vin；And
In the Approach by inchmeal stage, the top crown of capacitor array 10a, 10b is disconnected with Voltage Reference Buffer 11,
And make the bottom crown of capacitor array 10a, 10b connect Voltage Reference Buffer 11, so that described comparator 12
The electric charge of two inputs redistribute, complete Approach by inchmeal process according to the output result of described comparator 12.
Wherein, if described comparator 12 is output as height, then the positive input terminal with described comparator 12 is connected
Capacitor array 10a in the bottom crown of electric capacity in precalculated position still connect Voltage Reference Buffer 11, with described
The bottom crown ground connection of the electric capacity of same position in the capacitor array 10b that the negative input end of comparator 12 connects；If
Described comparator 12 is output as low, then the electric capacity battle array that the negative input end 10b with described comparator 12 is connected
In row, Voltage Reference Buffer 11 still connected by the bottom crown of the electric capacity in precalculated position, with described comparator 12 just
The bottom crown ground connection of the electric capacity of same position in the capacitor array 10a that input connects.
Further, refer to Fig. 3, utilize SAR logic control circuit 16 output based on comparator result
And determine each logic state (i.e. 0 or 1) of digital output signal one by one, the present embodiment represents with 1
The output voltage of comparator is high potential, represents that the output voltage of comparator is as electronegative potential with 0.
In order to be better understood from the control method of successive approximation analog-digital converter of the present invention, below in conjunction with
The sequence of switches accompanying drawings of the successive approximation analog-digital converter of 3 shown in Fig. 5 is carried out
Describe in detail.
As it is shown in figure 5, in sample phase, input signal Vip, Vin connect under capacitor array 10a, 10b
Pole plate, Voltage Reference Buffer (Vrefp buffer) 11 connects the top crown of two capacitor arrays 10a, 10b,
Input signal Vip, Vin are sampled；
In the Approach by inchmeal stage, first cycle, Voltage Reference Buffer 11 from two capacitor array 10a,
The top crown of 10b disconnects, and the bottom crown of two capacitor arrays 10a, 10b connects Voltage Reference Buffer 11 (i.e.
In capacitor array, the bottom crown of all of electric capacity is all connected with Voltage Reference Buffer 11), two of comparator 12
Input electric charge is redistributed.In the present embodiment, if the magnitude of voltage of input signal Vip is more than input signal
The magnitude of voltage of Vin, the output voltage of comparator 12 is high potential, if the magnitude of voltage of input signal Vip is little
In the magnitude of voltage of input signal Vin, then the output voltage of comparator 12 is electronegative potential；Second period, as
The output voltage really going up a cycle comparator 12 is high, then the positive input terminal with described comparator 12 is connected
Capacitor array 10a in the bottom crown of the electric capacity that electric capacity is 2C still connect Voltage Reference Buffer, with described
In the capacitor array 10b that the negative input end of comparator 12 connects under the electric capacity that electric capacity is 2C of same position
Pole plate ground connection；If the output voltage of upper cycle comparator 12 is electronegative potential, then with described comparator 12
The bottom crown of the electric capacity that electric capacity is 2C in the capacitor array 10b that negative input end connects still is connected reference voltage and is delayed
Rushing device 11, in the capacitor array 10a being connected with the positive input terminal of described comparator 12, the electric capacity of same position is
The bottom crown ground connection of the electric capacity of 2C；By that analogy, be fully completed until comparing, i.e. SAR ADC mono-is complete
The whole change-over period completes.
Table 1 is the SAR ADC of the present embodiment and the SAR ADC of IMCS structure and the SAR of MS structure
The comparison of ADC, specific as follows:
Table 1
From table 1 relative analysis, the SARADC of the present invention can overcome in conjunction with the advantage of both structures
The shortcoming that IMCS structure and MS structure exist, meets the demand of high accuracy and low-power consumption simultaneously.
To sum up, in successive approximation analog-digital converter provided by the present invention and control method thereof, described
Successive approximation analog-digital converter includes two capacitor arrays, two groups of switches, reference voltage bufferings
Device and a comparator, often group switch includes sampling switch array, reference voltage switch arrays and opens over the ground
Closing array, the top crown of each capacitor array is connected with comparator input, each capacitor array
Bottom crown and one group of sampling switch array connect, and two input selectivitys of comparator delay with reference voltage
Rushing device to connect, two groups of equal ground connection of switch arrays over the ground, two groups of reference voltage switch arrays are all slow with reference voltage
Rush device to connect.The successive approximation analog-digital converter of the present invention uses bottom crown sample mode so that with
Capacitor array degree parasitic capacitance and electric charge that the input of comparator connects inject insensitive, improve result
Precision；Only with a Voltage Reference Buffer in structure, reduce power consumption and the area of finished product.As can be seen here,
The successive approximation analog-digital converter of the present invention can meet for high accuracy and the need of low-power consumption simultaneously
Ask.
In this specification, each embodiment uses the mode gone forward one by one to describe, and what each embodiment stressed is
With the difference of other embodiments, between each embodiment, identical similar portion sees mutually.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention,
Any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, belong to power
The protection domain of profit claim.
Claims (10)
1. a successive approximation analog-digital converter, it is characterised in that including: two capacitor arrays,
Two groups of switches, a Voltage Reference Buffer and a comparator, often group switch includes that be sequentially connected with adopts
Sample switch arrays, reference voltage switch arrays and switch arrays over the ground, wherein, the upper pole of each capacitor array
Plate is connected with an input of described comparator, the bottom crown of each capacitor array and one group of sampling switch battle array
Row connect, and two input selectivitys of described comparator are connected with described Voltage Reference Buffer, two groups
The equal ground connection of switch arrays over the ground, two groups of reference voltage switch arrays are all connected with described Voltage Reference Buffer.
2. successive approximation analog-digital converter as claimed in claim 1, it is characterised in that Mei Ge electricity
When the bottom crown of appearance array and one group of sampling switch array connect, under each electric capacity in described capacitor array
Pole plate is connected with a sampling switch in described sampling switch array, and each electric capacity in described capacitor array
The sampling switch connected is different.
3. successive approximation analog-digital converter as claimed in claim 1, it is characterised in that described electricity
Holding array is stagewise binary weights capacitor array.
4. successive approximation analog-digital converter as claimed in claim 1, it is characterised in that also include
One SAR logic control circuit, described SAR logic control circuit is connected with the outfan of described comparator.
5. successive approximation analog-digital converter as claimed in claim 1, it is characterised in that Qi Zhongyi
The top crown of individual capacitor array is connected with the positive input terminal of described comparator, the top crown of another capacitor array
It is connected with the negative input end of described comparator.
6. a control method for successive approximation analog-digital converter as claimed in claim 1, its feature
It is, including:
Sample phase, connects Voltage Reference Buffer, a capacitor array by the top crown of two capacitor arrays
Bottom crown access input signal, the bottom crown of another capacitor array accesses another input signal, with to two
Individual input signal is sampled；And
In the Approach by inchmeal stage, the top crown of two capacitor arrays is disconnected with Voltage Reference Buffer, and makes electricity
The bottom crown holding array connects Voltage Reference Buffer, so that the electric charge of two inputs of described comparator is again
Distribution, completes Approach by inchmeal process according to the output result of described comparator.
7. the control method of successive approximation analog-digital converter as claimed in claim 6, its feature exists
In, if described comparator is output as height, then in the capacitor array that the positive input terminal with described comparator is connected
Voltage Reference Buffer still connected by the bottom crown of the electric capacity in precalculated position, connects with the negative input end of described comparator
The bottom crown ground connection of the electric capacity of same position in the capacitor array connect；
If described comparator is output as low, then in the capacitor array that the negative input end with described comparator is connected
Voltage Reference Buffer still connected by the bottom crown of the electric capacity in precalculated position, connects with the positive input terminal of described comparator
The bottom crown ground connection of the electric capacity of same position in the capacitor array connect.
8. the control method of successive approximation analog-digital converter as claimed in claim 6, its feature exists
In, described successive approximation analog-digital converter also includes a SAR logic control circuit, compares with described
The outfan of device connects, and utilizes SAR logic control circuit output based on comparator result to determine number one by one
Each logic state of word output signal.
9. the control method of successive approximation analog-digital converter as claimed in claim 6, its feature exists
In, described capacitor array is stagewise binary weights capacitor array.
10. the control method of successive approximation analog-digital converter as claimed in claim 6, its feature
It is, when the bottom crown of each capacitor array and one group of switch connect, each electric capacity in described capacitor array
Bottom crown be connected with a sampling switch in the sampling switch array of current switch group, and described electric capacity battle array
The sampling switch that in row, each electric capacity is connected is different.
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| CN107786206A (en) * | 2017-11-29 | 2018-03-09 | 四川知微传感技术有限公司 | Pipeline SAR-ADC system |
| CN109768800A (en) * | 2018-11-27 | 2019-05-17 | 西安电子科技大学 | A kind of super low-power consumption gradual approaching A/D converter based on Charge scaling |
| US10447291B1 (en) | 2018-09-14 | 2019-10-15 | Linear Technology Holding, LLC | High dynamic range analog-to-digital converter |
| CN110768670A (en) * | 2019-09-26 | 2020-02-07 | 西安交通大学 | Digital piecewise linear calibration method for successive approximation type analog-to-digital converter |
| WO2020103637A1 (en) * | 2018-11-23 | 2020-05-28 | 深圳锐越微技术有限公司 | Reference voltage control circuit, and analog-to-digital converter |
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| CN111786677A (en) * | 2019-04-03 | 2020-10-16 | 扬智科技股份有限公司 | Successive approximation analog-to-digital converter |
| WO2020244227A1 (en) * | 2019-06-05 | 2020-12-10 | 中国电子科技集团公司第二十四研究所 | Single-channel time-interleaved sampling-based sar adc and sampling method |
| CN112118009A (en) * | 2019-06-21 | 2020-12-22 | 瑞昱半导体股份有限公司 | Successive approximation analog-to-digital converter and operation method thereof |
| CN112968704A (en) * | 2021-02-03 | 2021-06-15 | 电子科技大学 | Successive approximation type analog-to-digital converter based on transient capacitance switching mode and quantization method thereof |
| CN113839673A (en) * | 2021-09-14 | 2021-12-24 | 无锡英迪芯微电子科技股份有限公司 | Novel digital domain self-calibration successive approximation analog-to-digital converter |
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