CN108988859B - Comparator offset voltage calibration method based on redundant bits - Google Patents
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Abstract
A comparator offset voltage calibration method based on redundant bits belongs to the technical field of analog integrated circuits. According to the SAR ADC based on the DAC capacitor array and comprising the redundant bit capacitor, firstly, the DAC capacitor array is used for sampling and quantizing 0 to obtain a first quantized code word, then the quantized capacitor in the DAC capacitor array is used for sampling and quantizing the input voltage to obtain a second quantized code word, the difference value of the first quantized code word and the ideal quantized code word is subtracted from the second quantized code word, the output quantized code word of the SAR ADC after the offset voltage of the calibration comparator is obtained, and finally the digit of the output quantized code word is converted into the correct digit to finish calibration. The SAR ADC calibration method has the characteristics of high flexibility, large calibratable offset voltage range and capability of completely ensuring the quantization range of the SAR ADC.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a comparator offset voltage calibration method based on redundant bits, which is used for calibrating comparator offset voltage in output quantization code words obtained by a successive approximation type analog-to-digital converter (SAR ADC for short).
Background
Compared with an analog circuit, the digital circuit has the characteristics of strong anti-interference capability, high reliability, high integration level and the like. The application of digital circuits in the field of signal processing is extremely wide. Digital circuits process digital signals, and most of the signals in nature are analog signals, and a module for converting the analog signals into the digital signals is called an analog-to-digital converter (ADC). Common ADCs are classified into flash ADCs, pipeline ADCs, sigma-delta ADCs, and Successive Approximation (SAR) ADCs, and a user may select an appropriate ADC according to speed and accuracy requirements.
The comparator is one of the most critical modules in various types of ADCs, and the higher speed and precision requirements of the ADCs bring great challenges to the design of the comparator. Due to process mismatch, the comparator has an inherent offset voltage, which can even reach tens of millivolts, seriously affecting the input range of the comparator. Input Offset Storage (IOS) and Output Offset Storage (OOS) of the comparator are two commonly used comparator Offset cancellation techniques. Both introduce a preamplifier and switching logic, which limits the speed of the comparator, increasing design complexity, even because of the extra offset error introduced by the channel charge injection of the switch. The successive approximation analog-to-digital converter (SAR ADC) has a relatively complex switching sequential logic, so if the input offset storage or the output offset storage is used in the SAR ADC to eliminate the offset voltage, the complexity of the sequential logic is further increased, and the design difficulty is increased.
The quantization process of the conventional SAR ADC is based on a binary search algorithm, and there is no overlapping interval in the same search range during the execution of the algorithm, i.e. once a range is excluded during the search process, the range is removed from the search range and is not considered any more. Thus, for each analog input voltage, there is a unique digital code, with one-to-one correspondence between the analog input and digital output of the ADC. This algorithm is not tolerant to switching errors and once an error occurs during the switching of a bit, it is not able to recover and produce the correct output codeword. To solve this problem, a redundant bit technique may be introduced, using a low binary (sub-radix-2) search algorithm. The low binary search algorithm has overlapped intervals in the same search range, the same analog input can correspond to a plurality of digital code outputs, and certain fault-tolerant capability is achieved. For an N-bit SAR ADC, the low binary search algorithm requires more than N conversion processes, and the number of bits of the obtained digital code will also be greater than N.
Disclosure of Invention
Aiming at the problems of limiting the speed of a comparator, increasing the design complexity and introducing extra offset errors in the traditional comparator offset elimination technology, the invention provides a method for calibrating the offset voltage of the comparator in the SAR ADC by utilizing the redundant bit technology based on the SAR ADC with a DAC capacitor array comprising the redundant bit capacitor, and the method has the characteristics of high flexibility, large correctable offset voltage range and capability of completely ensuring the quantization range of the SAR ADC.
The technical scheme of the invention is as follows:
the comparator offset voltage calibration method based on the redundant bits is used for calibrating comparator offset voltage in output quantization code words obtained by a successive approximation analog-to-digital converter, a DAC capacitor array of the successive approximation analog-to-digital converter comprises redundant capacitors and quantization capacitors, each redundant capacitor and each quantization capacitor in the DAC capacitor array are divided into two capacitors with equal capacitance values to form a first split capacitor array and a second split capacitor array, the first split capacitor array comprises each redundant capacitor in the DAC capacitor array and one capacitor after each quantization capacitor is split, and the second split capacitor array comprises each redundant capacitor in the DAC capacitor array and the other capacitor after each quantization capacitor is split;
the offset voltage calibration method of the comparator comprises the following steps:
connecting all capacitor upper electrode plates in the first split capacitor array and the second split capacitor array with a common-mode voltage, and sampling 0 by using all capacitor lower electrode plates in the first split capacitor array and the second split capacitor array;
step two, disconnecting the connection between the upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array and the common-mode voltage, and quantizing the sampling voltage obtained in the step one by the successive approximation analog-to-digital converter to generate a first quantized code word;
connecting common-mode voltage to upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array, connecting lower electrode plates of all capacitors after the split of all quantized capacitors in the first split capacitor array and the second split capacitor array to input voltage, connecting lower electrode plates of all capacitors after the split of all redundant capacitors in the first split capacitor array to positive reference voltage, and connecting lower electrode plates of all capacitors after the split of all redundant capacitors in the second split capacitor array to negative reference voltage;
step four, disconnecting the upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array from the common-mode voltage, and quantizing the sampling voltage obtained in the step three by the successive approximation analog-to-digital converter to generate a second quantized codeword;
step five, after the offset voltage of the comparator is calibrated, the output quantized code word of the successive approximation analog-to-digital converter is the second quantized code word- (the first quantized code word-the ideal quantized code word), and the ideal quantized code word is the quantized code word obtained by quantizing 0 under the ideal condition that the comparator has no offset voltage;
and step six, converting the output quantization code word of the successive approximation analog-to-digital converter obtained in the step five into a binary code with the corresponding bit of the redundancy capacitor subtracted.
Specifically, the successive approximation analog-to-digital converter is single-ended sampling, one input end of the comparator is connected with the DAC capacitor array, and the first step of sampling 0 by using all capacitor bottom plates in the first split capacitor array and the second split capacitor array comprises the following specific steps: and connecting all capacitor lower electrode plates in the first split capacitor array and the second split capacitor array with a ground voltage.
Specifically, the successive approximation analog-to-digital converter is double-end sampling, two input ends of the comparator are respectively connected with one DAC capacitor array, and the first step of sampling 0 by using all capacitor bottom plates in the first split capacitor array and the second split capacitor array comprises the following specific steps: and connecting all the lower capacitor plates in the first split capacitor array with positive reference voltage, and connecting all the lower capacitor plates in the second split capacitor array with negative reference voltage.
The invention has the beneficial effects that: the comparator offset voltage calibration method based on the redundant bit is suitable for the SAR ADC with the DAC capacitor array comprising the redundant bit capacitor, and has the characteristics of high flexibility, large correctable offset voltage range and capability of completely ensuring the quantization range of the SAR ADC.
Drawings
Fig. 1 is a schematic structural diagram of a DAC capacitor array in a successive approximation analog-to-digital converter to which the comparator offset voltage calibration method based on redundant bits according to the present invention is applied.
Fig. 2 is a schematic diagram of potentials of all capacitor plates in a DAC capacitor array during an offset voltage test phase according to the comparator offset voltage calibration method based on the redundancy bit, where fig. 2(a) is a schematic diagram of the plate potentials of the DAC capacitor array sampled at 0, and fig. 2(b) is a schematic diagram of the plate potentials of the comparator before comparison after sampling is completed.
Fig. 3 is a schematic diagram of potentials of all capacitor plates in a DAC capacitor array during a normal working phase of the comparator offset voltage calibration method based on the redundancy bit, where fig. 3(a) is a schematic diagram of the plate potentials of the DAC capacitor array sampling an input voltage, and fig. 3(b) is a schematic diagram of the plate potentials of the comparator before the comparator starts to compare after the sampling is completed.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
The offset voltage calibration method of the comparator based on the redundant bit is suitable for a successive approximation analog-to-digital converter (SAR ADC) with a DAC capacitor array containing the redundant bit capacitor, as shown in FIG. 1, a structure of the DAC capacitor array in the SAR ADC is given, in the embodiment, the SAR ADC with a 12-bit division structure with one redundant bit is taken as an example, the SAR ADC comprises a first DAC capacitor array and a second DAC capacitor array which are respectively connected with the positive input end and the negative input end of the comparator, the first DAC capacitor array and the second DAC capacitor array respectively comprise 12-bit quantization capacitors and 1-bit redundancy capacitors, each bit capacitor is classified into two capacitors with equal capacitance values which are respectively used for forming a first split capacitor array and a second split capacitor array, the first split capacitor array in the first DAC capacitor array comprises 12 CPAs (capacitor with post-split weights of 0.5, 1, 2, … … 1024 and one redundant capacitor after split, the weight is 64; the structures of the second split capacitor array CPB in the first DAC capacitor array, the first split capacitor array CNA in the second DAC capacitor array and the second split capacitor array CNB in the second DAC capacitor array are the same as the structure of the first split capacitor array CPA in the first DAC capacitor array.
The SAR ADC is a linear system based on which the offset voltage of the comparator can be eliminated by a simple subtraction operation. For a traditional N-bit ideal SAR ADC, assuming that the quantization range is Vmin-Vmax, when the input voltage is Vmin and Vmax respectively, the output code words are 0 and 2^ N-1 respectively. If the SAR ADC has an offset voltage Vos with a positive value, the output code word reaches the maximum code word 2^ N-1 when the input voltage is Vmax-Vos, and at the moment, even if the offset voltage is eliminated through subtraction operation, the input voltage of Vmax-Vos-Vmax sections cannot be restored, so that the input range of the SAR ADC is reduced.
As can be seen from the above analysis of the reason why the input voltage cannot be restored, the output of the SAR ADC already reaches the maximum code word that can be represented when the input does not reach the maximum Vmax due to the offset voltage, and the introduction of the redundant bit can solve this problem. For the DAC capacitor array of the twelve-bit SAR ADC with one-bit redundancy bit in the embodiment shown in fig. 1, if the redundancy capacitor does not participate in sampling the input of the SAR ADC in the sampling stage, when the input voltages are Vmin and Vmax, respectively, the output codewords after quantization are 64 and 8127, respectively. The twelve-bit SAR ADC maximum allowable code word is 2^13-1 ═ 8191, so that a redundancy space with 64 code words is reserved for offset voltage, the size of a corresponding analog value is about 33mV, namely the allowable offset voltage range is-33 mV to 33mV, the offset voltage in the range can be calibrated and the input range of the ADC is ensured, therefore, in the invention, a redundancy capacitor is added into a DAC capacitor array to provide the redundancy code word space for the offset voltage, wherein the number of the redundancy capacitor and the position in the DAC capacitor array can be set according to the offset size of the SAR ADC, and the higher the weight of the redundancy capacitor is, the larger the offset can be calibrated.
The offset voltage calibration method of the comparator provided by the invention has three stages: firstly, in the offset voltage testing stage, the SAR ADC quantizes the input of 0 to obtain a first quantized codeword D0; in a normal working stage, quantizing any input voltage by the SAR ADC to obtain a second quantized code Dvi; and thirdly, an offset voltage calibration output stage.
The calibration method of the present invention is described in detail below with respect to the SAR ADC of the twelve-bit trellis with one-bit redundancy bits in fig. 1.
Fig. 2 is a schematic diagram of the potential variation of the upper and lower plates of the capacitor in the offset voltage testing stage, which includes a sampling phase (step one) in the offset voltage testing stage and a comparison phase (step two) in the offset voltage testing stage.
Firstly, because the SAR ADC is of a differential structure and comprises two DAC capacitor arrays, the upper pole plates of all capacitors in the two DAC capacitor arrays are connected with a common-mode voltage VCM, the lower pole plates of a first split capacitor array CPA and a CNA in the two DAC capacitor arrays are connected with a positive reference voltage VREFP, and the lower pole plates of a second split capacitor array CPB and a CNB in the two DAC capacitor arrays are connected with a negative reference voltage VREFN, so that 0 sampling is completed; as shown in fig. 2 (a).
If the SAR ADC is of a single-ended sampling structure and only one input end of the comparator is connected to the DAC capacitor array, the specific way of sampling 0 by the DAC capacitor array in the step one is as follows: and connecting the upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array with a common mode voltage, and connecting the lower electrode plates with a ground voltage.
And step two, disconnecting the upper electrode plates of all capacitors in the two DAC capacitor arrays from the common-mode voltage VCM, enabling the comparator to start comparison as shown in fig. 2(b), and performing successive approximation on the sampling voltage obtained by sampling 0 in the step one of quantizing the analog-to-digital converter, thereby generating a first quantized code word D0.
Fig. 3 is a schematic diagram of the potential change of the upper and lower electrode plates of the capacitor in the second stage of normal operation, which includes a sampling phase (step three) in the normal operation stage and a comparison phase (step four) in the normal operation stage.
Connecting common-mode voltage VCM to upper electrode plates of all capacitors in the two DAC capacitor arrays, connecting negative input voltage Vin to lower electrode plates of capacitors after splitting of all quantized capacitors in the first split capacitor array CPA and the second split capacitor array CPB in the DAC capacitor array connected with the positive input end of the comparator, connecting positive input voltage Vip to lower electrode plates of capacitors after splitting of all quantized capacitors in the first split capacitor array CNA and the second split capacitor array CNB in the DAC capacitor array connected with the negative input end of the comparator, connecting positive reference voltage VREFP to lower electrode plates of capacitors after splitting of all redundant capacitors in the first split capacitor array CPA and the CNA in the two DAC capacitor arrays, connecting negative reference voltage VERFN to lower electrode plates of capacitors after splitting of all redundant capacitors in the second split capacitor array CPB and the CNB in the two DAC capacitor arrays, as shown in FIG. 3(a), the sampling of the input voltage vi ═ Vip-Vin is completed in the process, as the negative input voltage Vin ═ VCM-vi/2, the positive input voltage Vip ═ VCM + vi/2, and 2VCM-Vip ═ Vin, the lower plate connection voltage is subtracted by 2VCM when the lower plate voltage is turned over to the upper plate, and the positive input voltage Vip is complementary to the negative input voltage Vin, and the positive input voltage Vip is recorded in the output of the DAC capacitor array at the positive input end of the comparator, so the DAC capacitor array connected to the positive input end of the comparator samples the negative input voltage Vin, and the DAC capacitor array connected to the negative input end of the comparator samples the positive input voltage Vip.
If the SAR ADC has a single-ended sampling structure and only one of the input terminals of the comparator is connected to the DAC capacitor array, the specific method for sampling the input voltage Vi by the DAC capacitor array in step three is as follows: connecting common-mode voltage to upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array, connecting input voltage vi to lower electrode plates of all capacitors after the quantization capacitors in the first split capacitor array and the second split capacitor array are split, connecting the lower electrode plates of all capacitors after the redundancy capacitors in the first split capacitor array are split to positive reference voltage, and connecting the lower electrode plates of all capacitors after the redundancy capacitors in the second split capacitor array to negative reference voltage.
And step four, disconnecting the upper electrode plates of all capacitors in the two DAC capacitor arrays from the common-mode voltage VCM, enabling the comparator to start comparison, and quantizing the sampling voltage of the input voltage Vin obtained in the step three by the successive approximation analog-to-digital converter to generate a second quantized code word Dvi, as shown in fig. 3 (b).
And the third stage is a calibration output stage, and the third stage comprises a fifth step.
Step five, after the offset voltage of the comparator is calibrated, the output quantized codeword Dvi _ cali of the successive approximation analog-to-digital converter is the second quantized codeword Dvi- (the first quantized codeword D0 — the ideal quantized codeword D0i), where the ideal quantized codeword D0i is a quantized codeword obtained by quantizing 0 under the ideal condition that the comparator has no offset voltage, and the ideal quantized codeword D0i is a fixed value for the DAC capacitor array of the determined structure. Assuming that the DAC capacitor array containing one redundancy bit Cr is CN, … … Ci, Cr, Ci-1, … … and C0, the ideal code words of the DAC capacitor array are 4, which satisfies the condition that the code word corresponding to CN in CN to Cr is opposite to the code word corresponding to other bits, the code word corresponding to Ci-1 in Ci-1 to C0 is opposite to the code word corresponding to other bits, and any one of the 4 ideal code words can be selected. Taking the DAC capacitor array in this embodiment as an example, the ideal codeword in this embodiment may be D0i ═ 1000001000000, [ 1000000111111 ], or [ 0111111000000 ], or [ 0111110111111 ].
Combining the first quantized codeword D0 obtained in the first step, an offset code Doffset reflecting the offset voltage of the comparator can be obtained as D0-D0 i. For the second quantized codeword Dvi, which is the quantized code of any input voltage obtained in the second stage, the calibrated codeword Dvi _ cali is Dvi-Doffset.
Since the twelve-bit SAR ADC has a redundant bit, there are thirteen output codes, Dvi _ cali is a digital code obtained after the offset voltage is removed, and the digital code is still a thirteen code word, whereas the final output of the SAR ADC in this embodiment should be a twelve-bit binary code word, so that the corrected thirteen code word needs to be converted into a twelve-bit binary code, and this process is completed by converting the output quantized code word Dvi _ cali obtained in the fifth step into a binary code obtained by subtracting the corresponding bit of the redundant capacitor through the sixth step. The conversion can be performed by checking the codeword of the redundant bit, when the redundant bit is 1, the codeword is added with [ 1000000 ] after the redundant bit is removed, and when the redundant bit is 0, the codeword is subtracted with [ 1000000 ] after the redundant bit is removed, and the operation result is the final SAR ADC output codeword of this embodiment. The SAR ADC can also be converted using the above method if it has two or more redundant bits.
It will be understood by those skilled in the art that various modifications and combinations of modifications may be made to the present invention without departing from the spirit of the present invention, and the scope of the appended claims is to be accorded the full scope of the invention.
Claims (3)
1. The comparator offset voltage calibration method based on the redundant bits is used for calibrating comparator offset voltage in output quantization code words obtained by a successive approximation analog-to-digital converter, a DAC capacitor array of the successive approximation analog-to-digital converter comprises redundant capacitors and quantization capacitors, each redundant capacitor and each quantization capacitor in the DAC capacitor array are divided into two capacitors with equal capacitance values to form a first split capacitor array and a second split capacitor array, the first split capacitor array comprises each redundant capacitor in the DAC capacitor array and one capacitor after each quantization capacitor is split, and the second split capacitor array comprises each redundant capacitor in the DAC capacitor array and the other capacitor after each quantization capacitor is split;
the method for calibrating the offset voltage of the comparator is characterized by comprising the following steps of:
connecting all upper capacitor plates in the first split capacitor array and the second split capacitor array with a common-mode voltage, and sampling 0 by using all lower capacitor plates in the first split capacitor array and the second split capacitor array through an SAR ADC;
step two, disconnecting the connection between the upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array and the common-mode voltage, and quantizing the sampling voltage obtained in the step one by the successive approximation analog-to-digital converter to generate a first quantized code word;
connecting common-mode voltage to upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array, connecting lower electrode plates of all capacitors after the split of all quantized capacitors in the first split capacitor array and the second split capacitor array to input voltage, connecting lower electrode plates of all capacitors after the split of all redundant capacitors in the first split capacitor array to positive reference voltage, and connecting lower electrode plates of all capacitors after the split of all redundant capacitors in the second split capacitor array to negative reference voltage; sampling input voltage by an SAR ADC (synthetic aperture radar) by utilizing all lower electrode plates of capacitors in the first split capacitor array and the second split capacitor array;
step four, disconnecting the upper electrode plates of all capacitors in the first split capacitor array and the second split capacitor array from the common-mode voltage, and quantizing the sampling voltage obtained in the step three by the successive approximation analog-to-digital converter to generate a second quantized codeword;
step five, after the offset voltage of the comparator is calibrated, the output quantized code word of the successive approximation analog-to-digital converter is the second quantized code word- (the first quantized code word-the ideal quantized code word), and the ideal quantized code word is the quantized code word obtained by quantizing 0 under the ideal condition that the comparator has no offset voltage;
and step six, converting the output quantization code word of the successive approximation analog-to-digital converter obtained in the step five into a binary code with the corresponding bit of the redundancy capacitor subtracted.
2. The method according to claim 1, wherein the successive approximation analog-to-digital converter is single-ended sampling, one input terminal of the comparator is connected to the DAC capacitor array, and the first step of sampling 0 by using all lower capacitor plates in the first split capacitor array and the second split capacitor array is performed by: and connecting all capacitor lower electrode plates in the first split capacitor array and the second split capacitor array with a ground voltage.
3. The method according to claim 1, wherein the successive approximation analog-to-digital converter is double-ended sampling, two input terminals of the comparator are respectively connected to one DAC capacitor array, and the first step of sampling 0 by using all lower capacitor plate pairs in the first split capacitor array and the second split capacitor array comprises: and connecting all the lower capacitor plates in the first split capacitor array with positive reference voltage, and connecting all the lower capacitor plates in the second split capacitor array with negative reference voltage.
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| CN110661530B (en) * | 2019-08-30 | 2022-12-20 | 电子科技大学 | Analog-to-digital converter and quantization method based on code word recombination |
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