CN1499730A - Pipeline structured A/D converter with high speed and high precision - Google Patents
Pipeline structured A/D converter with high speed and high precision Download PDFInfo
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Abstract
Circuit includes M pieces of sub modules cascaded in step by step. Each conversion module is composed of sub A/D conversion circuit, sub D/A conversion circuit, adder and operational amplifier of multiplication factor. Each sub module outputs N(1)-N(J)-N(M) conversion data. Based on weights, M pieces of data are added so as to obtain output of whole A/D convertor. There are error measure circuit and circuit of correcting digital error in the A/D convertor. The error measure circuit includes logic circuit and oscillators with their oscillating period direct proportional to magnitude of capacitance. Circuit of correcting digital error is composed of each sub-correcting module cascaded in step by step.
Description
The present invention relates to integrated circuit, particularly a kind of A/D converter with high speed and high precision of pipeline organization is made the field.
The present pipeline organization analog to digital converter of CMOS technology has reached the precision of 12 bit 80MSPS.Because the problem of figure adjustment algorithm, the further raising of precision is restricted; In CMOS technology, the design of high speed high gain operational amplifier is a difficult problem, thereby has also caused the increasing of analog to digital converter design difficulty.
Another designing technique that can reach high-precision adc is to adopt the sigma-delta structure, though the precision of this structure can reach 24 bits, but the defective of this structure is the narrow bandwidth of analog signal, circuit structure instability when adopting higher order filter, and need a huge digital signal processing circuit and complicated digital processing algorithm.
The defective of circuit structure is at present:
(1) precision is difficult to further raising.
(2) circuit structure and algorithm complexity.
(3) bandwidth of processing signals is restricted.
Be illustrated in figure 1 as the structural representation of present pipeline organization analog to digital converter.Circuit is made of M submodule of connecting step by step, and each grade submodule is exported N (1)～N (J)～individual translation data of N (M) respectively, and M data are carried out addition according to weight, just obtains the output of whole analog to digital converter.
In each level conversion submodule, all constitute by sampling hold circuit, analog-to-digital conversion submodule, digital-to-analogue conversion submodule, adder, multiplier factor operational amplifier.Sampling hold circuit is gathered the analog signal on some time points and is guaranteed that in the maintenance stage value does not change, and submodule number conversion module quantizes back output binary digital data with this analog signal.These data obtain the output of corresponding levels conversion submodule through coding: simultaneously numeral is exported through deducting from the value that keeps after the digital-to-analogue conversion, amplified driving after difference signal and multiplication factor multiply each other and use for next stage conversion submodule.
Fig. 2 is that sampling maintenance, addition and multiplication factor function are in the realization circuit of the switching capacity form of one.Annexation is: the IMP node is connected with the end of K switch 1, K5, K9, K26, the INN node is connected with the end of K switch 13, K17, K21, K33, node VREFP is connected with the end of K switch 8, K8, K12, K16, K20, K24, node VREFN is connected with the end of K switch 2, K6, K10, K14, K18, K22, and node VREF is connected with the end of K switch 3, K7, K11, K15, K19, K23 and K25, K32.The other end of K switch 1, K2, K3, K4 is connected with capacitor C 1 and the other end of C1 is connected with the positive input terminal of fully differential operational amplifier, the other end of K switch 5, K6, K7, K8 is connected with capacitor C 2 and the other end of C2 is connected with the positive input terminal of fully differential operational amplifier, the other end of K switch 9, K10, K11, K12 is connected with capacitor C 3 and the other end of C3 is connected with the positive input terminal of fully differential operational amplifier, and the positive input terminal of fully differential operational amplifier is connected with an end of capacitor C 7 and an other end of K switch 25 simultaneously.The other end of C7 connects K switch 26, K27 and K27 is connected with the negative output terminal of fully differential operational amplifier; The other end of K switch 13, K14, K15, K16 is connected with capacitor C 4 and the other end of C4 is connected with the negative input end of fully differential operational amplifier, the other end of K switch 17, K18, K19, K20 is connected with capacitor C 5 and the other end of C5 is connected with the negative input end of fully differential operational amplifier, the other end of K switch 21, K22, K23, K24 is connected with capacitor C 6 and the other end of C6 is connected with the negative input end of fully differential operational amplifier, and the negative input end of fully differential operational amplifier is connected with an end of capacitor C 8 and an other end of K switch 32 simultaneously.The other end of C8 connects K switch 33, K34 and K34 is connected with the positive output end of fully differential operational amplifier; K switch 28 cross-over connections are between node OUTP and OUTN, output node OUTN is connected with an end of capacitor C 10 and an end of K switch 31, output node OUTP is connected with an end of capacitor C 9 and an end of K switch 30, the end of K switch 35, K36, K37 is connected with VREF, the other end of K37 is connected with K31 and C12, the other end of K36 is connected with K30 and C11, and node CMFB is connected with capacitor C 9, C10 and K switch 29, and K29 is connected with capacitor C 11, C12 and K switch 35.K switch 1, K5, K9, K13, K17, K21, K26, K28, K33, K35, K36, K37 are controlled by the CLK4 logical signal, K switch 25, K32 are controlled by logical signal CLK5, K switch 29, K30, K31, K34, K27 are controlled by logical signal CLK1, SW1 control switch K24 and K2, SW2 control switch K23 and K3, SW3 control switch K22 and K4, SW4 control switch K20 and K6, SW5 control switch K19 and K7, SW6 control switch K18 and K8, SW7 control switch K16 and K10, SW8 control switch K15 and K11, SW9 control switch K14 and K12.
Operation principle is:
(1) sample phase, capacitor C 1, C2, C3, C7 will be charged to INP and capacitor C 4, C5, C6, C8 will be charged to INN this moment.
Q[C1]＝C1*(INP-VREF)
Q[C2]＝C2*(INP-VREF)
Q[C3]＝C3*(INP-VREF)
Q[C4]＝C4*(INN-VREF)
Q[C5]＝C5*(INN-VREF)
Q[C6]＝C6*(INN-VREF)
Q[C7]＝C7*(INP-VREF)
Q[C8]＝C8*(INN-VREF)
(2) the subtraction stage, capacitor C 1, C2, C3, C4, C5, C6 will be connected respectively to reference voltage VREFP by switch this moment, VREF, VREFN and electric charge on C7, the C8 remains unchanged.
Q[SUB_C1]＝C1*(SW1*(VREFN-VP_AMP)+SW2*(VREF-VP_AMP)+SW3*(VREFP-VP_AMP))
Q[SUB_C2]＝C2*(SW4*(VREFN-VP_AMP)+SW5*(VREF-VP_AMP)+SW6*(VREFP-VP_AMP))
Q[SUB_C3]＝C3*(SW7*(VREFN-VP_AMP)+SW8*(VREF-VP_AMP)+SW9*(VREFP-VP_AMP))
Q[SUB_C4]＝C4*(SW9*(VREFN-VN_AMP)+SW8*(VREF-VN_AMP)+SW7*(VREFP-VN_AMP))
Q[SUB_C5]＝C5*(SW6*(VREFN-VN_AMP)+SW5*(VREF-VN_AMP)+SW4*(VREFP-VN_AMP))
Q[SUB_C6]＝C6*(SW3*(VREFN-VN_AMP)+SW2*(VREF-VN_AMP)+SW1*(VREFP-VN_AMP))
In following formula, VP_AMP and VN_AMP are respectively the positive input terminal and the negative input end voltage of fully differential operational amplifier, and switch SW [1～9] is value 1 or 0 respectively.
(3) multiplication stages, CLK1 is with K switch 27, K34 conducting, and capacitor C 7, C8 are connected with OUTN with the output OUTP of fully differential operational amplifier respectively.
C7*(OUTP-VP_AMP)＝Q[C1]+Q[C2]+Q[C3]+Q[C7]+Q[SUB_C1]+Q[SUB_C2]+Q[SUB_C3]C8*(OUTN-VP_AMP)
＝Q[C4]+Q[C5]+Q[C6]+Q[C8]+Q[SUB_C4]+Q[SUB_C5]+Q[SUB_C6]
In above calculating, DC component is included.After removing DC component, computing formula is:
C7*OUTP＝(C1+C2+C3+C7)*INP+VDC
C8*OUTN＝(C4+C5+C6+C8)*INN+VDC
Set C1=C2=C3=C4=C5=C6=C7=C8
Then, OUTP=4*INP and OUTN=4*INN
(OUTP-OUTN)＝4*(INP-INN)
From above analysis, if there is small error in electric capacity, may cause finally exporting the incorrect of numerical result, the reason of mistake is aspect following two:
(1) multiplication factor, i.e. (C1+C2+C3+C7)/C7 and (C4+C5+C6+C7)/C8.The subtraction stage is with respect to SW[1～9] middle 1 corresponding control signal, DC component need be deducted, and the size of the DC component of removing is relevant with the relative accuracy of electric capacity.The error of sample phase and the relative accuracy of electric capacity are irrelevant.
The objective of the invention is to overcome the shortcoming of prior art, further improve the operating accuracy of analog to digital converter.
The objective of the invention is to realize by following method.
The A/D converter with high speed and high precision of pipeline organization, circuit comprise M the submodule of series connection step by step, and each conversion submodule comprises that submodule number conversion circuit, subnumber analog conversion circuit, adder and multiplication factor operational amplifier constitute; Each grade submodule is exported N (1)～N (J)～individual translation data of N (M) respectively, and M data are carried out addition according to weight, obtains the output of whole analog to digital converter; It is characterized by, analog to digital converter is provided with error measure circuit, digital error correction circuit;
The error measure circuit comprises oscillator and the logical circuit part that is directly proportional with capacitance size cycle of oscillation of utilizing electric capacity to constitute, and wherein logical circuit comprises two counter COUNTER1, COUNTER2 and a memory set MEMORY and a START﹠amp; END LOGIC module;
The digital error correction module is made of each sub-correction module of series connection step by step, and each self-correcting module comprises: multiplication factor counting circuit Multiplier calculator, multiplication factor correction module Multiplier correction and sampling addition digital error correction module Sample/adder digital error correction.Like this,
(1) utilizes measuring circuit accurately to measure the relative size of electric capacity, and represent with digital form.
(2) multiplication factor is proofreaied and correct: multiplication factor is by the relative size decision of electric capacity, after recording the relative weighting of each electric capacity again, just can obtain actual multiplication factor, multiplication factor be returned to ideal value, obtain carrying out the precise figures expression of the preceding signal of multiplying at numeric field.
(3) subtraction is proofreaied and correct: subtraction is by with SW[1～9] in be that voltage on 1 the corresponding electric capacity of control signal deducts a direct voltage and obtains, therefore, the direct voltage that deducts is treated as numeral 1, the relative size of electric capacity promptly is the weight of this numeral 1, and the precise figures that utilize the computing that falls back to obtain the preceding signal of subtraction are expressed.
(4) with in the analog to digital converter step by step the conversion submodule of series connection by after carry out the figure adjustment computing forward step by step, till the precise figures that obtain input signal are expressed.
Description of drawings is as follows:
Fig. 1: the structural representation of current pipeline organization analog to digital converter
Fig. 2: the switched-capacitor circuit of sampling/subtraction/multiplication
Fig. 3: the structural representation of improved pipeline organization analog to digital converter
Fig. 4: electric capacity relative accuracy measuring circuit
Fig. 5: digital error correction schematic diagram
Below in conjunction with accompanying drawing structure of the present invention is described in further detail.
Improved pipeline organization analog to digital converter schematic diagram shown in Figure 3, circuit is made of M submodule of connecting step by step, each grade submodule is exported N (1)～N (J)～individual translation data of N (M) respectively, and M data are carried out addition according to weight, just obtains the output of whole analog to digital converter.
After powering on, measurement module records the numeral expression of the relative accuracy of each electric capacity in each conversion submodule, and this data passes is changed the data that submodule is exported to correction module to proofread and correct each.
Correction module obtains the numeral output of each conversion submodule and the state of each switch SW [1～9], obtain in the measurement module capacitance point simultaneously to the data of precision, thereby the error of calibration shift submodule output is till obtaining importing the precise figures expression of analog signal.
On the analog-to-digital conversion direction, in each level conversion submodule, all constitute by sampling hold circuit, analog-to-digital conversion submodule, digital-to-analogue conversion submodule, adder, multiplier factor operational amplifier.Sampling hold circuit is gathered the analog signal on some time points and is guaranteed that in the maintenance stage value does not change, and submodule number conversion module quantizes back output binary digital data with this analog signal.These data obtain the output of conversion submodule at the corresponding levels through coding; To from the value of maintenance, deduct after the digital-to-analogue conversion of numeral output process simultaneously, and amplify after difference signal and multiplication factor multiply each other to drive and change the submodule use for next stage.
Figure 4 shows that electric capacity relative accuracy test circuit.Annexation is: reference voltage Vref concatenation operation amplifier positive input terminal, the operational amplifier negative input end connects resistance and transistor MT1 source electrode, the output of MT1 grid concatenation operation amplifier and drain and connect current mirror I1, current mirror I1, I2, the I3 ratio is 1: 1: K, current mirror I2 connects another one current mirror I4, current mirror I4, the I5 ratio is 1: N, electric current I 3 and I5 and switch SW 1, SW2 connects, SW1, SW2 one end is connected with electric capacity and comparator positive input terminal, an other end is ground connection and power supply respectively, switch SW 1, SW2 is controlled by OUT and OUTB, the negative input end of comparator connects another one reference voltage Vref 2, exports OUTB and OUT respectively behind the output process two-stage inverter of comparator.
OUT is the input of COUNTER1 and CLKref is the input of COUNTER2, and counter COUNTER1 and COUNTER2 are subjected to Start﹠amp; End LOGIC module controls, they are output as the input of MEMORY module, the numeral expression of the relative accuracy of each electric capacity of storage in memory module MEMORY.
Operation principle is: when voltage on the electric capacity when returning the higher limit of comparator between the dead zone, OUTB is low for height OUT, switch SW 1 imports the electric capacity charging with the I3 electric current, switch SW 2 imports power supplys with electric current I 5; When voltage on the electric capacity when returning the higher limit of comparator between the dead zone, OUT is low for height OUTB, switch SW 2 imports capacitor discharge with the I5 electric current, switch SW 1 imports ground with electric current I 3.
When voltage on the electric capacity was lower than back the lower limit of comparator between the dead zone, OUTB was low for height OUT again, begins a new charge cycle, thereby obtains a triangular wave oscillator, and OUT and OUTB are periodic pulse signal.The cycle of pulse signal and RC time constant are proportional.
Counter COUNTER1 and COUNTER2 are opened for OUT and reference clock CLKref counting simultaneously, when counting down to a determined value M2, COUNTER2 stops the counting of COUNTER1 and COUNTER2 simultaneously, the result who supposes COUNTER1 this moment is NUM_C1, NUM_C1 is stored among the MEMORY: another method of counting is: the counting that stops COUNTER1 and COUNTER2 when COUNTER1 count down to a determined value M1 simultaneously, the result who supposes COUNTER2 this moment is stored in NUM_C1 among the MEMORY for NUM_C1.At this is the example explanation with the first method.
The electric current of current mirror I1 is: I1=Vref/R
Charging current is: I3=K*I1
Discharging current is: I5=N*I1
The triangular wave rising edge time: C*dV/I3
The triangular wave trailing edge time: C*dV/I5
Triangle is wave period: T=RC* (dv/Vref) * (1/K+ 1/N)
The cycle of reference clock is Tref, then has:
T*NUM_C1＝Tref*M2
The absolute value that obtains the RC time constant thus is:
RC＝Tref*(M2/NUM_C1)*(Vref/dV)*(K*N/(K+N))
In following formula, dV is the voltage between the dead zone that returns of comparator, and Vref is a reference voltage, determines and varies with temperature little voltage as voltage values such as bandgap voltage references.
So that C1 is measured as example,, obtain by above analysis:
NUM_C1=factor/C1, i.e. C1=FACTOR/NUM_C1, FACTOR and factor are constant.
Each electric capacity in each grade conversion submodule is carried out above-mentioned measurement, obtain the numeral expression NUM[1～M of the relative accuracy of each electric capacity] [1～N], wherein M be use in the analog to digital converter each the conversion submodule number, and the number of cascade structure, N is for being used in each grade circuit sampling/number of the electric capacity of subtraction/multiplication.
Digital error correction schematic diagram shown in Figure 5, circuit is by the M level or be less than M level correcting circuit and be in series, its order of connection is opposite with the waterfall sequence of analog-to-digital each conversion submodule, be first output MSB signal and the module that at first precision of lsb signal or technology decision be need not to proofread and correct in the correcting circuit begins in the analog-to-digital conversion, proofread and correct step by step until the precise number that obtains importing analog signal and express.
Each syndrome module comprises 3 parts, multiplication factor counting circuit (Multiplier calculator), multiplication factor correcting circuit (Multiplier correction) and sampling/subtraction digital correction circuit (Sample/adderdigital error correction).In the submodule each all obtains the data of the relative accuracy of each electric capacity from measuring circuit, also need to obtain by the submodule of conversion from modulus the information of each switch during subtraction is proofreaied and correct simultaneously.
Below briefly introduce bearing calibration.
(1) multiplication factor is proofreaied and correct: if in analog-to-digital conversion, adopt single-ended operational amplifier, be example with Fig. 2 then, only have half of circuit, so:
Computing formula is: (C1+C2+C3+C7)/and C7
Multiplication factor ideal value: 4
Multiplication factor actual numerical value: (1/NUM_C1+ 1/NUM_C2+ 1/NUM_C3+ 1/NUM_C7)/(1/NUM_C1)
Setting data IN (J+1) is for changing the data of submodule through the analog to digital converter J+1 level of corrected correct expression, then uncorrected J level output N (J) and IN (J+1) are obtained uncorrected data I N according to addition, then the accurate data before the multiplication factor computing are:
IN[Pre_MULT]＝4/((1/NUM_C1+ 1/NUM_C2+ 1/NUM_C3+ 1/NUM_C7)/(1/NJM_C1))
Circuit at the fully differential structure has:
IN[Pre_MULT]＝8/
(((1/NUM_C1+ 1/NUM_C2+ 1/NUM_C3+ 1/NUM_C7)/(1/NUM_C1)+
((1/NUM_C4+ 1/NUM_C5+ 1/NUM_C6+ 1/NUM_C8)/(1/NUM_C8)))
Wherein, IN[Pre_MULT] be the precise number expression of the analog signal before the multiplying.
(2) subtraction is proofreaied and correct
The computing formula of decrement is:
Q[SUB_C1]＝FACTOR/NUM_C1*(-SW1*1+SW2*0+SW3*1)
Q[SUB_C2]＝FACTOR/NUM_C2*(-SW4*1+SW5*0+SW6*1)
Q[SUB_C3]＝FACTOR/NUM_C3*(-SW7*1+SW8*0+SW9*1)
Q[SUB_C4]＝FACTOR/NUM_C4*(SW9*1+SW8*0-SW7*1)
Q[SUB_C5]＝FACTOR/NUM_C5*(SW6*1+SW5*0-SW4*1)
Q[SUB_C6]＝FACTOR/NUM_C6*(SW3*1+SW2*0-SW1*1)
The computing formula of AC sampling
Q[C1]＝FACTOR/NUM_C1*INP(D)
Q[C2]＝FACTOR/NUM_C2*INP(D)
Q[C3]＝FACTOR/NUM_C3*INP(D)
Q[C4]＝FACTOR/NUM_C4*INN(D)
Q[C5]＝FACTOR/NUM_C5*INN(D)
Q[C6]＝FACTOR/NUM_C6*INN(D)
Q[C7]＝FACTOR/NUM_C7*INP(D)
Q[C8]＝FACTOR/NUM_C8*INN(D)
Wherein, INP (D), INN (D) are the precise figures expression of the analog signal input of J level circuit.
(Q[SUB_C1]+Q[SUB_C2]+Q[SUB_C3])*weight+Q[C1]+Q[C2]+Q[C3]+Q[C7]+(Q[SUB_C4]+Q[SUB_C5]+Q[SUB_C6])*weight+Q[C4]+Q[C5]+Q[C6]+Q[C8]＝IN[Pre_MULT]
OUT(J)＝INP(D)-INN(D)
Thus, the precise number that obtains the analog signal input of J level circuit is expressed OUT (J), with of the data input of these data as J-1 level correcting circuit, obtain the accurate expression of J-1 level breadboardin signal by above step, till the accurate expression of the analog signal input that obtains the 1st grade of circuit.
Claims (11)
1, a kind of A/D converter with high speed and high precision of pipeline organization, circuit comprises M the submodule of series connection step by step, each conversion submodule comprises that submodule number conversion circuit, subnumber analog conversion circuit, adder and multiplication factor operational amplifier constitute: each grade submodule is exported N (1)～N (J)～individual translation data of N (M) respectively, M data are carried out addition according to weight, obtain the output of whole analog to digital converter: it is characterized by, analog to digital converter is provided with the error measure circuit, digital error correction circuit:
The error measure circuit comprises oscillator and the logical circuit part that is directly proportional with capacitance size cycle of oscillation of utilizing electric capacity to constitute, and wherein logical circuit comprises two counter COUNTER1, COUNTER2 and a memory set MEMORY and a START﹠amp; END LOGIC module:
The digital error correction module is made of each sub-correction module of series connection step by step, and each self-correcting module comprises: multiplication factor counting circuit Multiplier calculator, multiplication factor correction module Multipliercorrection and sampling addition digital error correction module Sample/adder digital error correction.
2, the A/D converter with high speed and high precision of pipeline organization according to claim 1 is characterized by: described error measure circuit is to measure realization by the relative value difference accumulated error to two similar devices in a definite time period to the measurement of slight error:
3, the A/D converter with high speed and high precision of pipeline organization according to claim 1, it is characterized by: described error measure circuit is to the measurement of a plurality of electric capacity matching degrees, be by constructing an oscillator, the cycle of oscillator generation signal is directly proportional with the size of electric capacity: in a definite time period number of oscillator pulses signal is measured, thereby obtain the data about several electric capacity matching degrees, these data are stored one by one with digital form.
4, the A/D converter with high speed and high precision of pipeline organization according to claim 1, it is characterized by: described error measure circuit is made of each sub-correction module of series connection step by step, and each sub-correction module comprises: multiplication factor counting circuit Multiplier calculator, multiplication factor correction module Multipliercorrection and sampling addition digital error correction module Sample/adder digital error correction.Series sequence in the figure adjustment module between each submodule and the series sequence of normally carrying out between analog-to-digital each submodule are reciprocal: the digital operation order of syndrome inside modules also is reciprocal with the analog order of changing in the submodule.
5, the A/D converter with high speed and high precision of pipeline organization according to claim 4 is characterized by: described multiplication factor counting circuit both had been suitable for single-ended operational amplifier structure, also was suitable for fully differential operational amplifier structure; The calculating of multiplication factor realizes at numeric field.
6, the A/D converter with high speed and high precision of pipeline organization according to claim 4, it is characterized by: described multiplication factor counting circuit calibration shift submodule is at last multiplication output stage, the error between desirable multiplication factor and the actual multiplication factor; This proofreaies and correct in numeric field realization and actual multiplication factor data and obtains from the error measure circuit.
7, the A/D converter with high speed and high precision of pipeline organization according to claim 4 is characterized by: the error that described sampling addition digital error correction module calibration shift submodule is introduced when sampling output is carried out subtraction with conversion submodule seed DAC output; This proofreaies and correct in numeric field realization and actual additive factor data and obtains from the error measure circuit; Error correction is to treat as linear coefficient measuring the error information that obtains.
8, the A/D converter with high speed and high precision of pipeline organization according to claim 2 is characterized by: the identical time period in the described error measure circuit can utilize inner high stable clock signal to obtain; Also can utilize outside high stable clock signal to obtain; Perhaps obtain by special phase-locked loop.
9, the A/D converter with high speed and high precision of pipeline organization according to claim 1, it is characterized by: described pipeline organization analog to digital converter utilizes original serial module structure step by step to obtain having the data converted step by step of error, the control information of utilizing the error measure module to obtain, push calculation to each submodule is counter, thereby progressively obtain the output of upper level circuit, the exact figure expression formula of circuit input just at the corresponding levels, last until the exact figure expression formula that obtains original input signal, and analog-to-digital precise information.
10, the A/D converter with high speed and high precision of pipeline organization according to claim 9, it is characterized by: described step by step numeral is counter pushes calculation and can begin the anti-calculation that pushes from last module, also can be from the maximum tolerance place module of technology decision.
11. the A/D converter with high speed and high precision of pipeline organization according to claim 1, it is characterized by, relative accuracy test circuit annexation is: reference voltage Vref concatenation operation amplifier positive input terminal, the operational amplifier negative input end connects resistance and transistor MT1 source electrode, the output of MT1 grid concatenation operation amplifier and drain and connect current mirror I1, current mirror I1, I2, the I3 ratio is 1: 1: K, current mirror I2 connects another one current mirror I4, current mirror I4, the I5 ratio is 1: N, electric current I 3 and 15 and switch SW 1, SW2 connects, SW1, SW2 one end is connected with electric capacity and comparator positive input terminal, an other end is ground connection and power supply respectively, switch SW 1, SW2 is controlled by OUT and OUTB, the negative input end of comparator connects another one reference voltage Vref 2, exports OUTB and OUT respectively behind the output process two-stage inverter of comparator.
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2002
- 2002-11-08 CN CNA021340269A patent/CN1499730A/en active Pending
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