CN105743504A - Digital analogue converter and source driving circuit - Google Patents
Digital analogue converter and source driving circuit Download PDFInfo
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- CN105743504A CN105743504A CN201610060024.5A CN201610060024A CN105743504A CN 105743504 A CN105743504 A CN 105743504A CN 201610060024 A CN201610060024 A CN 201610060024A CN 105743504 A CN105743504 A CN 105743504A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a digital analogue converter and a source driving circuit. In the invention, a harmonic signal is generated through a harmonic generator and sampled through a sampling unit; therefore, conversion from a digital signal to an analogue signal is realized; the digital analogue converter is simple in structure; the occupation area can be effectively reduced; the power consumption can be reduced; and thus, the source driving circuit adopting the digital analogue converter can be applicable to a flat-panel display having relatively high resolution.
Description
Technical field
The present invention relates to technical field of flat panel display, particularly to a kind of digital analog converter and source electrode drive circuit.
Background technology
Along with the development of information-intensive society, people are growing to the demand of display device.In order to meet this requirement, various panel display apparatus such as thin film transistor LCD device (TFT-LCD), plasma display device (PDP), organic light emitting display (OLED), field emission display device (FED) etc. are obtained for swift and violent development.
Refer to Fig. 1, it is the structural representation of panel display apparatus of prior art.As shown in Figure 1, existing panel display apparatus 10 generally includes source electrode drive circuit 100, gate driver circuit 110, sequential control circuit 120 and display floater 130, described sequential control circuit 120 is used for controlling described source electrode drive circuit 100 and gate driver circuit 110, driving voltage is sent to described display floater 130 by data wire (not shown) by described source electrode drive circuit 100, scanning signal is sent to described display floater 130 by scanning line (not shown) by described gate driver circuit 110, data signal that described display floater 130 provides according to described source electrode drive circuit 100 and the scanning signal that described gate driver circuit 110 provides show image.
Wherein, described source electrode drive circuit 100 generally includes digital analog converter (DACS), the digital signal output analogue signal that described digital analog converter provides in response to described sequential control circuit 120, described source electrode drive circuit 100 utilizes described digital analog converter digital signal transfers to corresponding driving voltage and provides described driving voltage to display floater 130.
But, the volume of described digital analog converter is generally relatively big, and its area taken accounts for the 60% of the whole source electrode drive circuit gross area, therefore causes that the volume of the chip for carrying source electrode drive circuit cannot reduce further.
Along with the development of Display Technique and electronic science and technology, the resolution of panel display apparatus improves constantly, and has reached full HD standard at present, follow-up also will develop into ultra high-definition standard.But corresponding, due to the raising of monitor resolution, in described source electrode drive circuit 100, the area occupied of digital analog converter and power consumption are increasing.For the resolution high-resolution panel display apparatus more than 10, existing digital analog converter is excessive due to area occupied and power consumption, cannot meet the actual demand of product.
Base this, how to solve the area occupied of digital analog converter in existing source electrode drive circuit and the problem that power consumption is excessive, become the technical problem that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
It is an object of the invention to provide a kind of digital analog converter and source electrode drive circuit, to solve the area occupied of source electrode drive circuit in existing source electrode drive circuit and the problem that power consumption is excessive.
For solving the problems referred to above, the present invention provides a kind of digital analog converter, described digital analog converter includes: digital analog converter, it is characterised in that including: clock counter, data register, comparator, harmonic generation device, the first sample-and-hold circuit and the second sample-and-hold circuit；
The control end of described data register, the end that controls controlling end and the second sample-and-hold circuit of comparator is all connected with the first outfan of described clock counter, the input of described harmonic generation device and an input of comparator are all connected with the second outfan of described clock counter, the input of described data register is used for receiving digital signal, the outfan of described data register is connected with another input of described comparator, the outfan of described comparator is connected with the control end of described first sample-and-hold circuit, the outfan of described harmonic generation device is connected with the input of described first sample-and-hold circuit, the outfan of described first sample-and-hold circuit is connected with the input of described second sample-and-hold circuit.
Optionally, in described digital analog converter, the first outfan of described clock counter is used for exporting the first clock signal, and the second outfan of described clock counter is used for exporting second clock signal；
The first clock signal output registration signal that described data register provides according to described digital signal and clock counter, the described comparator comparative result output control signal according to described registration signal with second clock signal, described harmonic generation device produces harmonic signal according to described second clock signal.
Optionally, in described digital analog converter, described harmonic generation device adopts diclinic rate score indicator or ∑ Delta modulator.
Optionally, in described digital analog converter, the structure of described first sample-and-hold circuit and the second sample-and-hold circuit is identical.
Accordingly, present invention also offers a kind of digital analog converter, described digital analog converter includes clock, enumerator, data register, comparator, harmonic generation device and sampling unit；
The input of described enumerator and harmonic wave maker is all connected with the second outfan of described clock, the outfan of described enumerator is connected with an input of described comparator, the end that controls of described data register is connected with the first outfan of described clock, the input of described data register is used for receiving digital signal, the outfan of described data register is connected with another input of described comparator, and the outfan of described comparator and harmonic wave maker is all connected with described sampling unit.
Optionally, in described digital analog converter, the first outfan of described clock is used for providing the first clock signal, and the second outfan of described clock is used for providing second clock signal；
Described enumerator exports clock count signal according to described second clock signal, described data register exports registration signal according to described digital signal and the first clock signal, the described comparator comparative result output control signal according to described registration signal with clock count signal, described harmonic generation device produces and output harmonic wave signal according to described second clock signal.
Optionally, in described digital analog converter, described sampling unit includes the first sampling channel, the second sampling channel and amplifier, the outfan of described first sampling channel and the second sampling channel is all connected with the positive side input of described amplifier, and the minus side input of described amplifier is connected with the outfan of described amplifier.
nullOptionally，In described digital analog converter，Described first sampling channel includes the first permutator、First clock buffer、First follower and the first sampling capacitance，Described second sampling channel includes the second permutator、Second clock buffer、Second follower and the second sampling capacitance，The input of described first permutator and the second permutator is all connected with the outfan of described harmonic generation device，The outfan of described first permutator is connected with the first substrate of described first clock buffer input and the first sampling capacitance，The outfan of described second permutator is connected with the first substrate of described second clock buffer input and the second sampling capacitance，The outfan of described first clock buffer and second clock buffer is all connected with the positive side input of described amplifier，The input of described first follower and the second follower is all connected with the outfan of described comparator，The outfan of described first follower is connected with the control end of described first permutator，The outfan of described second follower is connected with the control end of described second permutator.
Optionally, in described digital analog converter, described harmonic generation device adopts diclinic rate score indicator or ∑ Delta modulator.
Accordingly, present invention also offers a kind of source electrode drive circuit, described source electrode drive circuit includes digital analog converter as above.
In digital analog converter provided by the invention and source electrode drive circuit, produce harmonic signal by harmonic generation device and utilize sampling unit that described harmonic signal is sampled, and then realize the digital signal conversion to analogue signal, described digital analog converter simple in construction, can effectively reduce area occupied and reduce power consumption so that adopt the source electrode drive circuit of described digital analog converter can be applicable to the flat faced display of higher resolution.
Accompanying drawing explanation
Fig. 1 is the structural representation of the panel display apparatus of prior art；
Fig. 2 is the structural representation of the digital analog converter of the embodiment of the present invention one；
Fig. 3 is the working waveform figure of the digital analog converter of the embodiment of the present invention one；
Fig. 4 is the structural representation of the digital analog converter of the embodiment of the present invention two.
Detailed description of the invention
A kind of digital analog converter and the source electrode drive circuit that the present invention are proposed below in conjunction with the drawings and specific embodiments are described in further detail.According to the following describes and claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all adopts the form simplified very much and all uses non-ratio accurately, only in order to convenience, the purpose aiding in illustrating the embodiment of the present invention lucidly.
[embodiment one]
Refer to Fig. 2, it is the structural representation of digital analog converter of the embodiment of the present invention one.As in figure 2 it is shown, described digital analog converter 200 includes: clock counter 210, data register 220, comparator 230, harmonic generation device the 240, first sample-and-hold circuit 250 and the second sample-and-hold circuit 260；Control end, the control end C of comparator 230 and the end that controls of the second sample-and-hold circuit 260 of described data register 220 are all connected with the first outfan of described clock counter 210, and the input of described harmonic generation device 240 and the second input B of comparator 230 are all connected with the second outfan of described clock counter 210；The outfan of described data register 220 is connected with the first input end A of described comparator 230, the outfan of described comparator 230 is connected with the control end of described first sample-and-hold circuit 250, the outfan of described harmonic generation device 240 is connected with the input of described first sample-and-hold circuit 250, and the outfan of described first sample-and-hold circuit 250 is connected with the input of described second sample-and-hold circuit 260.
Concrete, described clock counter 210 includes the first outfan and the second outfan, and described clock counter 210 exports the first clock signal clk by described first outfan, by described second outfan output second clock signal S2.Wherein, described first clock signal clk output is to the control end of described data register 220, comparator 230 and the second sample-and-hold circuit 260, and described second clock signal S2 exports the second input B of the input to described harmonic generation device 240 and comparator 230.
Described data register 220 is used for receiving digital signal S1, and according to the first clock signal clk output registration signal S3 that described clock counter 210 provides.
The first input end A of described comparator 230 is connected with the outfan of described data register 220, for receiving the registration signal S3 that described data register 220 exports, second input B of described comparator 230 is connected with the second outfan of described clock counter 210, for receiving the second clock signal S2 that described clock counter 210 exports, described comparator 230 outfan is connected with the control end of described first sample-and-hold circuit 250, for exporting control signal S4 to described first sample-and-hold circuit 250.
Described harmonic generation device 240 is for receiving the second clock signal S2 that described clock counter 210 provides, and produces harmonic signal S5 according to described second clock signal S2.
In the present embodiment, described harmonic generation device 240 can adopt diclinic rate score indicator or ∑ Delta modulator.
Described first sample-and-hold circuit 250 and the second sample-and-hold circuit 260 are connected, and sample for the harmonic signal S5 respectively described harmonic generation device 240 produced and export analogue signal.Wherein, the input of described first sample-and-hold circuit 250 is connected with the outfan of described harmonic generation device 240, for receiving the harmonic signal S5 of described harmonic generation device 240 output.The end that controls of described first sample-and-hold circuit 250 is connected with the outfan of described comparator 230, for receiving the control signal S4 of the output of described comparator 230.The outfan of described first sample-and-hold circuit 250 is connected with the input of described second sample-and-hold circuit 260, for the sampled signal S6 after sampling to described second sample-and-hold circuit 260 output first time.The input of described second sample-and-hold circuit 260 is connected with the outfan of described first sample-and-hold circuit 250, for receiving the sampled signal S6 of described first sample-and-hold circuit 250 output.The end that controls of described second sample-and-hold circuit 260 is connected with the first outfan of described clock counter 210, for receiving the first clock signal clk that described clock counter 210 provides.The outfan of described second sample-and-hold circuit 260 is for exporting the analogue signal S7 after second time is sampled.
Preferably, the structure of described first sample-and-hold circuit and the second sample-and-hold circuit is identical.
Refer to Fig. 3, it is the working waveform figure of digital analog converter of the embodiment of the present invention one.nullAs shown in 2 and Fig. 3，Described clock counter 210 exports the first clock signal clk and second clock signal S2，One cycle corresponding digital signal S1 of described first clock signal clk，One cycle correspondence set of number signal S1 (0 of described second clock signal S2，0，1，2，3，4，5，6，7 or 7，7，6，5，4，3，2，1，0)，Its first input end A and the second input B registration signal S3 received and second clock signal S2 is compared and exports control signal S4 according to comparative result by described comparator 230，When described registration signal S3 and second clock signal S2 is unequal, the control signal S4 of the outfan output of described comparator 230 is invalid，When described registration signal S3 is equal with second clock signal S2, the control signal S4 of the outfan output of described comparator 230 is effective，Described first sample-and-hold circuit 250 is sampled according to the described control signal S4 harmonic signal S5 that described harmonic generation device 240 is exported，The sampled signal S6 of described first sample-and-hold circuit 250 output is again sampled by described second sample-and-hold circuit 260 according to described first clock signal clk，Final output analogue signal S7.
In the present embodiment, described first sample-and-hold circuit 250 and the second sample-and-hold circuit 260 forming sampling unit, the harmonic signal S5 that described harmonic generation device 240 is produced samples, and then output analogue signal S7.
The digital analog converter 200 that the present embodiment provides adopts harmonic generation device to realize the digital signal conversion to analogue signal, and compared with traditional digital analog converter, structure is more simple, and power consumption is lower.
[embodiment two]
Refer to Fig. 4, it is the structural representation of digital analog converter of the embodiment of the present invention two.As shown in Figure 4, described digital analog converter 300 includes: clock (not shown), enumerator 310, data register 320, comparator 330, harmonic generation device 340 and sampling unit 350；The input of described enumerator 310 and harmonic wave maker 340 is all connected with the second outfan of described clock, the outfan of described enumerator 310 is connected with an input of described comparator 330, the end that controls of described data register 320 is connected with the first outfan of described clock, the input of described data register 320 is used for receiving digital signal S1, the outfan of described data register 320 is connected with another input of described comparator 330, and the outfan of described comparator 330 and harmonic wave maker 340 is all connected with described sampling unit 350.
Concrete, the first outfan of described clock and the second outfan are for providing the first clock signal HCLK and second clock signal RCLK respectively.Wherein, described first clock signal HCLK output is to the control end of described data register 320, and described second clock signal RCLK exports the input to described harmonic generation device 340 sum counter 310 respectively.Described enumerator 310 exports clock count signal according to described second clock signal RCLK.Described data register 320 is used for receiving digital signal S1, and the first clock signal HCLK provided according to described digital signal S1 and clock counter 310 exports registration signal.The described comparator 330 comparative result output control signal according to described registration signal with clock count signal.Described harmonic generation device 340 produces and output harmonic wave signal according to described second clock signal RCLK.
In the present embodiment, described harmonic generation device 340 can adopt diclinic rate score indicator or ∑ Delta modulator.
Described sampling unit 350 includes the first sampling channel, the second sampling channel and amplifier 357, the outfan of described first sampling channel and the second sampling channel is all connected with the positive side input of described amplifier 357, and the minus side input of described amplifier 357 is connected with the outfan of described amplifier 357.
nullWherein，Described first sampling channel includes the first permutator 351a、First clock buffer 353a、First follower 355a and the first sampling capacitance C1，Described second sampling channel includes the second permutator 351b、Second clock buffer 353b、Second follower 355b and the second sampling capacitance C2，The input of described first permutator 351a and the second permutator 351b is all connected with the outfan of described harmonic generation device 340，The outfan of described first permutator 351a is connected with the first substrate of described first clock buffer 353a input and the first sampling capacitance C1，The outfan of described second permutator 351b is connected with the first substrate of described second clock buffer 353b input and the second sampling capacitance C2，The outfan of described first clock buffer 353a and second clock buffer 353b is all connected with the positive side input of described amplifier 357，The input of described first follower 355a and the second follower 355b is all connected with the outfan of described comparator 330，The outfan of described first follower 355a is connected with the control end of described first permutator 351a，The outfan of described second follower 355b is connected with the control end of described second permutator 351b.
As shown in Figure 4, the control signal that described first follower 355a exports according to the first reference signal PH and described comparator 330 exports the first switching signal to described first permutator 351a, the control signal that described second follower 355b exports according to the second reference signal NH and described comparator 330 exports second switch signal to described second permutator 351b, described first clock buffer 353a exports the first buffering signals according to described first switching signal and the second reference signal NH, described second clock buffer 353b exports the second buffering signals according to described second switch signal and the first reference signal PH, export after being carried out signal amplification by described amplifier 357 after described first buffering signals and the second buffering signals superposition.
The harmonic signal that described harmonic generation device 340 is produced by described sampling unit 350 is sampled, and then output analogue signal.The present embodiment and embodiment one are distinctive in that, the structure of the sampling unit that harmonic signal is sampled is different.In the present embodiment, described sampling unit 350 is made up of described first permutator 351a, the second permutator 351b, the first clock buffer 353a, second clock buffer 353b, the first follower 355a, the second follower 355b, the first sampling capacitance C1, the second sampling capacitance C2 and amplifier 357.And the sampling unit of embodiment one is made up of described first sample-and-hold circuit 250 and the second sample-and-hold circuit 260.
It addition, in the present embodiment, described clock sum counter 310 is independent, realizes clock and tally function respectively, enumerator 310 the second clock signal RCLK described clock provided counts and export clock count signal.And the clock counter 210 in embodiment one is made as a whole, itself having clock and tally function, directly exported second clock signal S2 by described clock counter 210, described second clock signal S2 is equivalent to described clock count signal.
[embodiment three]
Accordingly, present invention also offers a kind of source electrode drive circuit, described source electrode drive circuit includes digital analog converter as above.Specifically refer to above, repeat no more herein.
The source electrode drive circuit that the present embodiment provides adopts novel digital analog converter to replace traditional digital analog converter, is conducive to reduction further for carrying volume and the power consumption of the chip of described source electrode drive circuit.From another angle, adopt described source electrode drive circuit can realize higher resolution on existing chip area, for instance the high-resolution of more than 10.
To sum up, in digital analog converter provided by the invention and source electrode drive circuit, produce harmonic signal by harmonic generation device and utilize sampling unit that described harmonic signal is sampled, and then realize the digital signal conversion to analogue signal, described digital analog converter simple in construction, can effectively reduce area occupied and reduce power consumption so that adopt the source electrode drive circuit of described digital analog converter can be applicable to the flat faced display of higher resolution.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, belongs to the protection domain of claims.
Claims (10)
1. a digital analog converter, it is characterised in that including: clock counter, data register, comparator, harmonic generation device, the first sample-and-hold circuit and the second sample-and-hold circuit；
The control end of described data register, the end that controls controlling end and the second sample-and-hold circuit of comparator is all connected with the first outfan of described clock counter, the input of described harmonic generation device and an input of comparator are all connected with the second outfan of described clock counter, the input of described data register is used for receiving digital signal, the outfan of described data register is connected with another input of described comparator, the outfan of described comparator is connected with the control end of described first sample-and-hold circuit, the outfan of described harmonic generation device is connected with the input of described first sample-and-hold circuit, the outfan of described first sample-and-hold circuit is connected with the input of described second sample-and-hold circuit.
2. digital analog converter as claimed in claim 1, it is characterised in that the first outfan of described clock counter is used for exporting the first clock signal, and the second outfan of described clock counter is used for exporting second clock signal；
The first clock signal output registration signal that described data register provides according to described digital signal and clock counter, the described comparator comparative result output control signal according to described registration signal with second clock signal, described harmonic generation device produces harmonic signal according to described second clock signal.
3. digital analog converter as claimed in claim 1, it is characterised in that described harmonic generation device adopts diclinic rate score indicator or ∑ Delta modulator.
4. digital analog converter as claimed in claim 1, it is characterised in that the structure of described first sample-and-hold circuit and the second sample-and-hold circuit is identical.
5. a digital analog converter, it is characterised in that including: clock, enumerator, data register, comparator, harmonic generation device and sampling unit；
The input of described enumerator and harmonic wave maker is all connected with the second outfan of described clock, the outfan of described enumerator is connected with an input of described comparator, the end that controls of described data register is connected with the first outfan of described clock, the input of described data register is used for receiving digital signal, the outfan of described data register is connected with another input of described comparator, and the outfan of described comparator and harmonic wave maker is all connected with described sampling unit.
6. digital analog converter as claimed in claim 5, it is characterised in that the first outfan of described clock is used for providing the first clock signal, and the second outfan of described clock is used for providing second clock signal；
Described enumerator exports clock count signal according to described second clock signal, described data register exports registration signal according to described digital signal and the first clock signal, the described comparator comparative result output control signal according to described registration signal with clock count signal, described harmonic generation device produces and output harmonic wave signal according to described second clock signal.
7. digital analog converter as claimed in claim 5, it is characterized in that, described sampling unit includes the first sampling channel, the second sampling channel and amplifier, the outfan of described first sampling channel and the second sampling channel is all connected with the positive side input of described amplifier, and the minus side input of described amplifier is connected with the outfan of described amplifier.
null8. digital analog converter as claimed in claim 7，It is characterized in that，Described first sampling channel includes the first permutator、First clock buffer、First follower and the first sampling capacitance，Described second sampling channel includes the second permutator、Second clock buffer、Second follower and the second sampling capacitance，The input of described first permutator and the second permutator is all connected with the outfan of described harmonic generation device，The outfan of described first permutator is connected with the first substrate of described first clock buffer input and the first sampling capacitance，The outfan of described second permutator is connected with the first substrate of described second clock buffer input and the second sampling capacitance，The outfan of described first clock buffer and second clock buffer is all connected with the positive side input of described amplifier，The input of described first follower and the second follower is all connected with the outfan of described comparator，The outfan of described first follower is connected with the control end of described first permutator，The outfan of described second follower is connected with the control end of described second permutator.
9. digital analog converter as claimed in claim 5, it is characterised in that described harmonic generation device adopts diclinic rate score indicator or ∑ Delta modulator.
10. a source electrode drive circuit, it is characterised in that include digital analog converter as claimed in any one of claims 1-9 wherein.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008748A (en) * | 1997-09-16 | 1999-12-28 | Sterzer; Fred | Microwave phase logic implementations of an analog-to-digital converter |
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008748A (en) * | 1997-09-16 | 1999-12-28 | Sterzer; Fred | Microwave phase logic implementations of an analog-to-digital converter |
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
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