CN105743504B - Digital analog converter and source electrode drive circuit - Google Patents
Digital analog converter and source electrode drive circuit Download PDFInfo
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- CN105743504B CN105743504B CN201610060024.5A CN201610060024A CN105743504B CN 105743504 B CN105743504 B CN 105743504B CN 201610060024 A CN201610060024 A CN 201610060024A CN 105743504 B CN105743504 B CN 105743504B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
Abstract
In digital analog converter provided by the invention and source electrode drive circuit, harmonic signal is generated by harmonic generation device and the harmonic signal is sampled using sampling unit, and then realize the conversion of digital signal to analog signal, the digital analog converter structure is simple, area occupied can effectively be reduced and reduce power consumption, enable using the digital analog converter source electrode drive circuit be suitable for higher resolution flat-panel monitor.
Description
Technical field
The present invention relates to technical field of flat panel display, in particular to a kind of digital analog converter and source electrode drive circuit.
Background technique
With the development of information-intensive society, demand of the people to display equipment is growing.It is various in order to meet this requirement
Panel display apparatus such as thin film transistor LCD device (TFT-LCD), plasma display device (PDP), organic light emission
Display device (OLED), field emission display device (FED) etc. have all obtained swift and violent development.
Referring to FIG. 1, its structural schematic diagram for the panel display apparatus of the prior art.As shown in Figure 1, existing plate
Display device 10 generally includes source electrode drive circuit 100, gate driving circuit 110, sequential control circuit 120 and display panel
130, the sequential control circuit 120 is for controlling the source electrode drive circuit 100 and gate driving circuit 110, the source electrode
Driving voltage is sent to the display panel 130, the gate driving by data line (not shown) by driving circuit 100
Scanning signal is sent to the display panel 130, the display panel 130 by scan line (not shown) by circuit 110
According to the source electrode drive circuit 100 provide data-signal and the gate driving circuit 110 provide scanning signal come
Show image.
Wherein, the source electrode drive circuit 100 generally includes digital analog converter (DACS), the digital-to-analogue conversion
Device exports analog signal in response to the digital signal that the sequential control circuit 120 provides, and the source electrode drive circuit 100 utilizes
Digital signal is switched to corresponding driving voltage and the driving voltage is provided to display panel by the digital analog converter
130。
However, the volume of the digital analog converter is usually larger, the area occupied accounts for about entire source drive electricity
The 60% of the road gross area, therefore the volume of the chip for carrying source electrode drive circuit is caused not reduce further.
With the development of display technology and electronic science and technology, the resolution ratio of panel display apparatus is continuously improved, at present
Reached full HD standard, it is subsequent also to develop to ultra high-definition standard.But correspondingly, due to monitor resolution raising,
The area occupied of digital analog converter and power consumption are increasing in the source electrode drive circuit 100.For resolution ratio at 10
For above high-resolution panel display apparatus, existing digital analog converter since area occupied and power consumption are excessive,
It can no longer meet the actual demand of product.
Base this, it is excessive how to solve the area occupied of digital analog converter and power consumption in existing source electrode drive circuit
Problem, at those skilled in the art's technical problem urgently to be resolved.
Summary of the invention
The purpose of the present invention is to provide a kind of digital analog converter and source electrode drive circuits, to solve existing source electrode
The area occupied of source electrode drive circuit and the excessive problem of power consumption in driving circuit.
To solve the above problems, the present invention provides a kind of digital analog converter, the digital analog converter includes: number
Word analog converter characterized by comprising clock counter, data register, comparator, harmonic generation device, the first sampling
Holding circuit and the second sample-and-hold circuit；
The control terminal of the control terminal of the data register, the control terminal of comparator and the second sample-and-hold circuit with
First output end of the clock counter connects, and an input terminal of the input terminal of the harmonic generation device and comparator is and institute
The second output terminal connection of clock counter is stated, the input terminal of the data register is for receiving digital signal, the data
The output end of register is connect with another input terminal of the comparator, and the output end of the comparator and first sampling are protected
The control terminal connection of circuit is held, the output end of the harmonic generation device is connect with the input terminal of first sample-and-hold circuit,
The output end of first sample-and-hold circuit is connect with the input terminal of second sample-and-hold circuit.
Optionally, in the digital analog converter, the first output end of the clock counter is for exporting the
One clock signal, the second output terminal of the clock counter is for exporting second clock signal；
The first clock signal that the data register is provided with clock counter according to the digital signal exports deposit
Signal, comparison result output control signal of the comparator according to the deposit signal and second clock signal, the harmonic wave
Generator generates harmonic signal according to the second clock signal.
Optionally, in the digital analog converter, the harmonic generation device uses diclinic rate score indicator or ∑ Δ
Modulator.
Optionally, in the digital analog converter, first sample-and-hold circuit and the second sampling keep electricity
The structure on road is identical.
Correspondingly, the digital analog converter includes clock, meter the present invention also provides a kind of digital analog converter
Number device, data register, comparator, harmonic generation device and sampling unit；
The input terminal of the counter and harmonic wave generator is connect with the second output terminal of the clock, the counter
Output end connect with an input terminal of the comparator, the first output of the control terminal of the data register and the clock
End connection, the input terminal of the data register is for receiving digital signal, the output end of the data register and the ratio
Another input terminal compared with device connects, and the output end of the comparator and harmonic wave generator is connect with the sampling unit.
Optionally, in the digital analog converter, the first output end of the clock is for providing the first clock
Signal, the second output terminal of the clock is for providing second clock signal；
The counter exports clock count signal according to the second clock signal, and the data register is according to
Digital signal and the first clock signal output deposit signal, the comparator is according to the deposit signal and clock count signal
Comparison result output control signal, the harmonic generation device is generated according to the second clock signal and output harmonic wave signal.
Optionally, in the digital analog converter, the sampling unit includes the first sampling channel, the second sampling
The output end of channel and amplifier, first sampling channel and the second sampling channel with the positive side input terminal of the amplifier
Connection, the negative side input terminal of the amplifier are connect with the output end of the amplifier.
Optionally, in the digital analog converter, first sampling channel includes the first change-over switch, first
Clock buffer, the first follower and the first sampling capacitance, second sampling channel include the second change-over switch, second clock
The input terminal of buffer, the second follower and the second sampling capacitance, first change-over switch and the second change-over switch is and institute
State the output end connection of harmonic generation device, the output end of first change-over switch and the first clock buffer input terminal with
And first sampling capacitance first substrate connection, the output end of second change-over switch and the second clock buffer input
The connection of the first substrate of end and the second sampling capacitance, the output end of first clock buffer and second clock buffer are equal
Connect with the positive side input terminal of the amplifier, the input terminal of first follower and the second follower with the comparator
Output end connection, the output end of first follower connect with the control terminal of first change-over switch, described second with
It is connect with the output end of device with the control terminal of second change-over switch.
Optionally, in the digital analog converter, the harmonic generation device uses diclinic rate score indicator or ∑ Δ
Modulator.
Correspondingly, the source electrode drive circuit includes as described above the present invention also provides a kind of source electrode drive circuit
Digital analog converter.
In digital analog converter provided by the invention and source electrode drive circuit, harmonic wave letter is generated by harmonic generation device
Number and the harmonic signal is sampled using sampling unit, and then realize digital signal to analog signal conversion, it is described
Digital analog converter structure is simple, can effectively reduce area occupied and reduce power consumption, so that using the digital simulation
The source electrode drive circuit of converter can be suitable for the flat-panel monitor of higher resolution.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the panel display apparatus of the prior art；
Fig. 2 is the structural schematic diagram of the digital analog converter of the embodiment of the present invention one；
Fig. 3 is the working waveform figure of the digital analog converter of the embodiment of the present invention one；
Fig. 4 is the structural schematic diagram of the digital analog converter of the embodiment of the present invention two.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of digital analog converter proposed by the present invention and source drive electricity
Road is described in further detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It needs to illustrate
, attached drawing is all made of very simplified form and using non-accurate ratio, only conveniently, lucidly to aid in illustrating originally
The purpose of inventive embodiments.
[embodiment one]
Referring to FIG. 2, its structural schematic diagram for the digital analog converter of the embodiment of the present invention one.As shown in Fig. 2, institute
State digital analog converter 200 include: clock counter 210, data register 220, comparator 230, harmonic generation device 240,
First sample-and-hold circuit 250 and the second sample-and-hold circuit 260；The control terminal of the data register 220, comparator 230
Control terminal C and the second sample-and-hold circuit 260 control terminal with the first output end of the clock counter 210 connect
Connect, the second input terminal B of the input terminal of the harmonic generation device 240 and comparator 230 with the clock counter 210
The connection of two output ends；The output end of the data register 220 is connect with the first input end A of the comparator 230, the ratio
It is connect compared with the output end of device 230 with the control terminal of first sample-and-hold circuit 250, the output of the harmonic generation device 240
End connect with the input terminal of first sample-and-hold circuit 250, the output end of first sample-and-hold circuit 250 with it is described
The input terminal of second sample-and-hold circuit 260 connects.
Specifically, the clock counter 210 includes the first output end and second output terminal, the clock counter 210
The first clock signal clk is exported by first output end, second clock signal S2 is exported by the second output terminal.Its
In, first clock signal clk is exported to the data register 220, comparator 230 and the second sample-and-hold circuit 260
Control terminal, the second clock signal S2 exports second to the input terminal of the harmonic generation device 240 and comparator 230
Input terminal B.
The data register 220 is for receiving digital signal S1, and first provided according to the clock counter 210
Clock signal clk output deposit signal S3.
The first input end A of the comparator 230 is connected with the output end of the data register 220, for receiving
State the deposit signal S3 that data register 220 is exported, the second input terminal B and the clock counter of the comparator 230
210 second output terminal is connected, the second clock signal S2 exported for receiving the clock counter 210, the comparison
230 output end of device is connect with the control terminal of first sample-and-hold circuit 250, is used for first sample-and-hold circuit
250 output control signal S4.
The second clock signal S2 that the harmonic generation device 240 is provided for receiving the clock counter 210, and according to
The second clock signal S2 generates harmonic signal S5.
In the present embodiment, diclinic rate score indicator or ∑ Delta modulator is can be used in the harmonic generation device 240.
First sample-and-hold circuit 250 and the series connection of the second sample-and-hold circuit 260, for raw to the harmonic wave respectively
The harmonic signal S5 of 240 generations of growing up to be a useful person is sampled and is exported analog signal.Wherein, first sample-and-hold circuit 250
Input terminal is connected with the output end of the harmonic generation device 240, the harmonic signal exported for receiving the harmonic generation device 240
S5.The control terminal of first sample-and-hold circuit 250 is connected with the output end of the comparator 230, for receiving the ratio
Compared with the control signal S4 of the output of device 230.The output end of first sample-and-hold circuit 250 and second sampling keep electricity
The input terminal on road 260 is connected, for exporting the sampled signal S6 after sampling for the first time to second sample-and-hold circuit 260.
The input terminal of second sample-and-hold circuit 260 is connected with the output end of first sample-and-hold circuit 250, for receiving
The sampled signal S6 that first sample-and-hold circuit 250 exports.The control terminal of second sample-and-hold circuit 260 with it is described
First output end of clock counter 210 is connected, the first clock signal clk provided for receiving the clock counter 210.
The output end of second sample-and-hold circuit 260 is used to export the analog signal S7 after sampling second.
Preferably, the structure of first sample-and-hold circuit and the second sample-and-hold circuit is identical.
Referring to FIG. 3, its working waveform figure for the digital analog converter of the embodiment of the present invention one.Such as 2 and Fig. 3 institute
Show, the clock counter 210 exports the first clock signal clk and second clock signal S2, first clock signal clk
A cycle correspond to a digital signal S1, a cycle of the second clock signal S2 correspond to set of number signal S1 (0,
0,1,2,3,4,5,6,7 or 7,7,6,5,4,3,2,1,0), the comparator 230 is to its first input end A and the second input terminal B
The received deposit signal S3 of institute is compared with second clock signal S2 and exports control signal S4 according to comparison result, when described
The control signal S4 for depositing the output end output of the comparator 230 when signal S3 and second clock signal S2 unequal is invalid,
When the deposit signal S3 is equal with second clock signal S2, the control signal S4 of the output end output of the comparator 230 has
Effect, the harmonic signal that first sample-and-hold circuit 250 exports the harmonic generation device 240 according to the control signal S4
S5 is sampled, and second sample-and-hold circuit 260 keeps electricity to first sampling according to first clock signal clk
The sampled signal S6 that road 250 exports is sampled again, final output analog signal S7.
In the present embodiment, it is single that sampling is formed by first sample-and-hold circuit 250 and the second sample-and-hold circuit 260
Member, the harmonic signal S5 generated to the harmonic generation device 240 are sampled, and then export analog signal S7.
Digital analog converter 200 provided in this embodiment realizes digital signal to analog signal using harmonic generation device
Conversion, compared with traditional digital analog converter, structure is more simple, and power consumption is lower.
[embodiment two]
Referring to FIG. 4, its structural schematic diagram for the digital analog converter of the embodiment of the present invention two.As shown in figure 4, institute
State digital analog converter 300 include: clock (not shown), it is counter 310, data register 320, comparator 330, humorous
Wave generator 340 and sampling unit 350；The input terminal of the counter 310 and harmonic wave generator 340 with the clock
The connection of two output ends, the output end of the counter 310 are connect with an input terminal of the comparator 330, the data register
The control terminal of device 320 is connect with the first output end of the clock, and the input terminal of the data register 320 is for receiving number
Signal S1, the output end of the data register 320 are connect with another input terminal of the comparator 330, the comparator 330
It is connect with the sampling unit 350 with the output end of harmonic wave generator 340.
Specifically, the first output end and second output terminal of the clock for provide respectively the first clock signal HCLK and
Second clock signal RCLK.Wherein, the first clock signal HCLK is exported to the control terminal of the data register 320, institute
Second clock signal RCLK is stated to be exported respectively to the input terminal of the harmonic generation device 340 and counter 310.The counter
310 export clock count signal according to the second clock signal RCLK.The data register 320 is for receiving digital signal
S1, and the first clock signal HCLK output deposit signal that S1 and clock counter 310 provide according to the digital signal.It is described
Comparator 330 controls signal according to the comparison result output of the deposit signal and clock count signal.The harmonic generation device
340 generate simultaneously output harmonic wave signal according to the second clock signal RCLK.
In the present embodiment, diclinic rate score indicator or ∑ Delta modulator is can be used in the harmonic generation device 340.
The sampling unit 350 includes the first sampling channel, the second sampling channel and amplifier 357, first sampling
Channel is connect with the positive side input terminal of the amplifier 357 with the output end of the second sampling channel, and the amplifier 357 is born
Side input terminal is connect with the output end of the amplifier 357.
Wherein, first sampling channel is followed including the first change-over switch 351a, the first clock buffer 353a, first
Device 355a and the first sampling capacitance C1, second sampling channel include the second change-over switch 351b, second clock buffer
353b, the second follower 355b and the second sampling capacitance C2's, the first change-over switch 351a and the second change-over switch 351b
Input terminal is connect with the output end of the harmonic generation device 340, the output end of the first change-over switch 351a and described the
The connection of the first substrate of one clock buffer 353a input terminal and the first sampling capacitance C1, the second change-over switch 351b's
Output end is connect with the first substrate of the second clock buffer 353b input terminal and the second sampling capacitance C2, and described first
The output end of clock buffer 353a and second clock buffer 353b are connect with the positive side input terminal of the amplifier 357,
The input terminal of the first follower 355a and the second follower 355b are connect with the output end of the comparator 330, described
The output end of first follower 355a is connect with the control terminal of the first change-over switch 351a, the second follower 355b's
Output end is connect with the control terminal of the second change-over switch 351b.
As shown in figure 4, what the first follower 355a was exported according to the first reference signal PH and the comparator 330
It controls signal and exports first switch signal to the first change-over switch 351a, the second follower 355b is according to the second benchmark
The control signal that signal NH and the comparator 330 are exported exports second switch signal to the second change-over switch 351b,
The first clock buffer 353a exports the first buffering signals, institute according to the first switch signal and the second reference signal NH
It states second clock buffer 353b and the second buffering signals is exported according to the second switch signal and the first reference signal PH, it is described
It is exported after carrying out signal amplification by the amplifier 357 after first buffering signals and the superposition of the second buffering signals.
The harmonic signal that the sampling unit 350 generates the harmonic generation device 340 samples, and then exports simulation
Signal.The difference between this embodiment and the first embodiment lies in the structure difference of the sampling unit sampled to harmonic signal.This reality
It applies in example, the sampling unit 350 is by the first change-over switch 351a, the second change-over switch 351b, the first clock buffer
353a, second clock buffer 353b, the first follower 355a, the second follower 355b, the first sampling capacitance C1, the second sampling
Capacitor C2 and amplifier 357 form.And the sampling unit of embodiment one is taken by first sample-and-hold circuit 250 and second
What sample holding circuit 260 formed.
In addition, in the present embodiment, the clock and counter 310 be it is independent, realize clock and tally function respectively,
The second clock signal RCLK that the clock provides is counted by counter 310 and exports clock count signal.And implement
As a whole, itself has clock and tally function, passes through the clock counter clock counter 210 in example one
210 directly export second clock signal S2, and the second clock signal S2 is equivalent to the clock count signal.
[embodiment three]
Correspondingly, the source electrode drive circuit includes as described above the present invention also provides a kind of source electrode drive circuit
Digital analog converter.It specifically please refers to above, details are not described herein again.
Source electrode drive circuit provided in this embodiment replaces traditional digital simulation using novel digital analog converter
Converter is conducive to further reduce the volume and power consumption for carrying the chip of the source electrode drive circuit.From another angle
For, higher resolution ratio, such as 10 or more can be realized on existing chip area using the source electrode drive circuit
High-resolution.
To sum up, it in digital analog converter provided by the invention and source electrode drive circuit, is generated by harmonic generation device
Harmonic signal simultaneously samples the harmonic signal using sampling unit, and then realizes that digital signal turns to analog signal
It changes, the digital analog converter structure is simple, can effectively reduce area occupied and reduce power consumption, so that using the number
The source electrode drive circuit of word analog converter can be suitable for the flat-panel monitor of higher resolution.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of digital analog converter characterized by comprising clock counter, data register, comparator, harmonic wave are raw
It grows up to be a useful person, the first sample-and-hold circuit and the second sample-and-hold circuit；
The control terminal of the control terminal of the data register, the control terminal of comparator and the second sample-and-hold circuit with it is described
First output end of clock counter connects, an input terminal of the input terminal of the harmonic generation device and comparator with it is described when
The second output terminal of clock counter connects, and the input terminal of the data register is for receiving digital signal, the data register
The output end of device is connect with another input terminal of the comparator, and the output end of the comparator and first sampling keep electricity
The control terminal on road connects, and the output end of the harmonic generation device is connect with the input terminal of first sample-and-hold circuit, described
The output end of first sample-and-hold circuit is connect with the input terminal of second sample-and-hold circuit.
2. digital analog converter as described in claim 1, which is characterized in that the first output end of the clock counter is used
In exporting the first clock signal, the second output terminal of the clock counter is for exporting second clock signal；
The first clock signal output deposit signal that the data register is provided with clock counter according to the digital signal,
Comparison result output control signal of the comparator according to the deposit signal and second clock signal, the harmonic generation device
Harmonic signal is generated according to the second clock signal.
3. digital analog converter as described in claim 1, which is characterized in that the harmonic generation device uses dual slope integrating
Device or ∑ Delta modulator.
4. digital analog converter as described in claim 1, which is characterized in that first sample-and-hold circuit and second takes
The structure of sample holding circuit is identical.
5. a kind of digital analog converter characterized by comprising clock, counter, data register, comparator, harmonic wave are raw
It grows up to be a useful person and sampling unit；
The input terminal of the counter and harmonic wave generator is connect with the second output terminal of the clock, the counter it is defeated
Outlet is connect with an input terminal of the comparator, and the first output end of the control terminal of the data register and the clock connects
It connects, the input terminal of the data register is for receiving digital signal, the output end of the data register and the comparator
The connection of another input terminal, the output end of the comparator and harmonic wave generator connect with the sampling unit.
6. digital analog converter as claimed in claim 5, which is characterized in that the first output end of the clock is for providing
First clock signal, the second output terminal of the clock is for providing second clock signal；
The counter exports clock count signal according to the second clock signal, and the data register is according to the number
Signal and the first clock signal output deposit signal, the comparator is according to the deposit signal compared with clock count signal
As a result output control signal, the harmonic generation device is generated according to the second clock signal and output harmonic wave signal.
7. digital analog converter as claimed in claim 5, which is characterized in that the sampling unit includes that the first sampling is logical
The output end of road, the second sampling channel and amplifier, first sampling channel and the second sampling channel with the amplifier
The connection of positive side input terminal, the negative side input terminal of the amplifier connect with the output end of the amplifier.
8. digital analog converter as claimed in claim 7, which is characterized in that first sampling channel includes the first conversion
Switch, the first clock buffer, the first follower and the first sampling capacitance, second sampling channel include that the second conversion is opened
Pass, second clock buffer, the second follower and the second sampling capacitance, first change-over switch and the second change-over switch it is defeated
Enter end to connect with the output end of the harmonic generation device, the output end of first change-over switch and first clock buffer
The connection of the first substrate of device input terminal and the first sampling capacitance, the output end and the second clock of second change-over switch
The connection of the first substrate of buffer input and the second sampling capacitance, first clock buffer and second clock buffer
Output end connect with the positive side input terminal of the amplifier, the input terminal of first follower and the second follower with
The output end of the comparator connects, and the output end of first follower is connect with the control terminal of first change-over switch,
The output end of second follower is connect with the control terminal of second change-over switch.
9. digital analog converter as claimed in claim 5, which is characterized in that the harmonic generation device uses dual slope integrating
Device or ∑ Delta modulator.
10. a kind of source electrode drive circuit, which is characterized in that turn including digital simulation as claimed in any one of claims 1-9 wherein
Parallel operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610060024.5A CN105743504B (en) | 2016-01-28 | 2016-01-28 | Digital analog converter and source electrode drive circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610060024.5A CN105743504B (en) | 2016-01-28 | 2016-01-28 | Digital analog converter and source electrode drive circuit |
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| CN105743504B true CN105743504B (en) | 2019-01-18 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008748A (en) * | 1997-09-16 | 1999-12-28 | Sterzer; Fred | Microwave phase logic implementations of an analog-to-digital converter |
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
-
2016
- 2016-01-28 CN CN201610060024.5A patent/CN105743504B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008748A (en) * | 1997-09-16 | 1999-12-28 | Sterzer; Fred | Microwave phase logic implementations of an analog-to-digital converter |
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
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| Publication number | Publication date |
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| CN105743504A (en) | 2016-07-06 |
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Effective date of registration: 20201208 Address after: No.146 Tianying Road, high tech Zone, Chengdu, Sichuan Province Patentee after: Chengdu CHENXIAN photoelectric Co.,Ltd. Address before: 215300, 188, Feng Feng Road, Kunshan hi tech Zone, Kunshan, Suzhou, Jiangsu, Jiangsu Patentee before: Kunshan New Flat Panel Display Technology Center Co.,Ltd. Patentee before: KunShan Go-Visionox Opto-Electronics Co.,Ltd. |
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