CN1705236A - Analog digital converter having a function of dynamic adjustment corresponding to the state of the system - Google Patents
Analog digital converter having a function of dynamic adjustment corresponding to the state of the system Download PDFInfo
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- CN1705236A CN1705236A CN 200510074078 CN200510074078A CN1705236A CN 1705236 A CN1705236 A CN 1705236A CN 200510074078 CN200510074078 CN 200510074078 CN 200510074078 A CN200510074078 A CN 200510074078A CN 1705236 A CN1705236 A CN 1705236A
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Abstract
A DSP calculates time integration of the light amount received by a CCD, using an input image. Determination is made regarding whether or not the light amount is equal to or smaller than a predetermined threshold. In a case that the light amount is equal to or smaller than the predetermined threshold, the DSP outputs a control signal to an AD converter for operation in the 8-bit mode. In a case that the light amount is greater than the threshold, the DSP outputs a control signal to the AD converter for operation in the 10-bit mode. The AD converter has a function of dynamic adjustment of conversion bits according to control from the DSP.
Description
Technical field
The present invention relates to analog-digital converter, use its signal processing system and camera head, relate in particular to the analog-digital converter, the signal processing system of using it and the camera head that are loaded on system LSI (Large Scale Integration) etc.
Background technology
In recent years, the trend that presents Load System LSI on the portable machines such as digital camera.System LSI is to use a plurality of unifunctional LSI to come planing machine, and distribution is simplified, and can reduce the area occupied of LSI.Therefore, also help the miniaturization of machine.
[patent documentation 1] spy opens the 2001-78088 communique
The system loading shown in Figure 1 of patent documentation 1 has AD (Analog Digital) transducer 3.The specification of this AD converter 3 is fixed.Therefore, even, need the AD converter of 10 specifications though for example be generally in 8 also passable systems in the precision of 10 of temporary needs.
8 with 10 resolution under difference appears owing to consume electric power, so the AD converter of 10 specifications is compared with the AD converter of 8 specifications, consume electric power and become greatly.Therefore, the AD converter of the system of temporary needs high-precision signal processing is used useless consumption electric power when moving usually.
Summary of the invention
The present invention is in view of above-mentioned condition, and its purpose is to provide a kind of can reduce the analog-digital converter of useless consumption electric power, the signal processing system of using it and camera head.
In order to solve above-mentioned problem, the analog-digital converter of certain form of the present invention is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, wherein, according to the state of the system of being loaded, circuit is constituted or the circuit constant dynamic change.So-called " state of system " for example can comprise the state of the high-precision signal processing of requirement, not need the state of high-precision signal processing etc.
According to this form, can change with circuit formation or circuit constant that compliance with system requires, can prevent at system requirements, under the state of harsh specification requirement (over spec), change, use useless consumption electric power.
Other forms of the present invention also are analog-digital converters.This analog-digital converter be a kind of be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, wherein,, make conversion figure place dynamic change according to the state of the system of being loaded.
According to this form, can change with the figure place that compliance with system requires, can prevent to change, use useless consumption electric power with surpassing the figure place that requires.
Another form of the present invention also is an analog-digital converter.This analog-digital converter is a kind of analog-digital converter of elementary cell with level, and this elementary cell comprises: with the input analog signal conversion of self level analog-to-digital conversion circuit for the digital value of regulation figure place; The output of analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From will from the output analog signal of the amplifying circuit that the input analog signal of level is amplified, deducting the subtraction circuit of the output of D/A conversion circuit from the input analog signal of level or from magnification ratio with regulation; And by this elementary cell is used 1 time or reused, thereby the digital signal that obtains stipulating, wherein, according to the state of the system of being loaded, change offers the operating frequency of at least one grade, so that the dynamic change of conversion figure place.
" level " can be 1 also can be a plurality of.In addition, any one " level " can feed back to the output of oneself input of oneself, and will importing analog signal, to be divided into multiple conversions be digital value.Be provided with under the situation of feedback stage, owing to can change the conversion figure place according to its rotating speed, so can in identical circuit area, make the figure place dynamic change.Thus, irrelevant with the conversion figure place, can make the optimization circuits that does not have redundance.
Another form of the present invention is a signal processing system.This signal processing system is that be the signal processing system of analog-digital converter of the digital signal of regulation figure place a kind of comprising analog signal conversion, wherein possesses the control part of the conversion figure place dynamic change that makes analog-digital converter.Control part changes the conversion figure place by the ratio of operating frequency with the sample frequency of change analog-digital converter." control part " also can be according to the state of system, make the dynamic change of conversion figure place.
According to this form, owing to can reduce the useless consumption electric power of analog-digital converter, so can reduce the consumption electric power of whole system.
Control part can pass through the ratio of operating frequency with the sample frequency of change analog-digital converter, and the conversion figure place is changed.This changes figure place than changing owing to change, thus need not to be provided with unnecessary circuit part, therefore can be with the circuit area optimization.In addition, control part also can stop to supply with to the electric power of the part of the circuit that constitutes analog-digital converter, and the conversion figure place is changed.Thus, can reduce consumption electric power.
Control part can change the conversion figure place of analog-digital converter according to gain adjustment, also can the conversion figure place of analog-digital converter be changed according to side-play amount (offset) adjustment.Can comprise the gain adjustment of the variable amplifier that is arranged on the analog-digital converter prime in " gain is adjusted ".For example comprise the adjustment of the DC side-play amount composition that is input to the analog input signal in the analog-digital converter of received signal of converting in direct conversion (direct conversion) mode etc. in " side-play amount adjustment ".
Analog-digital converter can comprise with from the level output feed back to from the level input the level.Control part can make the operating frequency dynamic change that offers level.The operating frequency of the level by making feedback changes, thereby can easily change the rotating speed of this grade, and the conversion figure place is changed.
A form more of the present invention is a camera head.This device has: the be taken image pickup part of body of shooting; Amplify from the amplifier of the analog signal of image pickup part output with the gain of regulation; To be the analog-digital converter of the digital signal of regulation figure place from the analog signal conversion of amplifier output; With state, make the control part of the conversion figure place dynamic change of analog-digital converter according to system.Control part also can change the conversion figure place according to the Amplifier Gain adjustment.
According to this form, owing to can reduce the useless consumption electric power of analog converter, so can reduce the consumption electric power of whole camera head.
Other forms of the present invention are analog-digital converters.This analog-digital converter be a kind of be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, wherein the state according to the system of being loaded makes the current sinking dynamic change.
According to this form,, thereby can prevent to use useless consumption electric power by the current sinking action that requires with compliance with system.
Another form of the present invention or analog-digital converter.This analog-digital converter has the elementary cell of level, and this elementary cell comprises: with the input analog signal conversion of own level is the analog-to-digital conversion circuit of the digital value of regulation figure place; The output of analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From will from the output analog signal of the amplifying circuit that the input analog signal of level is amplified, deducting the subtraction circuit of the output of D/A conversion circuit from the input analog signal of level or from magnification ratio with regulation; And by use 1 time or repeated use, thereby the digital signal that obtains stipulating wherein, according to the state of the system of being loaded, makes the bias current dynamic change of the amplifying circuit that is contained at least one grade.
According to this form,, thereby can prevent the situation of the consumption electric power that the use of analog-digital converter of pipeline-type or circular form etc. is useless by the current sinking action that requires with compliance with system.
Another form of the present invention is a signal processing system.This signal processing system is that be the signal processing system of analog-digital converter of the digital signal of regulation figure place a kind of comprising analog signal conversion, comprising the control part of the current sinking dynamic change of the amplifying circuit that analog-digital converter is comprised.Control part can make the transistorized bias voltage dynamic change of moving as current source in amplifying circuit inside according to the signal of detection system state.
According to this form, owing to can reduce the useless consumption electric power of analog-digital converter, so can reduce the consumption electric power of whole system.
Other forms of the present invention are analog-digital converters.This analog-digital converter be a kind of be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, wherein make the circuit of the amplifying circuit that analog-digital converter comprises constitute dynamic change according to the state of the system of being loaded." amplifying circuit " can be made of differential amplifier circuit, also can make the transistorized connection form dynamic change of this differential amplifier circuit.
According to this form, the circuit by the amplifying circuit that requires with compliance with system constitutes and moves, thereby can prevent to use useless consumption electric power.
Another form of the present invention or analog-digital converter, this analog-digital converter have the elementary cell of level, and this elementary cell comprises: with the input analog signal conversion of own level is the analog-to-digital conversion circuit of the digital value of regulation figure place; The output of analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From input analog signal from level, or from will from the output analog signal of the amplifying circuit that the input analog signal of level is amplified, deducting the subtraction circuit of the output of D/A conversion circuit with the magnification ratio of stipulating; And by using 1 time or reuse, thereby the digital signal that obtains stipulating wherein, according to the state of the system of being loaded, constitutes the circuit of the amplifying circuit that at least one grade comprise and changes.
According to this form, the circuit by the amplifying circuit that requires with compliance with system constitutes and moves, thereby the analog-digital converter that can prevent pipeline-type or circular form etc. uses useless consumption electric power.
Another form of the present invention is a signal processing system.This signal processing system is that be the signal processing system of analog-digital converter of the digital signal of regulation figure place a kind of comprising analog signal conversion, constitutes the control part of dynamic change comprising the circuit of the amplifying circuit that analog-digital converter is comprised.Control part generates the signal of the circuit formation of decision amplifying circuit according to the signal of detection system state.
According to this form, owing to can reduce the useless consumption electric power of analog-digital converter, so can reduce the consumption electric power of whole system.
A form more of the present invention is an analog-digital converter.This analog-digital converter be a kind of be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, wherein make the capacitance dynamic change of the switching capacity type amplifying circuit that analog-digital converter comprises according to the state of the system of being loaded.
According to this form,, thereby can prevent to use useless consumption electric power by the capacitance action of the switching capacity type amplifying circuit that requires with compliance with system.
Other forms of the present invention also are analog-digital converters.This analog-digital converter has the elementary cell of level, and this elementary cell comprises: with the input analog signal conversion of own level is the analog-to-digital conversion circuit of the digital value of regulation figure place; The output of analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From input analog signal from level, or from will from the output analog signal of the amplifying circuit that the input analog signal of level is amplified, deducting the subtraction circuit of the output of D/A conversion circuit with the magnification ratio of stipulating; And by using 1 time or reuse, thereby the digital signal that obtains stipulating wherein, according to the state of the system of being loaded, makes the capacitance dynamic change of the switching capacity type amplifying circuit that at least one grade comprise.
According to this form, by the capacitance action of the switching capacity type amplifying circuit that requires with compliance with system, thereby the analog-digital converter that can prevent pipeline-type or circular form etc. uses useless consumption electric power.
Another form of the present invention is a signal processing system.This signal processing system is that be the signal processing system of analog-digital converter of the digital signal of regulation figure place a kind of comprising analog signal conversion, comprising the control part of the capacitance dynamic change of the switching capacity type amplifying circuit that analog-digital converter is comprised.Control part generates the signal of the capacitance of determine switch capacitor type amplifying circuit according to the signal of detection system state.
According to this form, owing to can reduce the useless consumption electric power of analog-digital converter, so can reduce the consumption electric power of whole system.
A form more of the present invention is an analog-digital converter.This analog-digital converter be a kind of be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, wherein the state according to the system of being loaded makes the operating frequency dynamic change.
According to this form,, thereby can prevent to use useless consumption electric power by the operating frequency action that requires with compliance with system.
And, in method, device, system, program, the combination in any that has write down the above inscape of phase double replacement between the recording medium etc. of program or the form of inscape of the present invention or performance, also be effective as form of the present invention.
Description of drawings
Fig. 1 is the figure of the basic comprising of the general image-signal processing system of expression.
Fig. 2 is the figure of basic comprising of the signal processing system of expression the 1st execution mode.
Fig. 3 is the figure of the AD converter of expression the 1st embodiment.
Fig. 4 is the time diagram of the course of action when being illustrated in 10 of conversions in the AD converter of Fig. 3.
Fig. 5 is the time diagram of the course of action when being illustrated in 8 of conversions in the AD converter 3 of Fig. 3.
Fig. 6 is the figure of the AD converter among expression the 2nd embodiment.
Fig. 7 is the flow chart of the action of the signal processing system in expression the 1st execution mode.
Fig. 8 is the figure of the basic comprising of the signal processing system in expression the 2nd execution mode.
Fig. 9 is the flow chart of the action of the signal processing system in expression the 2nd execution mode.
Figure 10 is the figure of the example adjusted of the scope of expression AD converter.
Figure 11 is the figure of the AD converter among expression the 3rd embodiment.
Figure 12 is the figure of the AD converter among expression the 4th embodiment.
Figure 13 is the figure that expression can change the 1st example that the circuit of the bias current of amplifying circuit constitutes.
Figure 14 is the figure that expression can change the 2nd example that the circuit of the bias current of amplifying circuit constitutes.
Figure 15 is the figure that expression can change the 3rd example that the circuit of the bias current of amplifying circuit constitutes.
Figure 16 is the figure of the AD converter among expression the 5th embodiment.
Figure 17 is the figure of the AD converter among expression the 6th embodiment.
Figure 18 is the figure that expression can change the example that the circuit of amplifying circuit constitutes.
Figure 19 is the figure of the AD converter among expression the 7th embodiment.
Figure 20 is the figure of the AD converter among expression the 8th embodiment.
Figure 21 is the figure of example that expression can change the capacitance of amplifying circuit.
Figure 22 is the AD converter of expression among the 9th embodiment and the figure of ADC control master clock (masterclock) generative circuit.
Figure 23 is the AD converter of expression among the 10th embodiment and the figure of ADC control master clock generative circuit.
Embodiment
(the 1st execution mode)
The 1st execution mode is the example that signal processing system of the present invention is applicable to the processing of picture signal.Fig. 1 represents the basic comprising of general image-signal processing system.CCD (Charge CoupledDevice) 12 is taken into from the light of the body that is taken and is converted to the signal of telecommunication, and is entered in the image processing usefulness system LSI 10 of singualtion.In this system LSI 10, be built-in with CDS (CorrelatedDouble Sampling) 14, variable amplifier 16, AD converter 20, DSP (Digital SignalProcessor) 18.
CDS14 removes noise by carrying out subtraction from the signal of the signal in each picture element signal of CCD12, during the picture signal of having sampled and the base period of having sampled.Variable amplifier 16 is according to by from the FEEDBACK CONTROL of DSP18 and the gain of appointment, the output signal of amplifying CDS14.That is, receive feedback signal, compensate the output signal of CDS14 in the mode in the prescribed limit of being accommodated in from DSP18.Specifically, in the light quantity of shining on the CCD12 is under the situation of dark image less than defined threshold, because the electron number after the opto-electronic conversion is few, full-scale (fullscale) of the output signal of CCD12 is also narrow, so variable amplifier 16 amplifies this output signal with high-gain.
Fig. 2 is the basic comprising of the signal processing system of expression the 1st execution mode.As mentioned above, the electron number of AD converter 20 conversions is few under the situation of dark image.Therefore, desire to amplify as if variable amplifier 16, even then AD converter 20 also is useless with the level exploded view image signal thinner than unit electronics level with high a little gain.Therefore, shown in the AD converter 20 of Fig. 1,, then become the signal that decomposes dark image if resolution is fixed superfluously.
The formation that the resolution that makes AD converter 20 is promptly changed the formation of figure place dynamic change has been added by the system of Fig. 2 in the system of Fig. 1.DSP18 dynamically controls the conversion figure place of AD converter 20 according to the dynamically gain of the variable amplifier 16 of control.That is, because the gain of variable amplifier 16 is when being the signal of the dark image of input when high, so be controlled to be the figure place of lacking than common conversion figure place.
Fig. 3 represents the AD converter 20 among the 1st embodiment.The 1st embodiment is: conversion is 4 in the prime 30 of acyclic type, and by 22 ground conversions, level 50 rotations in back by 2 output or 3 output, thereby add up to the example of 8 of outputs or 10 s' AD converter 20 in the back level 50 of circular form.The operating frequency of back level 50 becomes sample frequency * output number of times.For example, sample frequency is 20[MHz] time operating frequency, the time be 40[MHz 2 output], when 3 output, be 60[MHz].
In this AD converter 20, at first prime 30 is described.Input analog signal Vin is imported in the 1st amplifying circuit 32 and the 1AD change-over circuit 34.1AD change-over circuit 34 is flicker types, and its resolution is that the conversion figure place is 4.1AD change-over circuit 34 is a digital value with the analog signal conversion of being imported, and takes out high-order 4, outputs to encoder 70 and 1DA change-over circuit 36.1DA change-over circuit 36 will be converted to the analogue value by the digital value that 1AD change-over circuit 34 was changed.32 pairs of analog signal samplings of being imported of the 1st amplifying circuit keep outputing to the 1st subtraction circuit 38 after specified time limit.The 1st amplifying circuit 32 is amplified analog signal and playing a role as sampling hold circuit not.The 1st subtraction circuit 38 deducts the output of 1DA change-over circuit 36 from the output of the 1st amplifying circuit 32.
The 2nd amplifying circuit 40 is enlarged into 2 times with the output of the 1st subtraction circuit 38.Be set at by the reference voltage that will supply to the comparator of 2AD change-over circuit 54 comparator that supplies to 1AD change-over circuit 34 reference voltage 1/2, thereby can need 4 times place to drop to 2 times the magnification ratio of the 2nd amplifying circuit 40.And the 1st subtraction circuit 38 and the 2nd amplifying circuit 40 can be the 1st one-piece type subtraction amplification circuits 42.Thus, can simplify circuit.
Then, back level 50 is described.The 1st switch SW 1 and the 2nd switch SW 2 are alternately to connect the switch of disconnection.Under the state that the 1st switch SW 1 is connected, the 2nd switch SW 2 disconnects, be input to the 3rd amplifying circuit 52 and the 2AD change-over circuit 54 through the analog signal of the 1st switch SW 1 from prime 30 inputs.2AD change-over circuit 54 also is a flicker type, and the figure place that its resolution promptly comprises 1 of redundancy is 3.2AD change-over circuit 54 is a digital value with the analog signal conversion of being imported, and outputs in encoder 70 and the 2DA change-over circuit 56.2DA change-over circuit 56 will be converted to the analogue value by the digital value that the 2AD change-over circuit was changed.
The 3rd amplifying circuit 52 is enlarged into 2 times with the analog signal of being imported, and outputs to the 2nd subtraction circuit 58.The 2nd subtraction circuit 58 deducts the output of 2DA change-over circuit 56 from the output of the 3rd amplifying circuit 52, and outputs to the 4th amplifying circuit 60.The output of 2DA change-over circuit 56 is enlarged into 2 times in fact.
At this, the method that the output with 2DA change-over circuit 56 is enlarged into 2 times simply describes.Supply with hot side reference voltage V RT and low potential side reference voltage V RB to 2AD change-over circuit 54 and 2DA change-over circuit 56.2AD change-over circuit 54, utilizing with hot side reference voltage V RT and low potential side reference voltage V RB is the reference voltage range that the basis generates, and generates reference voltage.When the DA conversion of carrying out the capacitor array mode, 2DA change-over circuit 56 is by according to from the control of 2AD change-over circuit 54, optionally supply with accurate voltage VRT of current potential side group and low potential side reference voltage V RB to not shown set a plurality of electric capacity, thereby can obtain output voltage.Like this, the reference voltage range of general 2DA change-over circuit 56 serves as that the basis generates with hot side reference voltage V RT and low potential side reference voltage V RB also.At this moment, in order to carry out 2 times of amplifications, as long as the ratio of the reference voltage range of 2AD change-over circuit 54 and the reference voltage range of 2DA change-over circuit 56 is set at 1: 2.For example, carry out the input of the reference voltage of 2AD change-over circuit 54 individually, the output as if with differential formation 2DA change-over circuit 56 then can be set at 1: 2.
The 4th amplifying circuit 60 is enlarged into 2 times with the output of the 2nd subtraction circuit 58.In this stage, to the state transition that the 1st switch SW 1 disconnects, the 2nd switch SW 2 is connected.The analog signal that is exaggerated in the 4th amplifying circuit 60 is through the 2nd switch SW 2 and to the 3rd amplifying circuit 52 and 2AD change-over circuit 54 feedbacks.Below repeat above-mentioned processing.At this, remove redundant digit from 2AD change-over circuit 54, with the rotation of 2 digital values and when exporting 2 times, in back level 50, becoming 4 outputs, under the situation of 3 outputs, become 6 outputs.Therefore, prime 30 and back level 50 add up to 8 of outputs or 10 s' digital value.
Fig. 4 is the time diagram of the course of action when being illustrated in 10 of conversions in the AD converter 20 of Fig. 3.Below, begin to illustrate in order from the high position of figure.3 signal waveforms are represented the 1st clock signal clk the 1, the 2nd clock signal clk 2 and switching signal CLKSW.These are generated the clock signal of various frequencies with respect to the fundamental clock that the not shown timing generator (timing generator) by system generates by not shown frequency divider or multiplier.
The action of the 1st clock signal clk 1 control the 1st amplifying circuit the 32, the 2nd amplifying circuit 40,1AD change-over circuit 34 and 1DA change-over circuit 36.The action of the 2nd clock signal clk 2 controls the 3rd amplifying circuit the 52, the 4th amplifying circuit 60,2AD change-over circuit 54 and 2DA change-over circuit 56.The connection that switching signal CLKSW carries out the 1st switch SW 1 and the 2nd switch SW 2 disconnects control.
The frequency of the 2nd clock signal clk 2 is 3 times of frequency of the 1st clock signal clk 1.The 1st clock signal clk 1 can generate the 2nd clock signal clk 2 frequency divisions with frequency divider basically.In addition, the 2nd clock signal clk 2 basically can be with PLL etc. with 1 multiplication of the 1st clock signal clk and generate.Because the frequency of the 2nd clock signal clk 2 is 3 times of frequency of the 1st clock signal clk 1, so the speed of conversion processing of back grades 50 also is 3 times of speed of conversion processing of prime 30.Because the precision of simulation process such as subtraction in the more high-order conversion process or amplification is big to the conversion accuracy influence of integral body, so requirement resembles high precision the prime 30 of taking on these.Therefore, in the formation of this AD converter 20, do not require that the back level 50 that resembles processing accuracy high the prime 30 can be faster than the processing speed of prime 30 post with its speed of conversion processing.
The 1st amplifying circuit 32 and 1AD change-over circuit 34 is at the rising edge sampling input analog signal Vin of the 1st clock signal clk 1.The 1st amplifying circuit 32 keeps the analog signal of sample during for Hi at the 1st clock signal clk 1, carries out automatic zero set at the 1st clock signal clk 1 during for Lo and moves.The analog signal that the 2nd amplifying circuit 40 is imported in the trailing edge sampling of the 1st clock signal clk 1.Amplify the analog signal of sample during for Lo at the 1st clock signal clk 1, and output to the 3rd amplifying circuit 52 and 2AD change-over circuit 54, carry out automatic zero set at the 1st clock signal clk 1 during for Hi and move.In addition, adopt under the situation of the 1st subtraction amplification circuit 42, when the 1st clock signal clk 1 is Lo, the analog signal of sampling is carried out subtraction and amplify replacing the 2nd amplifying circuit 40.1AD change-over circuit 34 carries out switching motion and exports digital value D9～D6 during for Hi at the 1st clock signal clk 1, carries out the automatic zero set action during for Lo at the 1st clock signal clk 1.1DA change-over circuit 36 keeps the conversion specified data during for Lo at the 1st clock signal clk 1, becomes nondeterministic statement during for Hi at the 1st clock signal clk 1.
The 1st switch SW 1 is connected during for Hi at switching signal CLKSW, disconnects during for Lo at switching signal CLKSW.The 2nd switch SW 2 is connected during for Lo at switching signal CLKSW, disconnects during for Hi at switching signal CLKSW.
The 3rd amplifying circuit 52 and 2AD change-over circuit 54, the analog signal of being imported in the sampling of the rising edge of the 2nd clock signal clk 2.The 3rd amplifying circuit 52 amplifies in the analog signal that the 2nd clock signal clk 2 will be sampled during for Hi, carries out automatic zero set at the 2nd clock signal clk 2 during for Lo and moves.Do not amplify in during the D1～D0 of 2AD change-over circuit 54 conversion lowest orders.The 4th amplifying circuit 60, the analog signal of being imported in the sampling of the trailing edge of the 2nd clock signal clk 2.Amplify in the analog signal that the 2nd clock signal clk 2 will be sampled during for Lo, carry out automatic zero set at the 2nd clock signal clk 2 during for Hi and move.Adopt under the situation of the 2nd subtraction amplification circuit 62 replacing the 4th amplifying circuit 60, when the 2nd clock signal clk 2 is Lo, the analog signal of sampling is carried out subtraction and amplify.Do not amplify in during next half clock behind 2AD change-over circuit 54 conversion D1～D0.
2AD change-over circuit 54 carries out switching motion at the 2nd clock signal clk 2 during for Hi, and comprises redundant digit and export 3, carries out the automatic zero set action during for Lo at the 2nd clock signal clk 2.2DA change-over circuit 56 keeps the conversion specified data during for Lo at the 2nd clock signal clk 2, becomes nondeterministic statement during for Hi at the 2nd clock signal clk 2.When being output as D1～D0,2AD change-over circuit 54 do not carry out switching motion.
It during the automatic zero set of the 1st amplifying circuit the 32, the 2nd amplifying circuit the 40, the 3rd amplifying circuit the 52, the 4th amplifying circuit 60,1AD change-over circuit 34 and 2AD change-over circuit 54 state during the signal of being imported is sampled.As shown in the figure, during 2AD change-over circuit 54 conversion process D5～D4 and the D3～D2,1AD change-over circuit 34 conversion process is simultaneously followed the input analog signal Vin that imports.By such pipeline processes, as AD converter generally speaking, the 1st clock signal clk 1 as benchmark, can be exported 10 digital value 1 time in 1 cycle.
Fig. 5 is the time diagram of the course of action during 8 of conversions in the AD converter 20 of presentation graphs 3.The frequency of the 2nd clock signal clk 2 is 2 times of frequency of the 1st clock signal clk 1.The frequency of the 2nd clock signal clk 2 changes to 2/3 when changing 10.The 1st clock signal clk 1 when changing 10 and the frequency of the 2nd clock signal clk 2 can be generated by not shown frequency divider or multiplier.
The action of each composed component and the explanation of Fig. 4 are same substantially.Difference is: 2AD change-over circuit 54 is not D5～D4, D3～D2, the D1～D0 that is divided into 36 of low levels of conversion, but is divided into D3～D2, the D1～D0 of 4 of 2 conversion low levels.As shown in the figure, during 2AD change-over circuit 54 conversion process D3～D2 in, 1AD change-over circuit 34 is the then input analog signal Vin of input of conversion process simultaneously.By such pipeline processes, as AD converter generally speaking, the 1st clock signal clk 1 as benchmark, can be exported 8 digital value 1 time in 1 cycle.Like this, if course of action when changing with 10 resolution shown in Figure 4 and the course of action when changing with 8 resolution shown in Figure 5 compare, then as can be known: the frequency of side reduction the 2nd clock signal clk of changing with 8 resolution 2.Therefore, with the side that 8 resolution is changed, consume electric power and diminish.And then, also can change the bias current of amplifying circuit according to clock frequency intentionally, consume electric power to reduce.
Fig. 6 represents the AD converter 20 among the 2nd embodiment.The 2nd embodiment is: 4 of the 1st grade of 80 conversions, the 2nd grade 100,3rd level 120 and the 4th grade 140 respectively change 2, by the example of 4 grades of pipelined ad converters that constitute 20.
Input analog signal Vin is imported in the 1st amplifying circuit 82 and the 1AD change-over circuit 84.The 1st amplifying circuit 82 and 1AD change-over circuit 84, the signal of being imported with identical timing sampling.1AD change-over circuit 84 is flicker types, and it is 4 that its resolution is promptly changed figure place.The conversion of signals that 1AD change-over circuit 84 will be sampled is a digital value, and it is in the 1DA change-over circuit 86 that 4 of high positions are input to encoder 150.1DA change-over circuit 86 will be converted to the analogue value by the digital value of 1AD change-over circuit 84 through changing.
The 1st amplifying circuit 82 keeps specified time limit with the signal of sampling, and outputs to the 1st subtraction circuit 88.The 1st amplifying circuit does not amplify the signal of sampling, but plays a role as sampling hold circuit.The 1st subtraction circuit 88 deducts the output analog signal of 1DA change-over circuit 86 from the output analog signal of the 1st amplifying circuit 82.The 2nd amplifying circuit 90 is enlarged into 2 times with the output of the 1st subtraction circuit 88.And, replace the 1st subtraction circuit 88 and the 2nd amplifying circuit 90, also can adopt the 1st one-piece type subtraction amplification circuit 92.Thus, can dwindle circuit area.
The output analog signal of the 2nd amplifying circuit 90 is imported in the 3rd amplifying circuit 102 and the 2AD change-over circuit 104.The 3rd amplifying circuit is sampled with identical timing with 2AD change-over circuit 104.The 3rd amplifying circuit 102 is enlarged into 2 times with the signal of sampling, and outputs to the 2nd subtraction circuit 108.2AD change-over circuit 104 is a digital value with the conversion of signals of sampling, and begins 5,6 are outputed to encoder 150 and the 2DA change-over circuit 106 from a high position.
Because the 2nd grade 100 conversion figure place is 2, so original the 1st grade 80 output must be enlarged into 4 in fact (2 square) times.In the 1st grade 80, be enlarged into 2 times by the 2nd amplifying circuit 90.In addition, if the reference voltage of the comparator in the 2AD change-over circuit 104 is set at 1/2 of 1AD change-over circuit 84, then can realize above-mentioned substantial 4 times.
2DA change-over circuit 106 will be converted to the analogue value by the digital value that 2AD change-over circuit 104 was changed.At this moment, on one side the output of 2AD change-over circuit 104 is enlarged into 2 times, be converted to analog signal on one side.The 2nd subtraction circuit 108 deducts the output analog signal of 2DA change-over circuit 106 from the output analog signal of the 3rd amplifying circuit 102.The 4th amplifying circuit 110 is enlarged into 2 times with the output analog signal of the 2nd subtraction circuit 108.And, can replace the 2nd subtraction circuit 108 and the 4th amplifying circuit 110, and adopt the 2nd one-piece type subtraction amplification circuit 112.Thus, can dwindle circuit area.
The output analog signal of the 4th amplifying circuit 110 is imported in the 5th amplifying circuit 122 and the 3AD change-over circuit 124.The 5th amplifying circuit 122 is sampled with identical timing with 3AD change-over circuit 124.The 5th amplifying circuit 122 is enlarged into 2 times with the signal of sampling, and outputs to the 3rd subtraction circuit 128.3AD change-over circuit 124 is a digital value with the analog signal conversion of sampling, and will output to encoder 150 and 3DA change-over circuit 126 from 7,8 that a high position begins.
3DA change-over circuit 126 will be converted to the analogue value by the digital value that 3AD change-over circuit 124 converts.At this moment, on one side the output of 3AD change-over circuit 124 is enlarged into 2 times, be converted to analog signal on one side.The 3rd subtraction circuit 128 deducts the output analog signal of 3DA change-over circuit 126 from the output analog signal of the 5th amplifying circuit 122.The 6th amplifying circuit 130 is enlarged into 2 times with the output analog signal of the 3rd subtraction circuit 128.And, also can replace the 3rd subtraction circuit 138 and the 6th amplifying circuit 130, and adopt the 3rd one-piece type subtraction amplification circuit 132.
The output analog signal of the 6th amplifying circuit 130 is imported in the 4AD change-over circuit 142.142 pairs of analog signal samplings of being imported of 4AD change-over circuit are converted to digital value, and begin to output to encoder 150 with 9,10 from a high position.
The output digital value of the output digital value of the output digital value of the output digital value of the 1AD change-over circuit 84 that encoder 150 receptions are the 1st grade 80, the 2nd grade 100 2AD change-over circuit 104, the 3AD change-over circuit 124 of 3rd level 120 and the 4th grade 140 4AD change-over circuit 142, separate redundant digit, form 8 or 10 s' digital value.And, do not export under the situation of digital value at 4AD change-over circuit 142 from the 4th grade 140, become 8 digital value.Error correction circuit 152 is judged redundant digit and is carried out error correction.
Like this, this routine AD converter 20 under situation about changing with 10 resolution, by making whole levels effectively (active), thereby can realize.On the contrary, under situation about changing, stop by making the 4th grade 140, thereby can realize with 8 resolution.And under situation about changing with 8 resolution, the power supply that does not just stop the 4th grade is supplied with, and also can stop the 5th amplifying circuit 122 of 3rd level 120 and the power supply of the 6th amplifying circuit 130 and supply with.Thus, with the side that 8 resolution is changed, consume electric power and diminish.
Fig. 7 is the flow chart of the action of the signal processing system in expression the 1st execution mode.From the view data (S10) of AD converter 20 to the DSP18 input digitization.DSP18 carries out time integral, calculating (S12) to the light quantity that shines CCD12 from this view data.Judge that this light quantity is whether below the threshold value of regulation (S14).If the threshold value of regulation following ("Yes" of S14), then output makes the control signal of AD converter 20 with 8 bit patterns action usefulness.AD converter 20 according to this control, is digital value (S16) with 8 bit resolution conversions shown in Figure 5.
If not the threshold value of regulation following ("No" of S14), then output makes the control signal of AD converter 20 with 10 bit patterns action usefulness.AD converter 20 according to this control, is digital value (S18) with 10 bit resolution conversions shown in Figure 4.At this, the threshold value of regulation is set from the aspect of electron number, as long as the resolution that is set at 10 makes the decomposition analog signal become useless value.And optimum value can be tried to achieve by actual measurement or simulation.Below, (S20 is) suitably carries out above-mentioned processing till the input that does not have view data.Be not limited to present embodiment, also can with the gain control signal interlock that is dependent on from the routine processes of DSP, control the figure place of AD converter.
(the 2nd execution mode)
The 2nd execution mode is the example that signal processing system of the present invention is applicable to communication system.Fig. 8 represents the basic comprising of the signal processing system in the 2nd execution mode.At this, be example with the system that receives earthwave numeral TV signal.Antenna 160 receives RF (the Radio Frequency wireless frequency) signal of UHF frequency band, and outputs to tuner IC 170.Tuner IC 170 comprises not shown frequency mixer (mixer), with direct conversion regime the RF signal directly is converted to baseband signal.In tuner 170, be mounted with variable amplifier 172, according to by from the FEEDBACK CONTROL of DSP182 and baseband signal is amplified in the gain of appointment.Separate the system LSI 180 that calls and comprise AD converter 20 and DSP182.Above-mentioned baseband signal is imported in the AD converter 20.AD converter 20 is digital value with 8 or 10 s' conversion of resolution, and outputs to DSP182.DSP182 mainly carries out the gain controlling of demodulation process, variable amplifier 172 and the mode switch of AD converter described later 20 is handled.
Under the situation that has adopted direct conversion regime, owing to directly be converted to base band, be difficult so end DC side-play amount composition with electric capacity etc. in the prime of AD converter 20.Therefore, AD converter 20 is considered the side-play amount change and is set with redundant digit.For example, received signal is converted in the system of digital value, preestablishes 2 redundant digit, prepare the scope of 10 parts in resolution with 8.Under this situation, DSP182 measures DS side-play amount composition, ends side-play amount composition not from the output of AD converter 20.
Fig. 9 is the flow chart of the action of the signal processing system in expression the 2nd execution mode.DSP182 measures side-play amount from the output signal with the AD converter 20 of 10 bit patterns actions, measure the necessary scope (S30) of AD converter 20.During this side-play amount is measured, AD converter 20 is controlled to be with 10 bit patterns moves.Then,, then adjust this scope, so that possess 8 conversions scope interior (S34) that the received signal of this side-play amount is accommodated in AD converter 20 if DSP182 determines side-play amount (S32).And, the control signal that makes it with 8 bit patterns action usefulness is outputed to AD converter 20, AD converter 20 is transferred to 8 bit patterns (S36) as normal mode.Measure though DSP182 carries out side-play amount in the early stage, consider the variation of reception environment etc., also can carry out side-play amount each specified time limit and measure.In this case, during side-play amount is measured in, AD converter 20 is moved with 10 bit patterns.
Figure 10 represents the example that the scope of AD converter 20 is adjusted.Among Figure 10,3 scope a～c are respectively 8 conversion scopes.The scope d of its 4 times of sizes is measuring 10 the conversion scopes of side-play amount.DSP182 measures with the output signal of scope from side-play amount and measures the side-play amount composition, according to its result, selects suitable scope from above-mentioned 3 scope a～c.AD converter 20, if range of choice, then with 8 translative mode actions as normal mode.
At this, the method for the scope of adjusting AD converter 120 is described.The 1AD change-over circuit 34 that the variable control of DSP182 is shown in Figure 3 and the reference voltage range of 2AD change-over circuit 54.Particularly, the reference voltage range when this reference voltage range during with 8 bit patterns and 10 bit patterns compares, and is controlled to 1/4.For example, the control of the hot side reference voltage V RT step-down etc. of this reference voltage range will be used to generate as long as carry out.More specifically, for example,, also can use built-in resistance row, switch to change hot side reference voltage V RT, low potential side reference voltage V RB in order to generate reference voltage range.
Like this,, when side-play amount is measured, comprise redundant digit in the conversion figure place of AD converter 20, by after the side-play amount adjustment, moving, thereby can reduce the consumption electric power of AD converter with the conversion figure place of having removed redundant digit according to the 2nd execution mode.
In the above description, to setting forth according to the state of signal processing system, the AD converter 20 of conversion figure place dynamic change.Below, to according to the state of signal processing system, make in addition circuit constant and the AD converter 20 of at least one side's dynamic change of constituting of circuit describe.
At first, the AD converter 20 to the function that realizes the current sinking dynamic change describes.Figure 11 represents the AD converter 20 among the 3rd embodiment.AD converter 20 among the formation of the AD converter 20 among the 3rd embodiment and action and the 1st embodiment shown in Figure 3 is basic identical.And making the formation of conversion figure place dynamic change is not in essence in the following description, even but be mounted with also passablely, do not load yet and be fine.
Figure 12 represents the AD converter 20 among the 4th embodiment.AD converter 20 among the formation of the AD converter 20 among the 4th embodiment and action and the 2nd embodiment shown in Figure 6 is basic identical.AD converter 20 among the 4th embodiment also is the formation that has increased bias control circuit 154 in the formation of the 2nd embodiment.Bias control circuit 154 makes the bias voltage that supplies to the 1st amplifying circuit the 82, the 2nd amplifying circuit the 90, the 3rd amplifying circuit the 102, the 4th amplifying circuit the 110, the 5th amplifying circuit 122 and the 6th amplifying circuit 130, and system mode detection signal according to the rules changes.
Figure 13 represents to change the 1st example that the circuit of the bias current of amplifying circuit constitutes.This circuit formation comprises: operational amplifier 190; With the bias voltage generative circuit that is used for supplying with bias voltage to the constant-current source of operational amplifier 190.And this bias voltage generative circuit constitutes the part of above-mentioned bias control circuit 74,154.
1 pair pmos transistor M2, M4 provide supply voltage Vdd to drain electrode, and the bias voltage of regulation is provided to gate electrode.These have constituted current mirror circuit, flow through equal drain current in the electrode of two sides' source.1 pair nmos transistor M6, M8, drain electrode connects above-mentioned current mirror circuit, and the source electrode connects constant-current source.Provide differential input IN1, IN2 to gate electrode.And, can obtain exporting OUT from the tie point of PMOS transistor M4 and nmos pass transistor M8.1 pair nmos transistor M10, M12 constitute constant-current source.Supply with bias voltage from above-mentioned bias voltage generative circuit to the common gate electrode of 1 pair nmos transistor M10, M12.
The bias voltage generative circuit possesses the series circuit of PMOS transistor M14 and nmos pass transistor M16 between supply voltage Vdd and earthing potential.And the drain electrode of nmos pass transistor M16 is connected with gate electrode.PMOS transistor M14 plays constant-current source.On the gate electrode of PMOS transistor M14, apply the voltage that is controlled as the constant-current source action.The voltage of the tie point of PMOS transistor M14 and nmos pass transistor M16 as bias voltage, is supplied to the 1 pair nmos transistor M10 that the constant-current source as operational amplifier 190 plays a role, the gate electrode of M12.
Formation below in this basic comprising, adding.Between the tie point and earthing potential of above-mentioned PMOS transistor M14 and nmos pass transistor M16, with nmos pass transistor M24, the M34 of the additional in parallel stated number of nmos pass transistor M24.In order to control each nmos pass transistor M24, between this tie point and earthing potential, the series circuit of 2 nmos pass transistor M20, M22 of push-pull circuit (push pull circuit) effect has been set respectively.Connect the tie point of these two nmos pass transistor M20, M22 and the gate electrode of nmos pass transistor M24.
Constitute 1 piece with these three nmos pass transistor M20, M22, M24.This piece of stated number is set.In the example of Figure 13, be provided with 2.Import biasing (bias) control signal CONT1 and reverse signal thereof respectively to the gate electrode of 2 nmos pass transistor M20, M22 playing the push-pull circuit effect.
Nmos pass transistor M16 and a plurality of nmos pass transistor M24, M34 in parallel move in the zone of saturation, and M14 imports constant current to drain terminal from the PMOS transistor.The not shown control section of bias control circuit 74,154 is according to above-mentioned biasing (bias) the control signal CONT1, the CONT2 that supply to each piece respectively, among nmos pass transistor M24, the M34 of control stated number, connect gate terminal with drain terminal and effective quantity.Thus, make the voltage dynamic change of the tie point of above-mentioned PMOS transistor M14 and nmos pass transistor M16.Because this voltage is applied on the common gate electrode of amplifying circuit inside as nmos pass transistor M10, the M12 of constant-current source action that AD converter 20 comprised, so can make the bias current dynamic change of this amplifying circuit as bias voltage.
Figure 14 represents to change the 2nd example that the circuit of the bias current of amplifying circuit constitutes.This circuit constitutes, and is about operational amplifier 190 and be used for supplying with the PMOS transistor M14 of bias voltage and the series circuit of nmos pass transistor M16 to it, identical with the 1st example.M14 is in parallel with the PMOS transistor, and PMOS transistor M44, M54 that drain electrode is connected in the stated number of supply voltage Vdd are set.PMOS transistor M44, the M54 of this stated number also play a role as constant-current source.
In order to control each PMOS transistor M44, between the tie point of supply voltage Vdd and PMOS transistor M14 and nmos pass transistor M16, the series circuit of 2 nmos pass transistor M40, M42 of push-pull circuit effect has been set respectively.Connect the tie point of these two nmos pass transistor M40, M42 and the gate electrode of PMOS transistor M44.
By PMOS transistor M44 and 2 nmos pass transistor M40, M42, amount to 3 transistors and constitute 1 piece.This piece of stated number is set.Gate electrode to 2 nmos pass transistor M40, M42 playing the push-pull circuit effect is imported bias control signal CONT1 and reverse signal thereof respectively.
The not shown control section of bias control circuit 74,154 is according to the above-mentioned bias control signal CONT1, the CONT2 that supply to each piece respectively, the quantity of moving among PMOS transistor M44, the M54 of control stated number, as the constant-current source of the benchmark that becomes this bias voltage generative circuit.Thus, make the voltage dynamic change of the tie point of above-mentioned PMOS transistor M14 and nmos pass transistor M16.Thus, can change the bias current of the amplifying circuit that AD converter 20 comprised.
Figure 15 represents to change the 3rd example that the circuit of the bias current of amplifying circuit constitutes.This circuit constitutes, and is about operational amplifier 190 and be used for supplying with the PMOS transistor M14 of bias voltage and the series circuit of nmos pass transistor M16 to it, identical with the 1st example.The 3rd example has: though the bias voltage that is applied on the gate electrode of the nmos pass transistor M12, the M14 that move as the constant-current source of operational amplifier 190 does not change, can change the number of the constant-current source in the operational amplifier 190, formation.
The constant-current source of stated number is set between the common source electrode of 1 pair nmos transistor M6, the M8 of the differential input IN1, the IN2 that apply operational amplifier 190 and earthing potential.Constant-current source can be made of nmos pass transistor M60.In order to control this nmos pass transistor 60, be provided for its gate electrode and above-mentioned bias voltage being connected the switch SW 4 that disconnects and being used for its gate electrode and earthing potential are connected the switch SW 6 of disconnection.Control this to switch SW4, SW6 by connecting respectively with bias control signal CONT1 and reverse signal thereof to disconnect, thereby can connect any one switch SW 4, SW6.This nmos pass transistor M60 and 1 couple of switch SW4, SW6 are provided with the piece of stated number as 1.
The not shown control section of bias control circuit 74,154, according to the above-mentioned bias control signal CONT1, the CONT2 that supply to each piece respectively, the quantity of the nmos pass transistor M60 that plays the constant-current source effect of control stated number.Thus, make the value dynamic change of the constant-current source of the differential amplifier circuit that constitutes operational amplifier 190.Thus, can change the bias current of the amplifying circuit that AD converter 20 comprised.
Then, the AD converter 20 that makes the circuit of amplifying circuit constitute the function of dynamic change to realization describes.Figure 16 represents the AD converter 20 among the 5th embodiment.AD converter 20 among the formation of the AD converter 20 among the 5th embodiment and action and the 1st embodiment shown in Figure 3 is basic identical.
Figure 17 represents the AD converter 20 among the 6th embodiment.AD converter 20 among the formation of the AD converter 20 among the 6th embodiment and action and the 2nd embodiment shown in Figure 6 is basic identical.AD converter 20 among the 6th embodiment also is the formation that has increased amplifier formation control signal generative circuit 156 in the formation of the 2nd embodiment.Amplifier constitutes control signal generative circuit 156, system mode detection signal according to the rules, output amplifier constitutes control signal at least one in the 1st amplifying circuit the 82, the 2nd amplifying circuit the 90, the 3rd amplifying circuit the 102, the 4th amplifying circuit the 110, the 5th amplifying circuit 122 and the 6th amplifying circuit 130.
Figure 18 represents to change the example that the circuit of amplifying circuit constitutes.This example is to adopt the example of the differential amplifier circuit of complete differential mode.The formation of the differential amplifier circuit of folding cascode (cascode) type of Figure 18 (a) expression, the formation of the differential amplifier circuit that Figure 18 (b) expression is common.At first, illustrate that the common circuit shown in Figure 18 (b) constitutes.This differential amplifier circuit comprises 1 pair pmos transistor M70, M72,1 pair nmos transistor M74, M76 and constant-current source 202.
1 pair pmos transistor M70, M72 provide supply voltage Vdd to its drain electrode, provide regulation voltage bias VB 4 to gate electrode.1 pair nmos transistor M74, M76, its drain electrode is connected with the source electrode of 1 pair pmos transistor M70, M72, and its source electrode connects constant-current source 202.Provide differential input IN1, IN2 to its gate electrode.And, obtain differential output OUT1, OUT2 from the tie point of 1 pair pmos transistor M70, M72 and 1 pair nmos transistor M74, M76.
Next, the circuit formation of having added folding cascode shown in Figure 18 (a) is described.Cascode connects PMOS transistor MS0, M82, nmos pass transistor M84, M86 and 3 transistors such as nmos pass transistor M88, M90 on above-mentioned each tie point.On the gate electrode of 1 couple of PMOS crystal M80, M82, apply the voltage bias VB 3 of regulation, on 1 pair nmos transistor M84, M86 and 1 pair nmos transistor M88, M90, also apply regulation voltage bias VB 2, VB1 respectively.And, obtain differential output OUT1, OUT2 from the tie point of the drain electrode of the source electrode of 1 couple of PMOS crystal M80, M82 and 1 pair nmos transistor M84, M86.
Amplifier constitutes the not shown control section of control signal generative circuit 76,156, be applied to the voltage bias VB 3 on the gate electrode of 1 couple of PMOS crystal MS0, M82 by control, thereby switch the formation of the differential amplifier circuit of the formation of common differential amplifier circuit and folding cascode type.Particularly, by till the gate electrode of 1 pair pmos transistor M80, M82 being brought up to the level of supply voltage VDD, thereby can make it as common differential amplifier circuit action.
In addition, in addition, though various amplifiers such as 2 grades of amplifiers having added drive circuit on differential amplifier circuit or concertina type (telescopic) amplifier are arranged, understand these can be by additional diverter switch easily commutation circuit constitute.
Like this, constitute by the circuit that dynamically switches amplifying circuit, thereby can adopt following using method.For example, under the high situation of the precision prescribed of system, because the DC yield value of amplifying circuit must increase, so use the differential amplifier circuit that folds the cascode type.But folding cascode type differential amplifier circuit also has relative operating frequency, aspect that current efficiency is low.If exist according to the situation of system, the situation that precision can be low, then owing to be not to adopt folding cascode type differential amplifier circuit but adopt common differential amplifier circuit, current efficiency is good, so can move with current sinking still less.Therefore,, constitute by the circuit that makes the amplifying circuit that AD converter 20 comprised and to change, adjust the current sinking of amplifying circuit, thereby can more reduce current sinking than the situation that permanent circuit constitutes according to the requirement of system.
Then, the AD converter 20 to the function of the capacitance dynamic change that realizes making amplifying circuit describes.Figure 19 represents the AD converter 20 among the 7th embodiment.AD converter 20 among the formation of the AD converter 20 among the 7th embodiment and action and the 1st embodiment shown in Figure 3 is basic identical.
Figure 20 represents the AD converter 20 among the 8th embodiment.AD converter 20 among the formation of the AD converter 20 among the 8th embodiment and action and the 2nd embodiment shown in Figure 6 is basic identical.AD converter 20 among the 8th embodiment also is the formation that has increased capacitance control signal generative circuit 158 in the formation of the 2nd embodiment.Capacitance control signal generative circuit 158 system mode detection signal according to the rules, at least one the output capacitance value control signal in the 1st amplifying circuit the 82, the 2nd amplifying circuit the 90, the 3rd amplifying circuit the 102, the 4th amplifying circuit the 110, the 5th amplifying circuit 122 and the 6th amplifying circuit 130.
Figure 21 represents to change the example of the capacitance of amplifying circuit.This example is the example that has adopted switching capacity type amplifying circuit.Connecting input electric capacity C12 on reverse input end of operational amplifier 190, and input input voltage vin 1.Between the input terminal of the reverse input end of operational amplifier 190 and amplifying circuit integral body, input usefulness electric capacity C14, the C16 of stated number are set in parallel with electric capacity C12 with input.These are controlled to be whether form combined capacity by switch SW 12, SW14, switch SW 16 and SW18 respectively.These switch SW 12, SW14, SW16, SW18 are connected by the control signal of regulation and disconnect control.
Non-inverting input of operational amplifier 190 is connected between itself and the earthing potential.The lead-out terminal of operational amplifier 190 is situated between with reverse input end and is connected with electric capacity C22 by feedback.Feedback electric capacity C24, the C26 of stated number are set with electric capacity C22 in parallel with feedback in addition.These are controlled to be whether form combined capacity by switch SW 22, SW24, switch SW 26 and SW28 respectively.These switch SW 22, SW24, SW26, SW28 are also connected by the control signal of regulation and disconnect control.This switching capacity type amplifying circuit can amplify input voltage vin according to the ratio of input capacitance value with the feedback capacity value.
The not shown control section of capacitance control signal generative circuit 78,158 is controlled above-mentioned switch group, makes to connect the variation of electric capacity number, so that at least one side of input capacitance value and feedback capacity value changes.
Under the high situation of the precision prescribed of system, the sampling noiset value that amplifying circuit produces must reduce.Because the sampling noiset of switching capacity type amplifying circuit depends on √ (kT/C), so wish that the capacitance of amplifying circuit is big.And constant k is a Boltzmann constant, and variable T is an absolute temperature, and variable C is a capacitance.Relative therewith, in the AD converter of circular form or pipeline-type, the amplifying circuit file connects, and the increase of capacitance causes the increase of the load capacitance of prime, the increase that consumes electric power.Therefore, owing to precision, change by making the sampling capacitance value, thereby can reduce load capacitance, so can carry out the reduction of current sinking according to system requirements.
Next, to realization the AD converter 20 of the function of operating frequency dynamic change is described.Figure 22 represents AD converter 20 and the ADC control master clock generative circuit 210 among the 9th embodiment.AD converter 20 among the formation of the AD converter 20 among the 9th embodiment and action and the 1st embodiment shown in Figure 3 is basic identical.ADC control master clock generative circuit 210, the master clock that will be used for the operating frequency of regulation AD converter 20 supplies to AD converter 20 interior ADC and controls clock forming circuit 79.ADC control master clock generative circuit 210, system mode detection signal according to the rules, the system's pulse that generates from quartz crystal etc. generates the master clock of AD converter 20 usefulness.ADC control clock forming circuit 79 receives this master clock, sets the operating frequency of AD converter 20.
Figure 23 represents AD converter 20 and the ADC control master clock generative circuit 214 among the 10th embodiment.AD converter 20 among the formation of the AD converter 20 among the 10th embodiment and action and the 2nd embodiment shown in Figure 6 is basic identical.The master clock that ADC control master clock generative circuit 214 will be used for the operating frequency of regulation AD converter 20 supplies to the ADC control clock forming circuit 159 in the AD converter 20.ADC control clock forming circuit 159 receives above-mentioned shielding clock, sets the operating frequency of AD converter 20.
AD converter among the 9th embodiment and the 10th embodiment is all used amplifying circuit in inside.Therefore, if according to the conversion speed of system requirements, make the operating frequency dynamic change of AD converter 20, the optimization current sinking then can reduce the current sinking of AD converter 20.In addition, make the operating frequency dynamic change, also can realize the reduction of current sinking according to the precision prescribed of system.
For example, under the high situation of the precision prescribed of system, owing to must fully carry out the stable of amplifying circuit, so operating frequency must reduce.Relative therewith, under the low situation of precision prescribed, because to compare stable (settling) insufficient also passable with the high situation of precision, so can improve operating frequency.Thus, precision be not made as under the necessary situation, can shortening the required total ascent time of conversion, during not changing, can make the management of AD converter 20 for stand-by state or electric current such as cut off the electricity supply.
More than, the present invention that has been base description with the execution mode.These execution modes are examples, and the composition of each inscape or variety of processes can have various variation.In addition, those of ordinary skill in the art knows such variation also within the scope of the invention.Below, enumerate variation.
In order to reduce the consumption electric power of above-mentioned AD converter, illustrated a plurality of embodiment that its circuit formation or circuit constant dynamic change are used.These embodiment can certainly overlappingly use.
Above-mentioned AD converter has illustrated that selectivity switches the example of 8 bit patterns and 10 bit patterns.About this point, be not defined in this figure place, AD converter for example shown in Figure 3 also can be carried out 6,8,10 or 12 s' output, can carry out the switch mode of these combination in any is set.
In addition, the AD converter that comprises level of circular form is not limited to form shown in Figure 3, also can be the form more than 1 grade or 3 grades.If this level more than 1 is a circular form, the output figure place that change caused that then can carry out operating frequency changes.
Also have, the action of the AD converter that each execution mode is put down in writing regularly is not limited to the example of time diagram, can set arbitrarily in the limit of the action that can guarantee each inscape.
Claims (21)
1. analog-digital converter is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, it is characterized in that,
According to the state of the system of being loaded, circuit is constituted or the circuit constant dynamic change.
2. analog-digital converter is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, it is characterized in that,
According to the state of the system of being loaded, make the dynamic change of conversion figure place.
3. analog-digital converter wherein has the elementary cell of level, and this elementary cell comprises: will be from the input analog signal conversion of the level analog-to-digital conversion circuit for the digital value of stipulating figure place; The output of described analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From described input analog signal from level, or from will be described with the magnification ratio of regulation from the output analog signal of the amplifying circuit of the input analog signal amplification of level, deducting the subtraction circuit of the output of described D/A conversion circuit; And by this elementary cell is used 1 time or is reused, thereby the digital signal that obtains stipulating it is characterized in that,
According to the state of the system of being loaded, change offers the operating frequency of at least one described level, so that the dynamic change of conversion figure place.
4. signal processing system is to comprise with analog signal conversion being the signal processing system of analog-digital converter of the digital signal of regulation figure place, it is characterized in that,
The control part that possesses the conversion figure place dynamic change that makes described analog-digital converter;
Described control part passes through the ratio of operating frequency with the sample frequency of the described analog-digital converter of change, and described conversion figure place is changed.
5. signal processing system is to comprise with analog signal conversion being the signal processing system of analog-digital converter of the digital signal of regulation figure place, it is characterized in that,
The control part that possesses the conversion figure place dynamic change that makes described analog-digital converter;
Described control part changes the conversion figure place of described analog-digital converter according to gain adjustment.
6. signal processing system is to comprise with analog signal conversion being the signal processing system of analog-digital converter of the digital signal of regulation figure place, it is characterized in that,
The control part that possesses the conversion figure place dynamic change that makes described analog-digital converter;
Described control part changes the conversion figure place of described analog-digital converter according to the side-play amount adjustment.
7. signal processing system according to claim 4 is characterized in that,
Described analog-digital converter comprise with from the level output feed back to from the level input the level;
Described control part can make the operating frequency dynamic change that offers described level.
8. signal processing system according to claim 5 is characterized in that,
Described analog-digital converter comprise with from the level output feed back to from the level input the level;
Described control part can make the operating frequency dynamic change that offers described level.
9. signal processing system according to claim 6 is characterized in that,
Described analog-digital converter comprise with from the level output feed back to from the level input the level;
Described control part can make the operating frequency dynamic change that offers described level.
10. camera head is characterized in that having:
The be taken image pickup part of body of shooting;
Amplify from the amplifier of the analog signal of described image pickup part output with the gain of regulation;
To be the analog-digital converter of the digital signal of regulation figure place from the analog signal conversion of described amplifier output; With
According to the state of system, make the control part of the conversion figure place dynamic change of described analog-digital converter.
11. according to the described camera head of claim 10, it is characterized in that,
Described control part changes described conversion figure place according to described Amplifier Gain adjustment.
12. an analog-digital converter is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, it is characterized in that,
According to the state of the system of being loaded, make the current sinking dynamic change.
13. an analog-digital converter wherein has the elementary cell of level, this elementary cell comprises: will be from the input analog signal conversion of the level analog-to-digital conversion circuit for the digital value of stipulating figure place; The output of described analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From described input analog signal from level, or from will be described with the magnification ratio of regulation from the output analog signal of the amplifying circuit of the input analog signal amplification of level, deducting the subtraction circuit of the output of described D/A conversion circuit; And by this elementary cell is used 1 time or is reused, thereby the digital signal that obtains stipulating it is characterized in that,
According to the state of the system of being loaded, make the bias current dynamic change of the amplifying circuit that is contained at least one described level.
14. a signal processing system is to comprise with analog signal conversion being the signal processing system of analog-digital converter of the digital signal of regulation figure place, it is characterized in that,
The control part that comprises the current sinking dynamic change that makes the amplifying circuit that described analog-digital converter comprises;
Described control part makes the transistorized bias voltage dynamic change of moving as current source in described amplifying circuit inside according to the signal of detection system state.
15. an analog-digital converter is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, it is characterized in that,
According to the state of the system of being loaded, make the circuit of the amplifying circuit that analog-digital converter comprises constitute dynamic change.
16. an analog-digital converter wherein has the elementary cell of level, this elementary cell comprises: will be from the input analog signal conversion of the level analog-to-digital conversion circuit for the digital value of stipulating figure place; The output of described analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From described input analog signal from level, or from will be described with the magnification ratio of regulation from grade the output analog signal of the amplifying circuit that amplifies of input analog signal, deduct the subtraction circuit of the output of described D/A conversion circuit; And by this elementary cell is used 1 time or is reused, thereby the digital signal that obtains stipulating it is characterized in that,
According to the state of the system of being loaded, make the circuit of the amplifying circuit that is contained at least one described level constitute dynamic change.
17. a signal processing system is to comprise with analog signal conversion being the signal processing system of analog-digital converter of the digital signal of regulation figure place, it is characterized in that,
Comprise that the circuit that makes the amplifying circuit that described analog-digital converter comprises constitutes the control part of dynamic change;
Described control part generates the signal of the circuit formation of the described amplifying circuit of decision according to the signal of detection system state.
18. an analog-digital converter is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, it is characterized in that,
According to the state of the system of being loaded, make the capacitance dynamic change of the switching capacity type amplifying circuit that analog-digital converter comprises.
19. an analog-digital converter wherein has the elementary cell of level, this elementary cell comprises: will be from the input analog signal conversion of the level analog-to-digital conversion circuit for the digital value of stipulating figure place; The output of described analog-to-digital conversion circuit is converted to the Analog signals'digital analog conversion circuit; From the described input analog signal of level certainly, or from the output analog signal of magnification ratio, deduct the subtraction circuit of the output of described D/A conversion circuit with the amplifying circuit of the input analog signal amplification of described level certainly with regulation; And by this elementary cell is used 1 time or is reused, thereby the digital signal that obtains stipulating it is characterized in that,
According to the state of the system of being loaded, make the capacitance dynamic change of the switching capacity type amplifying circuit that is contained at least one described level.
20. a signal processing system is to comprise with analog signal conversion being the signal processing system of analog-digital converter of the digital signal of regulation figure place, it is characterized in that,
The control part that comprises the capacitance dynamic change that makes the switching capacity type amplifying circuit that described analog-digital converter comprises;
Described control part generates the signal of the capacitance of the described switching capacity type amplifying circuit of decision according to the signal of detection system state.
21. an analog-digital converter is to be the analog-digital converter of the digital signal of regulation figure place with analog signal conversion, it is characterized in that,
According to the state of the system of being loaded, make the operating frequency dynamic change.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004163204 | 2004-06-01 | ||
| JP2004163204 | 2004-06-01 | ||
| JP2005134185 | 2005-05-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1705236A true CN1705236A (en) | 2005-12-07 |
| CN100517975C CN100517975C (en) | 2009-07-22 |
Family
ID=35577677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100740789A Expired - Fee Related CN100517975C (en) | 2004-06-01 | 2005-05-31 | Analog digital converter having a function of dynamic adjustment corresponding to the state of the system |
Country Status (2)
| Country | Link |
|---|---|
| JP (2) | JP2008193743A (en) |
| CN (1) | CN100517975C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102894955A (en) * | 2011-07-29 | 2013-01-30 | 佳能株式会社 | Ophthalmologic apparatus |
| CN101849189B (en) * | 2007-11-05 | 2013-03-27 | 皇家飞利浦电子股份有限公司 | Current integrator with wide dynamic range |
| CN103839506A (en) * | 2012-11-20 | 2014-06-04 | 联咏科技股份有限公司 | Display device and drive circuit thereof, driving method of display panel, and display system |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6018829B2 (en) * | 2012-07-27 | 2016-11-02 | ローム株式会社 | Power supply apparatus, power supply system, and power supply method |
| JP6253608B2 (en) * | 2015-03-16 | 2017-12-27 | 株式会社東芝 | Analog / digital conversion circuit |
| JP6869847B2 (en) * | 2017-08-01 | 2021-05-12 | 株式会社日立製作所 | Analog-to-digital converter and probe for ultrasonic diagnostic equipment using it |
| US11366144B2 (en) | 2019-02-25 | 2022-06-21 | Hitachi Energy Switzerland Ag | Method and device for current and voltage measurement |
-
2005
- 2005-05-31 CN CNB2005100740789A patent/CN100517975C/en not_active Expired - Fee Related
-
2008
- 2008-05-09 JP JP2008123741A patent/JP2008193743A/en not_active Withdrawn
- 2008-05-09 JP JP2008123742A patent/JP2008193744A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101849189B (en) * | 2007-11-05 | 2013-03-27 | 皇家飞利浦电子股份有限公司 | Current integrator with wide dynamic range |
| CN102894955A (en) * | 2011-07-29 | 2013-01-30 | 佳能株式会社 | Ophthalmologic apparatus |
| US8944595B2 (en) | 2011-07-29 | 2015-02-03 | Canon Kabushiki Kaisha | Ophthalmologic apparatus |
| CN102894955B (en) * | 2011-07-29 | 2015-06-17 | 佳能株式会社 | Ophthalmologic apparatus |
| CN103839506A (en) * | 2012-11-20 | 2014-06-04 | 联咏科技股份有限公司 | Display device and drive circuit thereof, driving method of display panel, and display system |
| CN103839506B (en) * | 2012-11-20 | 2016-06-08 | 联咏科技股份有限公司 | Display device and drive circuit thereof, the driving method of display floater and display system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100517975C (en) | 2009-07-22 |
| JP2008193743A (en) | 2008-08-21 |
| JP2008193744A (en) | 2008-08-21 |
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