CN106209100B - A kind of LMS error correcting system and method applied to high-speed ADC - Google Patents
A kind of LMS error correcting system and method applied to high-speed ADC Download PDFInfo
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Abstract
The invention discloses a kind of LMS error correcting system and method applied to high-speed ADC, the system includes serial-parallel conversion circuit, concurrent operation circuit and result generative circuit；The output end and concurrent operation circuit connection of serial-parallel conversion circuit, the output end of concurrent operation circuit are connect with result generative circuit；Serial-parallel conversion circuit is used to the input signal of ADC and ADC sampled output signal carrying out serioparallel exchange, obtain the input signal and ADC sampled output signal of the ADC of multichannel, the signal that concurrent operation circuit is used to obtain serioparallel exchange carries out concurrent operation, as a result generative circuit is for being further processed concurrent operation circuit output, and realizes the output of error correction signal.The present invention first passes through serial-parallel conversion circuit and converts, result generative circuit is sent into after being calculated again by concurrent operation circuit, the data transfer rate of all variables has very big reduction, becomes the bottleneck that system for restricting realizes speed so as to avoid this maximum a part of operand.
Description
Technical field
The present invention relates to a kind of LMS error correcting systems and method applied to high-speed ADC.
Background technique
With the progress of integrated circuit technology, digital adaptation alignment technique (abbreviation LMS) is widely used in solution
All kinds of offset issues in ADC, LMS algorithm are to carry out constantly to the filter coefficient of initialization according to minimum mean square error criterion
Come what is realized, LMS algorithm has a convergence time, control of this time by the algorithm step-size factor, in certain value model for amendment
In enclosing, convergence time can be reduced by increasing step factor, but tracking accuracy is lower after stablizing, on the contrary then adjustment time is longer, surely
Tracking accuracy is higher after fixed.
Gain error correction to operational amplifier in ADC is a typical case of LMS algorithm.Due to operation amplifier
The correction of the gain error of device usually needs millesimal precision, so the step factor of LMS algorithm is usually a very little
Value, such as be in 10^-12 rank, at least need 41 bit decimals could be expressed in the form of signed number this step-length because
Son, therefore the bit wide of data is very big in concrete operation, it is difficult to it is realized in high speed circuit.With in recent years high speed
A kind of circuit and method that error correction LMS algorithm can be realized in high-speed ADC is badly in need of in the development of adc circuit.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of LMS error corrections applied to high-speed ADC
System and method.
The purpose of the present invention is achieved through the following technical solutions: a kind of LMS error correction applied to high-speed ADC
System, including serial-parallel conversion circuit, concurrent operation circuit and result generative circuit；The output end of the serial-parallel conversion circuit with
The output end of concurrent operation circuit connection, concurrent operation circuit is connect with result generative circuit；Serial-parallel conversion circuit is used for ADC
Sampled input signal and sampled output signal carry out serioparallel exchange, obtain multichannel ADC sampled input signal and ADC sampling it is defeated
Signal out, the signal that concurrent operation circuit is used to obtain serioparallel exchange carry out concurrent operation, and as a result generative circuit receives parallel
The output of computing circuit is further processed, and realizes the output of error correction signal.
The concurrent operation circuit includes multiple concurrent operation branches, and each concurrent operation branch corresponds to ADC all the way
Sampled input signal and ADC sampled output signal；The output end of each concurrent operation branch is connect with result generative circuit.
The concurrent operation branch include ADC sampled input signal parallel input terminal, sampled output signal parallel input terminal,
First operation output end, the second operation output end and four multipliers；
The two-way input terminal of first multiplier respectively with ADC sampled input signal parallel input terminal and sampled output signal simultaneously
The connection of row input terminal, the output end of the first multiplier connect with the input terminal all the way of third multiplier, third multiplier it is another
Road input terminal connection signal u, the output end of third multiplier are connect with the first operation output end；
The two-way input terminal of second multiplier is connect with sampled output signal parallel input terminal, the output of the second multiplier
End is connect with the input terminal all the way of the 4th multiplier, the another way input terminal connection signal u of the 4th multiplier, the 4th multiplier
Output end is connect with the second operation output end.
The result generative circuit includes adder one, adder two, adder three, subtracter, d type flip flop one, D touching
Send out device two, d type flip flop three, divider and the 5th multiplier；The input terminal of the adder one respectively with each concurrent operation branch
The first operation output end on road connects, and the output end of adder one passes through the first via input terminal of d type flip flop one and adder three
Connection；The input terminal of the adder two is connect with the second operation output end of each concurrent operation branch respectively, adder two
Output end and the negative input end of subtracter connect, the positive input of subtracter terminates 1*2expSignal, the output end and D of subtracter
Trigger two connects, and the output end of d type flip flop two is connect with the first via input terminal of the 5th multiplier, and the second of the 5th multiplier
Road input terminal is connect with the output end of d type flip flop three, and the output end of the 5th multiplier and the second road input terminal of adder three connect
It connects, the output end of adder three is connect with divider, which fixes, and divider output end was both defeated with d type flip flop three
Enter end connection, while also being connect with the output end of result generative circuit, as final LMS error correction signal.
In the result generative circuit, the signal w [kM] of the second road input terminal of the 5th multiplier input indicate error with
Track signal is obtained by the LMS error correction signal of last final output by the processing of d type flip flop three,.
A kind of bearing calibration of the LMS error correcting system applied to high-speed ADC, comprising the following steps:
S1. the sampled input signal d [n] and sampled output signal x [n] of ADC are obtained；
S2. signal d [n] and signal x [n] is subjected to serioparallel exchange, and u pairs of binding signal in each concurrent operation branch
The signal that serioparallel exchange obtains carries out operation, and u represents the significance bit of step factor scientific notation, i.e., by the step-length of LMS operation
Factor u*2-expAmplification 2expU can be obtained again；
S3. the signal of the first operation output end in each concurrent operation branch is added, is obtained p_res_sum [kM], it will
The second output terminal signal of each concurrent operation branch is added, and is handled by subtracter, and signal s_res_sum [kM] is obtained；
S4., signal P1 is obtained after p_res_sum [kM] to be passed through to the processing of d type flip flop one；S_res_sum [kM] is passed through
It after the processing of d type flip flop two, is multiplied to obtain signal P2 with w [kM], signal P1 is added with signal P2, due to generating s_res_
In the operation of sum [kM] and p_res_sum [kM], step factor is amplified 2expTimes, so the LMS for obtaining final output is missed
Poor correction signal is also amplified 2expTimes, i.e., output result is w [(k+1) M] * 2exp:
w[(k+1)M]*2exp=w [kM] * s_res_sum [kM]+p_res_sum [kM]；
S5. by the result w of adder three [(k+1) M] * 2expAfter carrying out division arithmetic by way of moving to right, obtain final
Output signal w [(k+1) M].
The step S2 includes following sub-step:
S21. by signal d [n] carry out serioparallel exchange, obtain d [kM], d [kM+1] ... .d [kM+m] ... d [kM+M-1]；Its
Middle m is 0 to the integer between M-1, and M indicates the signal number that serioparallel exchange obtains, i.e. the branch number of concurrent operation；
S22. by signal x [n] carry out serioparallel exchange, obtain x [kM], x [kM+1] ... .x [kM+m] ... x [kM+M-1]；Its
Middle m is 0 to the integer between M-1, and M indicates the signal number that serioparallel exchange obtains, i.e. the branch number of concurrent operation；
S23. in each branch of concurrent operation circuit, binding signal u carries out operation to the signal that serioparallel exchange obtains,
Operation result is exported from the first operation output end of each concurrent operation branch and the second operation output end, wherein u represents step-length
The significance bit of factor scientific notation is realized the step factor u*2 of LMS operation-expAmplification 2expTimes ,-exp is power exponent.
The step S3 includes following sub-step:
S31. the signal of the first operation output end in each concurrent operation branch is added by first adder, obtains p_
Res_sum [kM], due to using the significance bit u of step factor scientific notation to carry out operation, therefore LMS in concurrent operation branch
The step factor u*2 of operation-expActually it is exaggerated 2expTimes, only significance bit u participates in operation, and obtained signal is actually
It is exaggerated 2expTimes:
S32. the second output terminal signal of each concurrent operation branch is added by second adder, obtained signal is same
Sample is exaggerated 2expTimes, and by subtracter operation, since subtrahend is amplified 2expTimes, therefore minuend is also required to same times of amplification
Number, it is therefore desirable to use 1*2expThe signal for being added and obtaining is subtracted, is obtained s_res_sum [kM]::
The w [kM] passes through d type flip flop three by the LMS error correction signal w [(k+1) M] of last final output
Reason obtains.
Further, in formula w [(k+1) M] * 2expIt is real in=w [kM] * s_res_sum [kM]+p_res_sum [kM]
Operation amplifier result expands 2 on borderexpTimes；Final output result is needed divided by 2 in the applicationexp, or by multiplied by 2-exp, this amplification is offset by moving to right.
It is converted the beneficial effects of the present invention are: the present invention first passes through serial-parallel conversion circuit, then passes through concurrent operation electricity
Road and result generative circuit are calculated, and the data transfer rate of all variables all reduces M times than original input data rate, while parallel
Computing circuit can carry out corresponding pipeline operation according to the realization speed of circuit, so as to avoid this maximum portion of operand
It is divided into the bottleneck that system for restricting realizes speed.
Detailed description of the invention
Fig. 1 is the application block diagram that LMS algorithm corrects the gain of adc circuit amplifier；
Fig. 2 is the principle of the present invention block diagram；
Fig. 3 is the physical circuit figure of concurrent operation circuit and result generative circuit.
Specific embodiment
Technical solution of the present invention is described in further detail with reference to the accompanying drawing, but protection scope of the present invention is not limited to
It is as described below.
As shown in Figure 1, passing through the input terminal in ADC using the application block diagram of LMS algorithm correction adc circuit amplifier gain
The signal d [n] known is added, then the output x [n] of ADC and d [n] are subjected to related operation, the opamp_ in figure can be calculated
Gain value, i.e. amplifier gain.
As shown in Fig. 2, a kind of LMS error correcting system applied to high-speed ADC, including serial-parallel conversion circuit, parallel fortune
Calculate circuit and result generative circuit；The output end and concurrent operation circuit connection of the serial-parallel conversion circuit, as a result generate electricity
The output end and concurrent operation circuit connection on road；Serial-parallel conversion circuit is used for the input sample signal of ADC and sampling output letter
Number serioparallel exchange is carried out, obtains the ADC sampled input signal and ADC sampled output signal of multichannel, concurrent operation circuit is used for will
The signal that serioparallel exchange obtains carries out concurrent operation, and further place is done in the output that as a result generative circuit receives concurrent operation circuit
Reason, and realize the output of error correction signal.
It is big in LMS algorithm since the data transfer rate of high-speed ADC circuit is usually several hundred MHz even GHz or more in the application
The data operation of amount high-bit width can not be directly realized by so high data throughput, so must be introduced into serial-parallel conversion circuit,
Input data rate is reduced.
As shown in figure 3, the concurrent operation circuit includes multiple concurrent operation branches, each concurrent operation branch is corresponding
In ADC sampled input signal all the way and ADC sampled output signal；The output end of each concurrent operation branch generates electricity with result
Road connection.
The concurrent operation branch include ADC sampled input signal parallel input terminal, sampled output signal parallel input terminal,
First operation output end, the second operation output end and four multipliers；
The two-way input terminal of first multiplier respectively with ADC sampled input signal parallel input terminal and sampled output signal simultaneously
The connection of row input terminal, the output end of the first multiplier connect with the input terminal all the way of third multiplier, third multiplier it is another
Road input terminal connection signal u, the output end of third multiplier are connect with the first operation output end；
The two-way input terminal of second multiplier is connect with sampled output signal parallel input terminal, the output of the second multiplier
End is connect with the input terminal all the way of the 4th multiplier, the another way input terminal connection signal u of the 4th multiplier, the 4th multiplier
Output end is connect with the second operation output end.
The result generative circuit includes adder one, adder two, adder three, subtracter, d type flip flop one, D touching
Send out device two, d type flip flop three, divider and the 5th multiplier；The input terminal of the adder one respectively with each concurrent operation branch
The first operation output end on road connects, and the output end of adder one passes through the first via input terminal of d type flip flop one and adder three
Connection；The input terminal of the adder two is connect with the second operation output end of each concurrent operation branch respectively, adder two
Output end and the negative input end of subtracter connect, the positive input of subtracter terminates 1*2expSignal, the output end and D of subtracter
Trigger two connects, and the output end of d type flip flop two is connect with the first via input terminal of the 5th multiplier, and the second of the 5th multiplier
Road input terminal is connect with the output end of d type flip flop three, and the output end of multiplier is connect with the second road input terminal of adder three, is added
The output end of musical instruments used in a Buddhist or Taoist mass three is connect with divider, which fixes (divisor 2exp), divider output end was both triggered with D
The connection of three input terminal of device, while also being connect with the output end of result generative circuit, as final LMS error correction signal.
From figure 3, it can be seen that each concurrent operation branch calculates separately the corresponding p_res variable and s_ of current input
Res variable, the input data rate of concurrent operation branch are M/mono- of original data rate, so p_res variable and s_res become
The arithmetic speed of amount can be greatly lowered, and circuit is facilitated to realize.
In the result generative circuit, the signal w [kM] of the second road input terminal of the 5th multiplier input by it is last most
The LMS error correction signal exported eventually is obtained by the processing of d type flip flop three.
A kind of bearing calibration of the LMS error correcting system applied to high-speed ADC, comprising the following steps:
S1. the sampled input signal d [n] and sampled output signal x [n] of ADC are obtained；
S2. signal d [n] and signal x [n] is subjected to serioparallel exchange, and u pairs of binding signal in each concurrent operation branch
The signal that serioparallel exchange obtains carries out operation, and u represents the significance bit of step factor scientific notation, i.e., by the step-length of LMS operation
Factor u*2-expAmplification 2expU can be obtained again；
S3. the signal of the first operation output end in each concurrent operation branch is added, is obtained p_res_sum [kM], it will
The second output terminal signal of each concurrent operation branch is added, and is handled by subtracter, and signal s_res_sum [kM] is obtained；
S4., signal P1 is obtained after p_res_sum [kM] to be passed through to the processing of d type flip flop one；S_res_sum [kM] is passed through
It after the processing of d type flip flop two, is multiplied to obtain signal P2 with w [kM], signal P1 is added with signal P2, due to generating s_res_
In the operation of sum [kM] and p_res_sum [kM], step factor is amplified 2expTimes, so the LMS for obtaining final output is missed
Poor correction signal is also amplified 2expTimes, i.e., output result is w [(k+1) M] * 2exp:
w[(k+1)M]*2exp=w [kM] * s_res_sum [kM]+p_res_sum [kM]；
S5. by the result w of adder three [(k+1) M] * 2expAfter carrying out division arithmetic by way of moving to right, obtain final
Output signal w [(k+1) M].
Wherein s_res_sum [kM] and p_res_sum [kM] are unrelated with w [kM], can be carried out in advance according to input data solely
Vertical operation, i.e., realized by the adder in concurrent operation branch combination result generative circuit.
The step S2 includes following sub-step:
S21. by signal d [n] carry out serioparallel exchange, obtain d [kM], d [kM+1] ... .d [kM+m] ... d [kM+M-1]；Its
Middle m is 0 to the integer between M-1, and M indicates the signal number that serioparallel exchange obtains, i.e. the branch number of concurrent operation；
S22. by signal x [n] carry out serioparallel exchange, obtain x [kM], x [kM+1] ... .x [kM+m] ... x [kM+M-1]；Its
Middle m is 0 to the integer between M-1, and M indicates the signal number that serioparallel exchange obtains, i.e. the branch number of concurrent operation；S23. exist
In each branch of concurrent operation circuit, binding signal u carries out operation to the signal that serioparallel exchange obtains, from each concurrent operation
First operation output end of branch and the second operation output end export operation result；Wherein u represents step factor scientific notation
Significance bit, realize the step factor u*2 of LMS operation-expAmplification 2expTimes ,-exp is power exponent.
The step S3 includes following sub-step:
S31. the signal of the first operation output end in each concurrent operation branch is added by first adder, obtains p_
Res_sum [kM], due to using the significance bit u of step factor scientific notation to carry out operation, therefore LMS in concurrent operation branch
The step factor u*2 of operation-expActually it is exaggerated 2expTimes, only significance bit u participates in operation, and obtained signal also amplifies
2expTimes:
S32. the second output terminal signal of each concurrent operation branch is added by second adder, obtained signal is same
Sample is exaggerated 2expTimes, and by subtracter operation, since subtrahend is amplified 2expTimes, therefore minuend is also required to same times of amplification
Number, uses 1*2expThe signal for being added and obtaining is subtracted, is obtained s_res_sum [kM]:
The w [kM] passes through d type flip flop three by the LMS error correction signal w [(k+1) M] of last final output
Reason obtains.
Further, in formula w [(k+1) M] * 2expIt is real in=w [kM] * s_res_sum [kM]+p_res_sum [kM]
Operation amplifier result expands 2 on borderexpTimes；Final output result is needed divided by 2 in the applicationexp, or by multiplied by 2-exp, this amplification is offset by moving to right.
Claims (7)
1. a kind of LMS error correcting system applied to high-speed ADC, it is characterised in that: including serial-parallel conversion circuit, concurrent operation
Circuit and result generative circuit；The output end and concurrent operation circuit connection of the serial-parallel conversion circuit, concurrent operation circuit
Output end connect with result generative circuit；Serial-parallel conversion circuit is used to carry out the input signal of ADC and sampled output signal
Serioparallel exchange obtains the ADC input signal and ADC sampled output signal of multichannel, and concurrent operation circuit is for obtaining serioparallel exchange
The signal arrived carries out concurrent operation, and the output that as a result generative circuit receives concurrent operation circuit is further processed, and realizes mistake
The output of poor correction signal；
The concurrent operation circuit includes multiple concurrent operation branches, and each concurrent operation branch is inputted corresponding to ADC all the way
Signal and ADC sampled output signal；The output end of each concurrent operation branch is connect with result generative circuit；
The concurrent operation branch includes ADC input signal parallel input terminal, ADC sampled output signal parallel input terminal, first
Operation output end, the second operation output end and four multipliers；
The two-way input terminal of first multiplier is defeated parallel with ADC input signal parallel input terminal and ADC sampled output signal respectively
Enter end connection, the output end of the first multiplier is connect with the input terminal all the way of third multiplier, and the another way of third multiplier is defeated
Enter to hold connection signal u, the output end of third multiplier is connect with the first operation output end；
The two-way input terminal of second multiplier is connect with sampled output signal parallel input terminal, the output end of the second multiplier with
The input terminal all the way of 4th multiplier connects, the another way input terminal connection signal u of the 4th multiplier, the output of the 4th multiplier
End is connect with the second operation output end.
2. a kind of LMS error correcting system applied to high-speed ADC according to claim 1, it is characterised in that: described
As a result generative circuit includes adder one, adder two, adder three, subtracter, d type flip flop one, d type flip flop two, d type flip flop
Three, divider and the 5th multiplier；The input terminal of the adder one is defeated with the first operation of each concurrent operation branch respectively
The output end of outlet connection, adder one is connect by d type flip flop one with the first via input terminal of adder three；The adder
Two input terminal is connect with the second operation output end of each concurrent operation branch respectively, the output end and subtracter of adder two
Negative input end connection, the positive input of subtracter terminates 1*2expThe output end of signal, subtracter is connect with d type flip flop two, D touching
The output end of hair device two is connect with the first via input terminal of the 5th multiplier, and the second road input terminal and D of the 5th multiplier trigger
The output end of device three connects, and the output end of the 5th multiplier is connect with the second road input terminal of adder three, adder three it is defeated
Outlet is connect with divider, which fixes, and divider output end was both connect with three input terminal of d type flip flop, while
It is connect with the output end of result generative circuit, as final LMS error correction signal.
3. a kind of LMS error correcting system applied to high-speed ADC according to claim 2, it is characterised in that: the knot
In fruit generative circuit, the signal w [kM] of the second road input terminal of the 5th multiplier input by last final output LMS error
Correction signal is obtained by the processing of d type flip flop three.
4. a kind of correction of LMS error correcting system applied to high-speed ADC as described in any one of claims 1 to 3
Method, it is characterised in that: the following steps are included:
S1. the sampled input signal d [n] and sampled output signal x [n] of ADC are obtained；
S2. signal d [n] and signal x [n] are subjected to serioparallel exchange, and in each concurrent operation branch binding signal u to string simultaneously
The signal being converted to carries out concurrent operation, and u represents the significance bit of step factor scientific notation, i.e., by the step-length of LMS operation
Factor u*2-expAmplification 2expU can be obtained again；
S3. the signal of the first operation output end in each concurrent operation branch is added, obtains p_res_sum [kM], it will be each
The second output terminal signal of concurrent operation branch is added, and is handled by subtracter, and signal s_res_sum [kM] is obtained；
S4., signal P1 is obtained after p_res_sum [kM] to be passed through to the processing of d type flip flop one；S_res_sum [kM] is touched by D
After sending out the processing of device two, it is multiplied to obtain signal P2 with w [kM], signal P1 is added with signal P2, obtains amplification 2expLMS again is missed
Difference correction output signal w [(k+1) M] * 2exp:
w[(k+1)M]*2exp=w [kM] * s_res_sum [kM]+p_res_sum [kM]；
S5. by w [(k+1) M] * 2expAfter carrying out division arithmetic by way of moving to right, final output signal w [(k+1) M] is obtained.
5. a kind of bearing calibration of LMS error correcting system applied to high-speed ADC according to claim 4, feature
Be: the step S2 includes following sub-step:
S21. by signal d [n] carry out serioparallel exchange, obtain d [kM], d [kM+1] ... .d [kM+m] ... d [kM+M-1]；Wherein m
It is 0 to the integer between M-1, M indicates the signal number that serioparallel exchange obtains, i.e. the branch number of concurrent operation；
S22. by signal x [n] carry out serioparallel exchange, obtain x [kM], x [kM+1] ... .x [kM+m] ... x [kM+M-1]；Wherein m
It is 0 to the integer between M-1, M indicates the signal number that serioparallel exchange obtains, i.e. the branch number of concurrent operation；
S23. in each branch of concurrent operation circuit, the signal that binding signal u obtains serioparallel exchange carries out operation, from every
First operation output end of a concurrent operation branch and the second operation output end export operation result, and wherein u represents step factor
The significance bit of scientific notation is realized the step factor u*2 of LMS operation-expAmplification 2expTimes.
6. a kind of bearing calibration of LMS error correcting system applied to high-speed ADC according to claim 4, feature
Be: the step S3 includes following sub-step:
S31. the signal of the first operation output end in each concurrent operation branch is added by first adder, obtains p_res_
Sum [kM]:
S32. the second output terminal signal of each concurrent operation branch is added by second adder, and by subtracter, used
1*2expThe signal for being added and obtaining is subtracted, is obtained s_res_sum [kM]:
7. a kind of bearing calibration of LMS error correcting system applied to high-speed ADC according to claim 4, feature
Be: the w [kM] is handled by the LMS error correction signal w [(k+1) M] of last final output by third d type flip flop
It obtains.
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