CN106357335B - A kind of signal time delay method of adjustment and device - Google Patents
A kind of signal time delay method of adjustment and device Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of signal time delay methods of adjustment, comprising: obtains the first delay information, the first delay information includes at least the first integer delay information and the first fractional delays information；The second reference information after the first reference information and IQ correction before obtaining t moment signal IQ correction；The second delay information is determined according to first reference information and second reference information；The adjustment of decimal time delay is carried out to the signal of preset time after the t moment according to the first fractional delays information and the second delay information.The embodiment of the present invention further simultaneously discloses a kind of signal time delay adjustment device.
Description
Technical Field
The present invention relates to signal adjustment technologies in the field of optical communications, and in particular, to a method and an apparatus for adjusting signal delay.
Background
With the increasing of internet data services, 10G and 40G optical transmission cannot meet the increasing demand of current data services, and future transmission networks and metropolitan area networks will be developed towards 100G or even higher rates. The problems of chromatic dispersion, polarization film dispersion, strong filtering effect, misalignment of lane signal time delay and the like can be generated in optical signal transmission, and the delay of the lane signal in the optical transmission process mainly comes from a transmitting end device, an optical fiber and a receiving end device.
The delay compensation method in the prior art comprises transmitting end pre-compensation and post-compensation, wherein the transmitting end pre-compensation mainly solves the time delay caused by a transmitting end device, and the post-compensation mainly solves the time delay caused by an optical fiber and a receiving end device. However, the adverse effect of unstable lane signal delay caused by the non-ideal characteristics of the device and the long-distance optical path on the signal in the long-distance optical transmission process of 100G is more obvious than that of 10G and 40G, as shown in fig. 1, while the delay compensation in the prior art can only perform fixed delay compensation, i.e. fixed integer delay adjustment and fractional delay adjustment, and cannot meet the delay compensation with high precision under 100G.
Disclosure of Invention
In order to solve the foregoing technical problems, embodiments of the present invention desirably provide a method and an apparatus for adjusting a signal delay, which can dynamically adjust a delay of a signal and improve accuracy of delay adjustment.
The technical scheme of the invention is realized as follows:
the embodiment of the invention provides a signal time delay adjusting method, which comprises the following steps:
acquiring first delay information, wherein the first delay information at least comprises first integer delay information and first fractional delay information;
acquiring first reference information before IQ correction and second reference information after IQ correction of a signal at a time t;
determining second delay information according to the first reference information and the second reference information;
and performing decimal time delay adjustment on the signal of preset time after the time t according to the first decimal delay information and the second delay information.
Wherein the signals comprise at least an I signal and a Q signal;
the acquiring first reference information before IQ correction and second reference information after IQ correction of the signal at the time t includes:
and selecting an I reference point before IQ correction of the I signal at the t moment, selecting a Q reference point before IQ correction of the Q signal at the t moment, and selecting a reference point after IQ correction of the signal at the t moment.
Wherein determining second delay information according to the first reference information and the second reference information comprises:
carrying out early gate interpolation calculation on the I reference point to determine an early gate point, and carrying out late gate interpolation calculation on the I reference point to determine a late gate point;
carrying out early gate IQ correction calculation according to the Q reference point and the early gate point, and carrying out late gate IQ correction calculation according to the Q reference point and the late gate point;
carrying out difference multiplication calculation on the early gate point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a first average value;
carrying out difference multiplication calculation on the delay point, accumulating the results of the difference multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a second average value;
carrying out differential multiplication calculation on the IQ corrected reference point, accumulating the results of the differential multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a third average value;
and comparing the first average value, the second average value and the third average value with a preset threshold value to determine second delay information.
Wherein, the adjusting the decimal time delay of the signal of the preset time after the time t according to the first decimal delay information and the second delay information includes:
and determining a delay filter coefficient according to the first decimal delay information and the second delay information, and performing decimal delay adjustment on a signal of preset time after the time t according to the delay filter coefficient.
Further, the method further comprises:
and performing integer time delay adjustment on the signal of preset time after the time t according to the first integer delay information.
The embodiment of the invention also provides a signal delay adjusting device, which comprises: the device comprises a first acquisition unit, a second acquisition unit, a determination unit and an adjustment unit; wherein,
the first obtaining unit is configured to obtain first delay information, where the first delay information at least includes first integer delay information and first fractional delay information;
the second obtaining unit is used for obtaining first reference information before IQ correction of the signal at the time t and second reference information after IQ correction;
the determining unit is configured to determine second delay information according to the first reference information and the second reference information;
and the adjusting unit is used for carrying out decimal time delay adjustment on the signal of preset time after the time t according to the first decimal delay information and the second delay information.
Wherein the signals comprise at least an I signal and a Q signal;
the second obtaining unit is specifically configured to select an I reference point before IQ correction of the I signal at the time t, select a Q reference point before IQ correction of the Q signal at the time t, and select a reference point after IQ correction of the Q signal at the time t.
The determining unit is specifically configured to perform early gate interpolation calculation on the I reference point to determine an early gate point, and perform late gate interpolation calculation on the I reference point to determine a late gate point; carrying out early gate IQ correction calculation according to the Q reference point and the early gate point, and carrying out late gate IQ correction calculation according to the Q reference point and the late gate point; then, carrying out difference multiplication calculation on the early gate point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a first average value; carrying out difference multiplication calculation on the delay point, accumulating the results of the difference multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a second average value; carrying out differential multiplication calculation on the IQ corrected reference point, accumulating the results of the differential multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a third average value; and comparing the first average value, the second average value and the third average value with a preset threshold value to determine second delay information.
The adjusting unit is specifically configured to determine a delay filter coefficient according to the first fractional delay information and the second delay information, and perform fractional delay adjustment on a signal at a preset time after the time t according to the delay filter coefficient.
Further, the adjusting unit is further configured to perform integer time delay adjustment on the signal at the preset time after the time t according to the first integer delay information.
The signal delay adjusting method and device provided by the embodiment of the invention obtain first delay information, wherein the first delay information at least comprises first integer delay information and first decimal delay information; acquiring first reference information before IQ correction and second reference information after IQ correction of a signal at a time t; determining second delay information according to the first reference information and the second reference information; and performing decimal time delay adjustment on the signal of preset time after the time t according to the first decimal delay information and the second delay information. The signal delay adjusting method and device provided by the embodiment of the invention realize real-time updating of the delay information by acquiring the second delay information in real time and recalculating the delay filter coefficient by the second delay information and the first fractional delay information, thereby realizing dynamic adjustment of the delay of the signal, improving the accuracy of delay adjustment and further meeting the requirement of delay adjustment of an optical transmission system with 100G or even higher information content.
Drawings
FIG. 1 is a schematic diagram of a prior art signal delay adjustment;
fig. 2 is a first flowchart of a delay adjustment method according to an embodiment of the present invention;
fig. 3 is a first schematic diagram illustrating signal delay adjustment according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a method for determining delay information according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a signal delay adjustment according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of a signal delay adjustment method according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating an early gate-late gate interpolation operation according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a signal delay adjusting apparatus according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Example one
An embodiment of the present invention provides a method for adjusting a signal delay, as shown in fig. 2, the method includes:
step 101, a signal delay adjusting device obtains first delay information, where the first delay information at least includes first integer delay information and first fractional delay information.
Specifically, the signal delay adjusting apparatus may determine the first delay information by a hardware or software method (e.g., chip scaling). As shown in fig. 3, the first delay information is generally signal fixed delay information caused by a receiving device, where the first delay information at least includes first integer delay information and first fractional delay information, and the signal after t time may be subjected to integer delay adjustment according to the first integer delay information, where the delay information may be understood as a delay amount, and the integer delay adjustment may be specifically adjusted in units of clock cycles by buffering signal sample values.
Step 102, the signal delay adjusting device obtains first reference information before IQ correction of the signal at time t and second reference information after IQ correction.
Wherein the signals include at least an I signal and a Q signal, the I signal being 128 data-parallel and the Q signal also being 128 data-parallel. As shown in fig. 3, the signal delay adjusting device selects an I reference point before IQ correction of the I signal at the time t, selects a Q reference point before IQ correction of the Q signal at the time t, and selects a reference point after IQ correction of the signal at the time t.
In signal analysis, the signal is usually subjected to vector decomposition, that is, the signal is decomposed into two components with the same frequency and the same peak amplitude but with 90-degree phase difference. The IQ signals are two paths of orthogonal signals.
Step 103, the signal delay adjusting device determines second delay information according to the first reference information and the second reference information.
Specifically, as shown in fig. 4, the signal delay adjusting device performs an early gate interpolation calculation on the I reference point to determine an early gate point, performs a late gate interpolation calculation on the I reference point to determine a late gate point, performs an early gate IQ correction calculation on the Q reference point and the early gate point obtained by the early gate interpolation calculation, performs a late gate IQ correction calculation on the Q reference point and the late gate point obtained by the late gate interpolation calculation, and further performs a differential multiplication, an accumulation, and an averaging calculation on the early gate point, the late gate point, and the reference point obtained after the IQ correction, respectively, that is, the early gate point is subjected to the differential multiplication calculation, the results obtained by the differential multiplication calculation are accumulated within a preset clock length, and then the accumulated results are averaged to obtain a first average value; carrying out difference multiplication calculation on the delay points, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a second average value; carrying out difference multiplication calculation on the IQ corrected reference point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a third average value; and comparing and judging the first average value, the second average value and the third average value with a preset threshold value, and gradually increasing or decreasing step size adjustment quantity (step) according to a judgment result to determine second delay information. Wherein the preset threshold value and the long adjustment amount (step) are determined by simulation experience values.
It should be noted that, the IQ correction method may use an existing schmitt orthogonal algorithm (GSOP), or may use another method that can implement IQ correction, and the embodiment of the present invention is not limited to this.
And step 104, the signal delay adjusting device performs decimal delay adjustment on the signal of preset time after the time t according to the first decimal delay information and the second delay information.
Specifically, as shown in fig. 3, the signal delay adjusting device determines a delay filter coefficient according to the first fractional delay information and the second delay information, and performs fractional delay adjustment on the signal at a preset time after the time t according to the delay filter coefficient. As shown in fig. 3 and 5, when the signal is in the transmission process, the second delay amount is updated in real time according to the dynamic tracking feedback amount, which can be understood as a dynamic delay tracking process, thereby implementing the dynamic adjustment of the delay of the signal.
The signal after the preset time t may be understood as a signal after the time t + △ t, where the preset time △ t may be fixed or variable, and this embodiment is not limited thereto.
The signal delay adjusting method provided by the embodiment of the invention realizes real-time updating of the delay information by acquiring the second delay information in real time and recalculating the delay filter coefficient by the second delay information and the first fractional delay information, thereby realizing dynamic signal delay adjustment and improving the accuracy of delay adjustment.
Example two
An embodiment of the present invention provides a method for adjusting a signal delay, as shown in fig. 6, the method includes:
step 201, a signal delay adjusting device obtains first delay information, where the first delay information at least includes first integer delay information and first fractional delay information.
Specifically, the signal delay adjusting apparatus may determine the first delay information by a hardware or software method (e.g., chip scaling). As shown in fig. 3, the first delay information is generally signal fixed delay information caused by the receiving device, wherein the first delay information at least includes first integer delay information and first fractional delay information, the delay information can be understood as a delay amount, and the integer delay adjustment is adjusted by buffering signal sample values in units of clock cycles.
Step 202, the signal delay adjusting device selects an I reference point before IQ correction of the I signal at the time t, selects a Q reference point before IQ correction of the Q signal at the time t, and selects a reference point after IQ correction of the signal at the time t.
Wherein the signals include at least an I signal and a Q signal, the I signal being 128 data-parallel and the Q signal also being 128 data-parallel. In signal analysis, the signal is usually subjected to vector decomposition, that is, the signal is decomposed into two components with the same frequency and the same peak amplitude but with a phase difference of 90 degrees. The IQ signals are two paths of orthogonal signals.
For example, a certain two adjacent points in the middle of parallel data of the I-path signal and the Q-path signal in the same polarization state may be selected as reference points, the reference point selected for the I-path signal is an I-reference point, the reference point selected for the Q-path signal is a Q-reference point, and then interpolation calculation may be performed on the reference points of the I-path signal.
Step 203, the signal delay adjusting device number delay adjusting device performs early gate interpolation calculation on the I reference point to determine an early gate point, and performs late gate interpolation calculation on the I reference point to determine a late gate point; carrying out early gate IQ correction calculation according to the Q reference point and the early gate point, and carrying out late gate IQ correction calculation according to the Q reference point and the late gate point; carrying out difference multiplication calculation on the early gate point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a first average value; carrying out difference multiplication calculation on the delay point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a second average value; carrying out difference multiplication calculation on the IQ corrected reference point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a third average value; and comparing the first average value, the second average value and the third average value with a preset threshold value to determine second delay information.
Wherein the signals include at least an I signal and a Q signal. And the signal time delay adjusting device performs early gate interpolation calculation on the I reference point to determine an early gate point, and performs late gate interpolation calculation on the I reference point to determine a late gate point. The early gate interpolation and late gate interpolation can be understood as fixed fractional delay interpolation, for example, the delay amount can be 1/3 at 100G. Selecting some two adjacent points in the middle of parallel data of the I path signal and the Q path signal in the same polarization state as reference points, and performing interpolation calculation on the reference points of the I path signal. As shown in FIG. 7, for 6 of the 128 channels of I signal data, the interpolation will use the data points near the reference point, the early gate interpolation estimates the forward value of the reference point time of the I channel signal, and the late gate interpolation estimates the backward value of the reference point time of the I channel signal. The interpolation coefficient is calculated by software according to the delay amount, for example, the early gate delay amount may be-1/3, the late gate delay amount may be 1/3, and IQ correction is performed on the early gate and the late gate after interpolation, where the IQ correction method may use the existing GSOP algorithm, or may use other methods that can implement IQ correction.
Specifically, the IQ data of the early point, the reference point and the late point are multiplied differentially, and the differential multiplication formula is as follows:
dIQ＝(I[k+1]-I[k])*(Q[k+1]-Q[k])
where k and k +1 are two reference points in the parallel data. The early point, the reference point and the late point are all required to be subjected to difference multiplication calculation.
Furthermore, after the IQ data of the early gate point, the reference point and the late gate point are respectively multiplied differentially, the difference multiplication values are respectively accumulated within a preset clock length, wherein the preset clock length can be a certain clock length, for example, 128 paths of data in parallel under a 500MHz clock can be set to be 2^19 clock periods. Then, storing the respective accumulated values into 3 FIFOs with certain length, storing the accumulated values calculated for multiple periods in each FIFO, averaging the accumulated values in each FIFO, namely, adding all the values in the FIFOs, dividing the added values by the FIFO length, and dividing the obtained values by the accumulated period 2^19), and finally, comparing the three difference multiplied average values with a preset threshold value to judge the direction of time delay adjustment, namely, second time delay information.
The FIFO is an abbreviation of First Input First Output, the FIFO is a traditional in-sequence execution method, an instruction which enters First is completed and retired First, and then a second instruction is executed, and the FIFO is only used for data caching in the embodiment of the invention.
Specifically, the three average values are compared and judged with a preset threshold value, and step-up or step-down step adjustment amount (step) is gradually increased or decreased according to the judgment result to determine second delay information. Assume three averages: the first average value calculated according to the early gate point is s0, the third average value calculated according to the reference point after IQ correction is s1, the second average value calculated according to the late gate point is s2, and two preset threshold values are sth1 and sth2, wherein the preset threshold value and the step size adjustment quantity step are determined by simulation experience values, and the specific judgment conditions are as follows:
where dt is the estimated dynamic delay value, i.e. the second delay information.
It should be noted that, due to the non-ideality of the receiving device receiving the signal, the orthogonality between IQ signals is destroyed, and the amplitude consistency and orthogonality of the IQ signals should be ensured before the difference averaging in the tracking module.
And 204, determining a delay filter coefficient by the signal delay adjusting device according to the first decimal delay information and the second delay information, and performing decimal delay adjustment on the signal at the preset time after the time t according to the delay filter coefficient.
The signal after the preset time t may be understood as a signal after the time t + △ t, where the preset time △ t may be fixed or variable, and this embodiment is not limited thereto.
Specifically, as shown in fig. 3, the second delay information, i.e., the dynamic delay amount, is fed back to the first fractional delay information to form a new fractional delay amount, a group of delay filter coefficients is generated from the fractional delay amount, and after the delay filter coefficients are obtained, the fractional delay adjustment can be realized by multiplying the data points and the buffer points by the filter coefficients and summing the data points and the buffer points. The filter coefficients use a Farrow filter architecture (e.g., a 4-order structure at 100G). The Farrow matrix and coefficient calculation formula is as follows:
where u is a decimal adjustment amount, the filter coefficient calculated with this configuration has a characteristic that the coefficient c0 is c 3. This structure can be realized by a simple multiply-add structure, and the description of this embodiment is omitted here.
Specifically, in the 100G high data transmission process, a data parallel transmission and processing mode is generally adopted, and the delay filter is also realized in parallel by a multiplication and addition structure. Fractional delay adjustment requires buffering the last beat of sample values by the delay filter length minus one (e.g., the buffering point under a 4-order filter is 3 data after the previous beat).
Further, the method further comprises:
step 205, the signal delay adjusting device performs integer delay adjustment on the signal at the preset time after the time t according to the first integer delay information.
Specifically, the delay information may be understood as a delay amount. In the 100G high data transmission process, a data parallel transmission and processing mode is generally adopted, the tail end data of one beat can be cached in parallel data on each lane according to the adjustment range of the integer delay, the caching number is determined by the integer adjustment range, the adjusted integer number is generally supported, and finally, each sampling point of the parallel data is selected and output through the configured integer delay value to realize the integer delay adjustment.
The signal delay adjusting method provided by the embodiment of the invention realizes real-time updating of the delay information by acquiring the second delay information in real time and recalculating the delay filter coefficient by the second delay information and the first fractional delay information, thereby realizing dynamic signal delay adjustment and improving the accuracy of delay adjustment.
EXAMPLE III
An embodiment of the present invention provides a signal delay adjusting apparatus 1, as shown in fig. 8, where the apparatus 1 includes: a first acquisition unit 10, a second acquisition unit 11, a determination unit 12, an adjustment unit 13,
a first obtaining unit 10, configured to obtain first delay information, where the first delay information at least includes first integer delay information and first fractional delay information.
The second obtaining unit 11 is configured to obtain first reference information before IQ correction of the signal at time t and second reference information after IQ correction.
A determining unit 12, configured to determine second delay information according to the first reference information and the second reference information.
And the adjusting unit 13 is configured to perform decimal time delay adjustment on the signal of the preset time after the time t according to the first decimal delay information and the second decimal delay information.
Further, the signals include at least an I signal and a Q signal.
The second obtaining unit 11 is specifically configured to select an I reference point before IQ correction of the I signal at the time t, select a Q reference point before IQ correction of the Q signal at the time t, and select a reference point after IQ correction of the Q signal at the time t.
Further, the determining unit 12 is specifically configured to perform an early gate interpolation calculation on the I reference point to determine an early gate point, and perform a late gate interpolation calculation on the I reference point to determine a late gate point; carrying out early gate IQ correction calculation according to the Q reference point and the early gate point, and carrying out late gate IQ correction calculation according to the Q reference point and the late gate point; then, carrying out difference multiplication calculation on the early gate point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a first average value; carrying out difference multiplication calculation on the delay point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a second average value; carrying out difference multiplication calculation on the IQ corrected reference point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a third average value; and comparing the first average value, the second average value and the third average value with a preset threshold value to determine second delay information.
Further, the adjusting unit 13 is specifically configured to determine a delay filter coefficient according to the first fractional delay information and the second delay information, and perform fractional delay adjustment on a signal at a preset time after the time t according to the delay filter coefficient.
Further, the adjusting unit 13 is further configured to perform integer time delay adjustment on the signal at the preset time after the time t according to the first integer delay information.
Specifically, for understanding of the signal delay adjusting device provided in the embodiment of the present invention, reference may be made to the descriptions of the signal delay adjusting methods in the first embodiment and the second embodiment, and details of this embodiment are not repeated herein.
The signal delay adjusting device provided by the embodiment of the invention realizes real-time updating of delay information by acquiring the second delay information in real time and recalculating the delay filter coefficient by the second delay information and the first fractional delay information, thereby realizing dynamic signal delay adjustment and improving the accuracy of delay adjustment.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. A method for adjusting signal delay, the method comprising:
acquiring first delay information, wherein the first delay information at least comprises first integer delay information and first fractional delay information;
acquiring first reference information before IQ correction and second reference information after IQ correction of a signal at a time t; wherein the signals comprise at least an I signal and a Q signal; the first reference information comprises an I reference point before IQ correction and a Q reference point before IQ correction; the second reference information comprises an IQ corrected reference point;
carrying out early gate interpolation calculation on the I reference point to determine an early gate point, and carrying out late gate interpolation calculation on the I reference point to determine a late gate point;
carrying out early gate IQ correction calculation according to the Q reference point and the early gate point, and carrying out late gate IQ correction calculation according to the Q reference point and the late gate point;
carrying out difference multiplication calculation on the early gate point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a first average value;
carrying out difference multiplication calculation on the delay point, accumulating the results of the difference multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a second average value;
carrying out differential multiplication calculation on the IQ corrected reference point, accumulating the results of the differential multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a third average value;
comparing the first average value, the second average value and the third average value with a preset threshold value to determine second delay information;
and performing decimal time delay adjustment on the signal of preset time after the time t according to the first decimal delay information and the second delay information.
2. The method according to claim 1, wherein the obtaining first reference information before IQ correction and second reference information after IQ correction of the t-time signal comprises:
and selecting an I reference point before IQ correction of the I signal at the t moment, selecting a Q reference point before IQ correction of the Q signal at the t moment, and selecting a reference point after IQ correction of the signal at the t moment.
3. The method according to claim 1, wherein the performing fractional delay adjustment on the signal a preset time after the time t according to the first fractional delay information and the second delay information comprises:
and determining a delay filter coefficient according to the first decimal delay information and the second delay information, and performing decimal delay adjustment on a signal of preset time after the time t according to the delay filter coefficient.
4. The signal delay adjustment method according to any one of claims 1 to 3, further comprising:
and performing integer time delay adjustment on the signal of preset time after the time t according to the first integer delay information.
5. A signal delay adjustment apparatus, comprising: the device comprises a first acquisition unit, a second acquisition unit, a determination unit and an adjustment unit; wherein,
the first obtaining unit is configured to obtain first delay information, where the first delay information at least includes first integer delay information and first fractional delay information;
the second obtaining unit is used for obtaining first reference information before IQ correction of the signal at the time t and second reference information after IQ correction; wherein the signals comprise at least an I signal and a Q signal; the first reference information comprises an I reference point before IQ correction and a Q reference point before IQ correction; the second reference information comprises an IQ corrected reference point;
the determining unit is used for performing early gate interpolation calculation on the I reference point to determine an early gate point and performing late gate interpolation calculation on the I reference point to determine a late gate point; carrying out early gate IQ correction calculation according to the Q reference point and the early gate point, and carrying out late gate IQ correction calculation according to the Q reference point and the late gate point; then, carrying out difference multiplication calculation on the early gate point, accumulating the results of the difference multiplication calculation within a preset clock length, and then averaging the accumulated results to obtain a first average value; carrying out difference multiplication calculation on the delay point, accumulating the results of the difference multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a second average value; carrying out differential multiplication calculation on the IQ corrected reference point, accumulating the results of the differential multiplication calculation within the preset clock length, and then averaging the accumulated results to obtain a third average value; comparing the first average value, the second average value and the third average value with a preset threshold value to determine second delay information;
and the adjusting unit is used for carrying out decimal time delay adjustment on the signal of preset time after the time t according to the first decimal delay information and the second delay information.
6. The apparatus according to claim 5, wherein the second obtaining unit is specifically configured to select an I reference point before IQ correction of the I signal at the time t, select a Q reference point before IQ correction of the Q signal at the time t, and select a reference point after IQ correction of the Q signal at the time t.
7. The apparatus according to claim 5, wherein the adjusting unit is specifically configured to determine a delay filter coefficient according to the first fractional delay information and the second delay information, and perform fractional delay adjustment on the signal a preset time after the time t according to the delay filter coefficient.
8. The apparatus according to any one of claims 5 to 7, wherein the adjusting unit is further configured to perform integer delay adjustment on the signal at a preset time after the time t according to the first integer delay information.
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| CN112306943B (en) * | 2020-11-08 | 2023-03-07 | 西安电子工程研究所 | Idelay real-time adjustment method based on FPGA high-speed SerDes |
| CN115774658A (en) * | 2022-11-15 | 2023-03-10 | 中国华能集团清洁能源技术研究院有限公司 | Simulation system step size distribution method and system |
| CN115801147B (en) * | 2022-11-30 | 2023-09-22 | 珠海笛思科技有限公司 | Data communication processing method and system |
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Application publication date: 20170125 Assignee: Xi'an Chris Semiconductor Technology Co.,Ltd. Assignor: SANECHIPS TECHNOLOGY Co.,Ltd. Contract record no.: 2019440020036 Denomination of invention: Signal time delay adjusting method and device Granted publication date: 20190205 License type: Common License Record date: 20190619 |
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