A kind of signal time delay method of adjustment and device
Technical field
The present invention relates to optical communication field signal adjustment technology, more particularly, to a kind of signal time delay method of adjustment and
Device.
Background technology
With the continuous growth of Intemet data traffic, the optical transport of 10g, 40g can not meet current number
According to the increased requirement of business, future transmission net will be sent out towards the direction of 100g even more high speed with Metropolitan Area Network (MAN)
Exhibition.When can produce chromatic dispersion, polarizing coating dispersion, strong filter effect, lane signal in optical signal transmission
Prolong the problems such as do not line up, and the delay for the lane signal in optical transmission process, mostly come from transmitting terminal
Device, optical fiber and receiving terminal device.
The delay compensation method of prior art includes make a start precompensation, post-equalization, wherein, precompensation of making a start
Mainly solve the time delay that device causes of making a start, post-equalization mainly solves the time delay that optical fiber is caused with receiving end device.
However, due to device non-ideal characteristic and the long lane letter bringing away from light path in the long-distance optical transmission process of 100g
Number postpone the unstable harmful effect for signal become apparent from compared to 10g, 40g, as shown in figure 1,
And the delay compensation that delay compensation of the prior art can only be fixed, that is, the integer time delay adjustment fixed and
Decimal time delay adjusts it is impossible to meet high-precision delay compensation under 100g.
Content of the invention
For solving above-mentioned technical problem, embodiment of the present invention expectation provides a kind of signal time delay method of adjustment and dress
Put, the delay of signal can be dynamically adjusted, and improve the precision postponing adjustment.
The technical scheme is that and be achieved in that:
Embodiments provide a kind of signal time delay method of adjustment, methods described includes:
Obtain the first delay information, described first delay information at least includes the first integer delay information and first
Fractional delays information;
Obtain the first reference information before t signal iq correction and the second reference information after iq correction;
Second delay information is determined according to described first reference information and described second reference information;
Information is postponed to Preset Time after described t according to described first fractional delays information and described second
Signal carry out decimal time delay adjustment.
Wherein, described signal at least includes i signal and q signal;
The first reference information before described acquisition t signal iq correction and second after iq correction are with reference to letter
Breath, comprising:
Choose the i reference point before described t i signal iq correction, choose described t q signal iq school
Just front q reference point, chooses the reference point after described t signal iq correction.
Wherein, the second delay information is determined according to described first reference information and described second reference information, bag
Include:
Described i reference point is carried out early door interpolation calculation and determines early doors, described i reference point is entered walking retardation in children door
Interpolation calculation determines slow doors;
Carry out early door iq correction according to described q reference point and described early doors to calculate, according to described q reference
Point and described slow doors enter walking retardation in children door iq correction and calculate;
Described early doors is carried out difference multiplication calculate, in default clock length, described difference is multiplied and calculates
Result added up, then described accumulated result is averaged, obtain the first meansigma methodss;
Described slow doors is carried out difference multiplication calculate, in described default clock length, described difference is multiplied
The result calculating is added up, and then described accumulated result is averaged, and obtains the second meansigma methodss;
Reference point after described iq is corrected carries out difference multiplication and calculates, by institute in described default clock length
The result stating difference multiplication calculating is added up, and then described accumulated result is averaged, obtains the 3rd
Meansigma methodss;
Described first meansigma methodss, described second meansigma methodss, described 3rd meansigma methodss are entered with default threshold value
Row compares, and determines the second delay information.
Wherein, described according to described first fractional delays information and described second postpone information to described t
The signal of Preset Time carries out decimal time delay adjustment afterwards, comprising:
Delay filtering coefficient is determined according to described first fractional delays information and described second delay information, and root
According to described delay filtering coefficient, decimal time delay adjustment is carried out to the signal of Preset Time after described t.
Further, methods described also includes:
Integer time delay is carried out to the signal of Preset Time after described t according to described first integer delay information
Adjustment.
The embodiment of the present invention additionally provides a kind of signal time delay adjusting apparatus, and described device includes: the first acquisition
Unit, second acquisition unit, determining unit, adjustment unit;Wherein,
Described first acquisition unit, for obtaining the first delay information, described first delay information at least includes
First integer delay information and the first fractional delays information;
Described second acquisition unit, for obtaining the first reference information and iq before t signal iq correction
The second reference information after correction;
Described determining unit, for determining second according to described first reference information and described second reference information
Delay information;
Described adjustment unit, for postponing information to institute according to described first fractional delays information and described second
After stating t, the signal of Preset Time carries out decimal time delay adjustment.
Wherein, described signal at least includes i signal and q signal;
Described second acquisition unit, specifically for choosing the i reference point before described t i signal iq correction,
Choose the q reference point before described t q signal iq correction, after choosing described t signal iq correction
Reference point.
Wherein, described determining unit, determines early specifically for described i reference point is carried out early door interpolation calculation
Doors, described i reference point is entered walking retardation in children door interpolation calculation and determines slow doors;And according to described q reference point and
Described early doors carries out early door iq correction and calculates, and enters walking retardation in children door according to described q reference point and described slow doors
Iq correction calculates;Then described early doors is carried out difference multiplication to calculate, will be described in default clock length
The result that difference multiplication calculates is added up, and then described accumulated result is averaged, and obtains first flat
Average;Described slow doors is carried out difference multiplication calculate, by described difference phase in described default clock length
The result taking advantage of calculating is added up, and then described accumulated result is averaged, and obtains the second meansigma methodss;
Reference point after described iq is corrected carries out difference multiplication and calculates, by described difference in described default clock length
Split-phase takes advantage of the result of calculating to be added up, and then described accumulated result is averaged, and obtains the 3rd average
Value;Described first meansigma methodss, described second meansigma methodss, described 3rd meansigma methodss are entered with default threshold value
Row compares, and determines the second delay information.
Wherein, described adjustment unit, specifically for prolonging according to described first fractional delays information and described second
Information determines delay filtering coefficient late, and the letter to Preset Time after described t according to delay filtering coefficient
Number carry out decimal time delay adjustment.
Further, described adjustment unit, when being additionally operable to according to described first integer delay information to described t
After quarter, the signal of Preset Time carries out integer time delay adjustment.
Signal time delay method of adjustment provided in an embodiment of the present invention and device, obtain the first delay information, described
First delay information at least includes the first integer delay information and the first fractional delays information;Obtain t letter
The first reference information before number iq correction and the second reference information after iq correction;According to described first reference
Information and described second reference information determine the second delay information;According to described first fractional delays information and institute
Second delay information of stating carries out decimal time delay adjustment to the signal of Preset Time after t.The embodiment of the present invention
The signal time delay method of adjustment providing and device pass through real-time acquisition the second delay information, and second is postponed letter
Breath and the first fractional delays information recalculate delay filtering coefficient it is achieved that the real-time update of delayed data,
It is achieved thereby that dynamically adjusting the delay of signal, and improve the precision postponing adjustment, and then meet 100g
The time delay adjustment of even more high quantity of information optical transmission system.
Brief description
Fig. 1 is that the signal time delay of prior art adjusts schematic diagram;
Fig. 2 is time delay adjusting method schematic flow sheet one provided in an embodiment of the present invention;
Fig. 3 is that signal time delay provided in an embodiment of the present invention adjusts schematic diagram one;
Fig. 4 determines method schematic diagram for delayed data provided in an embodiment of the present invention;
Fig. 5 is that signal time delay provided in an embodiment of the present invention adjusts schematic diagram two;
Fig. 6 is signal time delay method of adjustment schematic flow sheet two provided in an embodiment of the present invention;
Fig. 7 is early Men Chimen interpolation arithmetic schematic diagram provided in an embodiment of the present invention;
Fig. 8 is signal time delay adjusting apparatus structural representation provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by.
Embodiment one
The embodiment of the present invention provides a kind of signal time delay method of adjustment, as shown in Fig. 2 the method includes:
Step 101, signal time delay adjusting apparatus obtain the first delay information, and described first postpones information at least
Including the first integer delay information and the first fractional delays information.
Specifically, signal time delay adjusting apparatus pass through hardware or the method (for example, chip calibration) of software can
To determine the first delay information.As shown in figure 3, this first delay information is usually caused by receiving device
Signal fixed delay information, wherein, this first delay information at least includes the first integer delay information and first
Fractional delays information, can carry out whole according to the first integer delay information to the signal of Preset Time after t
Number postpones adjustment, and delay information can be understood as retardation, and the adjustment of integer time delay specifically can be believed by caching
Number sample value was adjusted in units of the clock cycle.
Step 102, signal time delay adjusting apparatus obtain t signal iq correction before the first reference information and
The second reference information after iq correction.
Wherein, described signal at least includes i signal and q signal, and i signal is that 128 data are parallel, q
Signal is also that 128 data are parallel.As shown in figure 3, signal time delay adjusting apparatus choose described t i
I reference point before signal iq correction, chooses the q reference point before described t q signal iq correction, and
Choose the reference point after described t signal iq correction.
Wherein, in signal analysis, generally signal is carried out resolution of vectors, that is, signal decomposition is frequency
Rate is identical, peak amplitude is identical but two components of 90 degree of phase.Iq signal is the orthogonal letter of two-way
Number.
Step 103, signal time delay adjusting apparatus are according to described first reference information and described second reference information
Determine the second delay information.
Specifically, as shown in figure 4, described i reference point is carried out early door interpolation meter by signal time delay adjusting apparatus
Calculate and determine early doors, and described i reference point is entered walking retardation in children door interpolation calculation and determine slow doors, then, according to
The early doors of described q reference point and early door interpolation calculation carries out early door iq correction and calculates, and is joined according to described q
The slow doors of examination point and slow door interpolation calculation enters walking retardation in children door iq correction and calculates, further, by early doors, late
Reference point after doors and iq correction carries out difference multiplication respectively, adds up and be averaging calculating, you can to manage
Xie Wei, described early doors is carried out difference multiplication and calculates, and in default clock length, described difference is multiplied
The result calculating is added up, and then described accumulated result is averaged, and obtains the first meansigma methodss;Will
Described slow doors carries out difference multiplication and calculates, and the knot of the calculating that in default clock length, described difference is multiplied
Fruit is added up, and then described accumulated result is averaged, and obtains the second meansigma methodss;By described iq school
Reference point after just carries out difference multiplication and calculates, and in default clock length, the multiplication of described difference is calculated
Result is added up, and then described accumulated result is averaged, and obtains the 3rd meansigma methodss;By described
One meansigma methodss, described second meansigma methodss, described 3rd meansigma methodss and default threshold value are compared judgement,
According to judged result progressively increasing or decreasing step-length adjustment amount (step) to determine the second delay information.Wherein,
Predetermined threshold value and long adjustment amount (step) are to be determined by emulation empirical value.
It should be noted that iq bearing calibration can using existing Schmidt's orthogonal algorithm (gsop,
Gram-schmidt orthogonal procedure), it would however also be possible to employ the method that other can realize iq correction,
The embodiment of the present invention is not especially limited to this.
Step 104, signal time delay adjusting apparatus are according to described first fractional delays information and described second delay
Information carries out decimal time delay adjustment to the signal of Preset Time after described t.
Specifically, as shown in figure 3, signal time delay adjusting apparatus are according to described first fractional delays information and institute
Second delay information of stating determines delay filtering coefficient, and according to described delay filtering coefficient to described t after
The signal of Preset Time carries out decimal time delay adjustment.As shown in Fig. 3, Fig. 5, when signal is in transmitting procedure,
Second retardation is according to Dynamic tracing feedback amount real-time update, and it can be understood as the mistake of dynamic delay tracking
Journey, it is achieved thereby that dynamically adjust the delay of signal.
Wherein, after t the signal of Preset Time it is to be understood that signal after t+ △ t, when this is default
Between △ t can be fixing or change, the present embodiment does not limit to this.
Signal time delay method of adjustment provided in an embodiment of the present invention passes through real-time acquisition the second delay information, and will
Second delay information and the first fractional delays information recalculate delay filtering coefficient it is achieved that delayed data
Real-time update, it is achieved thereby that dynamically adjusting the delay of signal, and improves the precision postponing adjustment.
Embodiment two
The embodiment of the present invention provides a kind of signal time delay method of adjustment, as shown in fig. 6, the method includes:
Step 201, signal time delay adjusting apparatus obtain the first delay information, and described first postpones information at least
Including the first integer delay information and the first fractional delays information.
Specifically, signal time delay adjusting apparatus pass through hardware or the method (for example, chip calibration) of software can
To determine the first delay information.As shown in figure 3, this first delay information is usually caused by receiving device
Signal fixed delay information, wherein, this first delay information at least includes the first integer delay information and first
Fractional delays information, delay information can be understood as retardation, and buffered signal sampling point is passed through in the adjustment of integer time delay
Value was adjusted in units of the clock cycle.
Step 202, signal time delay adjusting apparatus choose the i reference point before described t i signal iq correction,
Choose the q reference point before described t q signal iq correction, after choosing described t signal iq correction
Reference point.
Wherein, described signal at least includes i signal and q signal, and i signal is that 128 data are parallel, q
Signal is also that 128 data are parallel.In signal analysis, generally signal is carried out resolution of vectors, that is,
By signal decomposition for frequency is identical, peak amplitude is identical but two components of 90 degree of phase.Iq signal
For the signal that two-way is orthogonal.
Exemplary, the centre in i road signal and q road signal parallel data in same polarization state can be chosen
Certain adjacent 2 points is reference point, and the reference point chosen in i road signal is i reference point, chooses in q road signal
Reference point be q reference point, then again interpolation calculation is carried out to the reference point of i road signal.
Described i reference point is carried out early door interpolation by step 203, signal time delay adjusting apparatus time delay adjusting apparatus
Calculate and determine early doors, described i reference point is entered walking retardation in children door interpolation calculation and determines slow doors;According to described q
Reference point and described early doors carry out early door iq correction and calculate, according to described q reference point and described slow doors
Enter walking retardation in children door iq correction to calculate;Described early doors is carried out difference multiplication calculate, will in default clock length
The described difference result calculating that is multiplied is added up, and then described accumulated result is averaged, and obtains the
One meansigma methodss;Described slow doors is carried out difference multiplication calculate, by described difference phase in default clock length
The result taking advantage of calculating is added up, and then described accumulated result is averaged, and obtains the second meansigma methodss;
Reference point after described iq is corrected carries out difference multiplication and calculates, by described difference phase in default clock length
The result taking advantage of calculating is added up, and then described accumulated result is averaged, and obtains the 3rd meansigma methodss;
Described first meansigma methodss, described second meansigma methodss, described 3rd meansigma methodss are compared with default threshold value
Relatively, determine the second delay information.
Wherein, described signal at least includes i signal and q signal.Described i is joined by signal time delay adjusting apparatus
Examination point carries out early door interpolation calculation and determines early doors, described i reference point is entered walking retardation in children door interpolation calculation and determines late
Doors.Early door interpolation calculation and slow door interpolation can be understood as fixed decimal and postpone interpolation calculation, for example, 100g
Lower retardation can be 1/3.Choose the centre in i road signal and q road signal parallel data in same polarization state
Adjacent 2 points is reference point, carries out interpolation calculation to the reference point of i road signal.As shown in fig. 7, believing for i
6 tunnels in number 128 circuit-switched data, interpolation calculation will use the data point near reference point, early door interpolating estimation
I road signal reference point time forward value, the slow door interpolating estimation i road signal reference point time is worth rearward.Interpolation system
Number is calculated according to retardation by software, and for example, early gate delay amount can be -1/3, and slow gate delay amount can
Think 1/3, after interpolation, iq correction is carried out to early doors and slow doors, wherein, iq bearing calibration can be using existing
Some gsop algorithms, it would however also be possible to employ the method that other can realize iq correction.
Specifically, make the difference split-phase to the iq data of early doors, reference point and slow doors respectively to take advantage of, difference is multiplied
Formula is as follows:
Diq=(i [k+1]-i [k]) * (q [k+1]-q [k])
Wherein, k and k+1 is two reference points in parallel data.Early doors, reference point are both needed to slow doors
Carry out difference multiplication to calculate.
Further, respectively the iq data of early doors, reference point and slow doors is made the difference after split-phase takes advantage of, and
Respectively difference multiplied value is added up in default clock length, wherein, default clock length can be certain
Clock length, for example, under 500mhz clock, 128 circuit-switched data may be configured as 2^19 clock cycle parallel.
Then, respective accumulated value is stored in 3 certain length fifo, each multiple computation of Period of fifo memory storage
Accumulated value, accumulated value in each fifo is averaged, that is, in fifo all values be added after divided by fifo
Length is again divided by accumulation period 2^19), finally, will be with pre-determined threshold by these three difference multiplication meansigma methodss
Value is compared the direction judging to determine time delay adjustment, i.e. the second delayed data.
Wherein, fifo is the abbreviation of first input first output, and First Input First Output is a kind of traditional
Sequentially execute method, the instruction being introduced into first completes and retires from office, and then just execution Article 2 instruction, at this
In bright embodiment, fifo only does data buffer storage and uses.
Specifically, above three meansigma methodss and predetermined threshold value are compared judgement, according to judged result by
Step increasing or decreasing step-length adjustment amount (step) is to determine the second delayed data.Assume that three meansigma methodss are:
The 3rd of reference point calculating after being s0, corrected according to iq according to the first meansigma methodss that early doors calculates is average
Being worth for s1, according to the second meansigma methodss that slow doors calculates is s2, and presetting two threshold values is sth1 and sth2,
Wherein, predetermined threshold value and step-length adjustment amount step determine by emulating empirical value, concrete Rule of judgment is as follows:
Wherein, dt is the dynamic delay value of estimation, i.e. the second delayed data.
It should be noted that normally due to accepting the imperfection accepting device of signal, orthogonal between iq
Property can be destroyed, in tracking module, difference should ensure that before being averaging that the amplitude of iq signal is consistent and orthogonality.
Step 204, signal time delay adjusting apparatus are according to described first fractional delays information and described second delay
Information determines delay filtering coefficient, and according to described delay filtering coefficient to Preset Time after described t
Signal carries out decimal time delay adjustment.
Wherein, after t the signal of Preset Time it is to be understood that signal after t+ △ t, when this is default
Between △ t can be fixing or change, the present embodiment does not limit to this.
Specifically, as shown in figure 3, the second delayed data is that dynamic deferred amount feeds back to the first fractional delays
In information, constitute new fractional delays amount, one group of delay filtering coefficient is produced by fractional delays amount, is prolonged
Late after filter factor, by data point and buffer are multiplied with filter factor summation, you can realize decimal and prolong
Adjust late.Filter factor adopts farrow filtering framework (for example, under 100g can be 4 stage structures).farrow
Matrix and coefficient formulas are as follows:
Wherein, u is decimal adjustment amount, has coefficient c0=c3's using the filter factor of this Structure Calculation
Characteristic.This structure can achieve, the present embodiment will not be described here by simply multiply-add structure.
Specifically, transmission and the process of data parallel can in the high data transmission procedure of 100g, typically be adopted
Mode, delay filter is also by multiply-add structure Parallel Implementation.The adjustment of decimal time delay needs the upper bat sample of caching
Point value, caching number subtracts one for delay filter length, and (for example, under 4 rank wave filter, buffer is after previous bat 3
Individual data).
Further, methods described also includes:
Step 205, signal time delay adjusting apparatus are according to described first integer delay information to pre- after described t
If the signal of time carries out integer time delay adjustment.
Specifically, delay information can be understood as retardation.Due in the high data transmission procedure of 100g, one
As can adopt the transmission of data parallel and processing mode, according to the adjusting range of integer delay, can be to every lane
On the upper bat endian data of parallel data caching, caching number determines by integer adjusting range, general support
The integer number of adjustment, the integer delay value finally by configuration selects to each sampling point of parallel data
Export and to realize integer delay adjustment.
Signal time delay method of adjustment provided in an embodiment of the present invention passes through real-time acquisition the second delay information, and will
Second delay information and the first fractional delays information recalculate delay filtering coefficient it is achieved that delayed data
Real-time update, it is achieved thereby that dynamically adjusting the delay of signal, and improves the precision postponing adjustment.
Embodiment three
The embodiment of the present invention provides a kind of signal time delay adjusting apparatus 1, as shown in figure 8, this device 1 includes:
First acquisition unit 10, second acquisition unit 11, determining unit 12, adjustment unit 13,
First acquisition unit 10, for obtaining the first delay information, described first delay information at least includes the
One integer delay information and the first fractional delays information.
Second acquisition unit 11, for obtaining the first reference information and iq school before t signal iq correction
The second reference information after just.
According to described first reference information and described second reference information, determining unit 12, for determining that second prolongs
Information late.
Adjustment unit 13, for postponing information to described according to described first fractional delays information and described second
After t, the signal of Preset Time carries out decimal time delay adjustment.
Further, described signal at least includes i signal and q signal.
Second acquisition unit 11, specifically for choosing the i reference point before described t i signal iq correction,
Choose the q reference point before described t q signal iq correction, after choosing described t signal iq correction
Reference point.
Further, it is determined that unit 12, determine specifically for described i reference point is carried out early door interpolation calculation
Early doors, described i reference point is entered walking retardation in children door interpolation calculation and determines slow doors;And according to described q reference point
Carry out early door iq correction with described early doors to calculate, the walking retardation in children is entered according to described q reference point and described slow doors
Door iq correction calculates;Then described early doors is carried out difference multiplication to calculate, by institute in default clock length
The result stating difference multiplication calculating is added up, and then described accumulated result is averaged, obtains first
Meansigma methodss;Described slow doors is carried out difference multiplication calculate, in default clock length, described difference is multiplied
The result calculating is added up, and then described accumulated result is averaged, and obtains the second meansigma methodss;Will
Reference point after described iq correction carries out difference multiplication and calculates, and in default clock length, described difference is multiplied
The result calculating is added up, and then described accumulated result is averaged, and obtains the 3rd meansigma methodss;Will
Described first meansigma methodss, described second meansigma methodss, described 3rd meansigma methodss are compared with default threshold value,
Determine the second delay information.
Further, adjustment unit 13, specifically for according to described first fractional delays information and described second
Delay information determines delay filtering coefficient, and according to delay filtering coefficient to Preset Time after described t
Signal carries out decimal time delay adjustment.
Further, adjustment unit 13, are additionally operable to according to described first integer delay information to described t
The signal of Preset Time carries out integer time delay adjustment afterwards.
Specifically, the understanding of signal time delay adjusting apparatus provided in an embodiment of the present invention may be referred to embodiment one
With the explanation of the signal time delay method of adjustment of embodiment two, the present embodiment will not be described here.
Signal time delay adjusting apparatus provided in an embodiment of the present invention pass through real-time acquisition the second delay information, and will
Second delay information and the first fractional delays information recalculate delay filtering coefficient it is achieved that delayed data
Real-time update, it is achieved thereby that dynamically adjusting the delay of signal, and improves the precision postponing adjustment.
Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or meter
Calculation machine program product.Therefore, the present invention can using hardware embodiment, software implementation or combine software and
The form of the embodiment of hardware aspect.And, the present invention can adopt and wherein include calculating one or more
Computer-usable storage medium (including but not limited to disk memory and the optical storage of machine usable program code
Device etc.) the upper computer program implemented form.
The present invention is with reference to method according to embodiments of the present invention, equipment (system) and computer program
Flow chart and/or block diagram describing.It should be understood that can be by computer program instructions flowchart and/or side
Each flow process in block diagram and/or the knot of the flow process in square frame and flow chart and/or block diagram and/or square frame
Close.Can provide these computer program instructions to general purpose computer, special-purpose computer, Embedded Processor or
The processor of other programmable data processing device with produce a machine so that by computer or other can
The instruction of the computing device of programming data processing equipment produces for realizing in one flow process or multiple of flow chart
The device of the function of specifying in flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions may be alternatively stored in and can guide computer or other programmable data processing device
So that being stored in this computer-readable memory in the computer-readable memory working in a specific way
Instruction produces the manufacture including command device, and this command device is realized in one flow process of flow chart or multiple stream
The function of specifying in journey and/or one square frame of block diagram or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, makes
Obtain and series of operation steps is executed on computer or other programmable devices to produce computer implemented place
Reason, thus the instruction of execution is provided for realizing in flow chart one on computer or other programmable devices
The step of the function of specifying in flow process or multiple flow process and/or one square frame of block diagram or multiple square frame.
The above, only presently preferred embodiments of the present invention, it is not intended to limit the protection model of the present invention
Enclose.