CN116455395B - Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus - Google Patents

Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus Download PDF

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CN116455395B
CN116455395B CN202310424061.XA CN202310424061A CN116455395B CN 116455395 B CN116455395 B CN 116455395B CN 202310424061 A CN202310424061 A CN 202310424061A CN 116455395 B CN116455395 B CN 116455395B
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quantization
switch
residual
voltage
capacitor array
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CN116455395A (en
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祝润坤
鲁文高
周飞
安泊伟
张雅聪
陈中建
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Peking University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention provides a pipelined successive approximation type analog-to-digital converter circuit, an analog-to-digital converter and electronic equipment, and relates to the technical field of integrated circuits, comprising: the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module; the residual quantization SAR module is used for performing successive approximation quantization on the residual voltage to obtain a residual quantization result. The invention reduces the problem that the sampling speed cannot be raised because the quantization of the full bit is required to be carried out in the same quantization period in the traditional high-precision SAR-ADC. The problem that error codes and comparison misjudgment are caused by incomplete signal establishment is solved; the problem of overhigh power consumption caused by overlarge capacitance value of the capacitors in the capacitor array in the traditional high-precision SAR-ADC is solved, and meanwhile, the probability of precision reduction caused by process production mismatch is reduced due to the reduction of the number of the capacitors.

Description

Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a pipeline successive approximation type analog-to-digital converter, an analog-to-digital converter, and an electronic device.
Background
At present, in the traditional high-precision SAR-ADC, full bit quantization is required in the same quantization period, and due to small single comparison period time margin, incomplete signal establishment causes error codes, comparison erroneous judgment and incapability of raising sampling speed.
In addition, the problems of high signal establishment precision, bandwidth, noise, large capacitance value in a capacitor array and the like in the SAR-ADC at medium and high speeds lead to higher power consumption, and meanwhile, the precision reduction probability caused by process production mismatch is improved.
Disclosure of Invention
In view of the above, the present invention provides a pipelined successive approximation type analog-to-digital converter, an analog-to-digital converter and an electronic device.
The embodiment of the invention provides a pipelined successive approximation type analog-to-digital conversion circuit, which comprises: a coarse quantization SAR module and a residual quantization SAR module;
in a coarse quantization stage, the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module;
the residual quantization SAR module comprises: a residual quantization capacitor array, a residual quantization logic unit, and a comparator;
in the residual quantization stage, the residual quantization capacitor array is used for integrating two paths of output currents to obtain two residual quantization integrated voltages and outputting the two residual quantization integrated voltages to the comparator, and performing successive approximation quantization according to the on-off condition of a residual quantization capacitor array switch to obtain a residual quantization result;
the comparator is used for comparing the magnitudes of two residual quantized integral voltages and outputting a first result signal to the residual quantized logic unit;
the residual quantization logic unit is used for generating a residual quantization control signal according to the first result signal so as to control the on-off of the residual quantization capacitor array switch;
the coarse quantization SAR module completes coarse quantization of the fully-differential input voltage in the current coarse quantization period, and simultaneously completes residual quantization of residual voltage in the previous coarse quantization period;
the capacitance value of the integrating capacitor in the coarse quantization SAR module is far smaller than that of the capacitor in the residual quantization capacitor array.
Optionally, the coarse quantization SAR module comprises: the device comprises a capacitive full-differential SAR ADC structure, a voltage-to-current amplifying unit, a coarse quantization logic unit, a judgment latch unit and a coarse quantization integration unit;
in the coarse quantization stage, the capacitive full-differential SAR ADC structure is configured to integrate the full-differential input voltage to obtain a positive input end voltage and a negative input end voltage, and output the positive input end voltage and the negative input end voltage to the positive input end and the negative input end of the voltage-to-current amplifying unit, respectively, and perform successive approximation quantization according to the on-off condition of a capacitive array switch in the capacitive full-differential SAR ADC structure, so as to obtain the coarse quantization result;
the voltage-to-current amplifying unit is used for converting and amplifying the positive input end voltage and the negative input end voltage into two paths of corresponding output currents and outputting the two paths of corresponding output currents to the coarse quantization integrating unit and the residual quantization SAR module;
the coarse quantization integration unit is used for integrating the two paths of output currents to obtain two integrated voltages and outputting the two integrated voltages to the judgment latch unit;
the judgment latch unit is used for comparing the magnitudes of the two coarse quantization integral voltages and outputting a second result signal to the coarse quantization logic unit;
and the coarse quantization logic unit is used for generating a coarse quantization control signal according to the second result signal so as to control the on-off of a capacitor array switch in the capacitor type full-differential SAR ADC structure.
Optionally, the residual quantization capacitor array includes: a first half unit and a second half unit;
the first half unit receives a first output current of the two paths of output currents, and the second half unit receives a second output current of the two paths of output currents;
the first half unit includes: the first residual quantization capacitor array, the second residual quantization capacitor array, the first switch, the second switch, the third switch, the fourth switch and the first reset switch;
the first end of the first switch receives the first output current, and the second end of the first switch is respectively connected with the second end of the first reset switch, the upper polar plate of the first residual quantized capacitor array, the upper polar plate of the second residual quantized capacitor array and the positive input end of the comparator;
the first end of the first reset switch is connected with the lower polar plate of the first residual error quantization capacitor array and grounded;
the lower polar plate of the second residual error quantification capacitor array is respectively connected with the second end of the second switch, the second end of the third switch and the second end of the fourth switch;
the first end of the second switch and the first end of the fourth switch are grounded;
the first end of the third switch is connected with the output end of the reference voltage selection module.
Optionally, the second half unit includes: a third residual quantization capacitor array, a fourth residual quantization capacitor array, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a second reset switch;
the first end of the fifth switch receives the second output current, and the second end of the fifth switch is respectively connected with the first end of the second reset switch, the upper polar plate of the third residual quantized capacitor array, the upper polar plate of the fourth residual quantized capacitor array and the negative input end of the comparator;
the second end of the second reset switch is connected with the lower polar plate of the third residual error quantization capacitor array and grounded;
the lower polar plate of the fourth residual quantization capacitor array is respectively connected with the first end of the sixth switch, the first end of the seventh switch and the first end of the eighth switch;
the second end of the fifth switch and the first end of the eighth switch are grounded;
the second end of the seventh switch is connected with the output end of the reference voltage selection module;
and the output end of the comparator is connected with the residual error quantization logic unit.
Optionally, the first residual quantization capacitor array and the first residual quantization capacitor arrayThe third residual quantization capacitor arrays each include: 2 n-k A unit capacitance;
the second residual quantization capacitor array and the fourth residual quantization capacitor array each include: 2 k A number of unit capacitors, n > k;
the sum of the number of the unit capacitors in the first residual quantized capacitor array and the number of the unit capacitors in the second residual quantized capacitor array is as follows: 2 n A unit capacitance;
the sum of the number of the unit capacitors in the third residual quantization capacitor array and the number of the unit capacitors in the fourth residual quantization capacitor array is as follows: 2 n A unit capacitance.
Optionally, the reference voltage selecting module is configured to select the reference voltage from 2 L Selecting any one of the reference voltages and outputting the selected reference voltage to a first end of the third switch and a second end of the seventh switch;
said arbitrary voltage V DAC The expression of (2) is:
in the above, V ref Representing the reference voltage.
Optionally, the first switch, the second switch, the fifth switch, and the sixth switch are simultaneously closed or simultaneously opened;
the first reset switch and the second reset switch are simultaneously closed or simultaneously opened;
the third switch and the eighth switch are simultaneously closed or simultaneously opened;
the fourth switch and the seventh switch are simultaneously closed or simultaneously opened;
wherein the residual quantization stage comprises: an integration stage and a quantization stage;
during the coarse quantization phase, the first switch is open;
during the integration phase, the first switch is closed;
the first reset switch is closed when the first switch is closed, and is opened after all unit capacitors in the residual quantized capacitor array are reset;
in the quantization stage, if the first output current is greater than the second output current, the fourth switch is closed, and the third switch is opened;
in the quantization stage, if the first output current is smaller than the second output current, the third switch is closed, and the fourth switch is opened.
Optionally, the first output current and the second output current both pass through t 1 After time integration, the integrated voltage V is obtained A 、V B The following steps are:
in the above, G m Representing the voltage-to-current amplification factor, C u2 Representing the capacitance value of the unit capacitor;
if V A >V B The residual is quantized to L-bit, and then in the quantization stage, any voltage V is obtained before the first comparison of successive approximation quantization DAC Selecting an intermediate level of the reference voltage, namely:
in the above, V ref Representing the reference voltage;
for the first comparison, the voltage V is integrated A Unchanged, integral voltage V B Rise of voltage value of (2)Then again compare the integrated voltage V A 、V B If V is the magnitude relation of A >V B Then any voltage V DAC The process is as follows:
if at this time V A ＜V B Then any voltage V DAC The process is as follows:
and by analogy, L times of comparison are carried out, and an L-bit residual error quantization result is obtained.
An embodiment of the present invention provides an analog-to-digital converter including: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any preceding claim.
The embodiment of the invention also provides electronic equipment, which comprises: a comparator;
the comparator includes: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any preceding claim.
The invention provides a pipelined successive approximation type analog-to-digital conversion circuit, which comprises: a coarse quantization SAR module and a residual quantization SAR module; in the coarse quantization stage, the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module.
The residual quantization SAR module comprises: a residual quantization capacitor array, a residual quantization logic unit, and a comparator; in the residual quantization stage, the residual quantization capacitor array is used for integrating two paths of output currents to obtain two residual quantization integrated voltages and outputting the two residual quantization integrated voltages to the comparator, and the residual quantization capacitor array is used for executing successive approximation quantization according to the on-off condition of a residual quantization capacitor array switch to obtain a residual quantization result.
The comparator is used for comparing the magnitudes of the two residual quantized integral voltages and outputting a first result signal to the residual quantized logic unit; the residual quantization logic unit is used for generating a residual quantization control signal according to the first result signal so as to control the on-off of the residual quantization capacitor array switch; the method comprises the steps that in a current coarse quantization period, a coarse quantization SAR module completes coarse quantization of a fully differential input voltage, and meanwhile, a residual quantization SAR module completes residual quantization of residual voltage of a previous coarse quantization period; the capacitance value of the integrating capacitor in the coarse quantization SAR module is far smaller than that of the capacitor in the residual quantization capacitor array.
The pipelined successive approximation type analog-to-digital conversion circuit provided by the invention reduces the problem that the sampling speed cannot be raised because full bit quantization is required to be carried out in the same quantization period in the traditional high-precision SAR-ADC. The power consumption problem caused by the fact that the pipeline and the Gm share the same mode is reduced, the working mode of the pipeline reduces the problem that single comparison period time margin is small, and error codes and comparison misjudgment are caused by incomplete signal establishment; the residual quantization mode is adopted, so that the problem of overhigh power consumption caused by overlarge capacitance value of the capacitor in the capacitor array in the traditional high-precision SAR-ADC is solved, meanwhile, the reduction of the number of the capacitors is realized, the precision reduction probability caused by process production mismatch is reduced, and the high-precision SAR-ADC capacitor has high practicability.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of an overall structure of a pipelined successive approximation analog-to-digital converter circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure of a coarse quantization SAR module in an embodiment of the present invention;
FIG. 3 is a coarse quantization timing diagram in an embodiment of the present invention;
FIG. 4 is a diagram of voltage V during coarse quantization SAR in an embodiment of the present invention X 、V Y A variation schematic;
FIG. 5 is a schematic diagram of a residual quantization SAR module in an embodiment of the present invention;
FIG. 6 is a graph of voltage V during successive approximation of residual quantization in an embodiment of the invention A 、V B Is a variation of the schematic diagram;
fig. 7 is a general timing diagram of a successive approximation analog-to-digital conversion circuit in residual quantization according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The pipeline successive approximation type analog-to-digital conversion circuit can be used in analog-to-digital converter systems and other systems which are applicable to comparators, and is particularly applicable to middle-high-precision ADC comparators. The pipelined successive approximation type analog-to-digital conversion circuit comprises: a coarse quantization SAR module and a residual quantization SAR module.
In the coarse quantization stage, the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module.
The residual quantization SAR module comprises: a residual quantization capacitor array, a residual quantization logic unit, and a comparator; in the residual quantization stage, the residual quantization capacitor array is used for integrating two paths of output currents to obtain two residual quantization integrated voltages and outputting the two residual quantization integrated voltages to the comparator, and the residual quantization capacitor array is used for executing successive approximation quantization according to the on-off condition of a residual quantization capacitor array switch to obtain a residual quantization result.
The comparator is used for comparing the magnitudes of the two residual quantized integral voltages and outputting a first result signal to the residual quantized logic unit; the residual quantization logic unit is used for generating a residual quantization control signal according to the first result signal so as to control the on-off of the residual quantization capacitor array switch.
The method comprises the steps that in a current coarse quantization period, a coarse quantization SAR module completes coarse quantization of a fully differential input voltage, and meanwhile, a residual quantization SAR module completes residual quantization of residual voltage of a previous coarse quantization period; the capacitance value of the integrating capacitor in the coarse quantization SAR module is far smaller than the capacitance value of the capacitor in the residual quantization capacitor array, so that the capacitance value of the capacitor in the coarse quantization SAR module does not influence the capacitance weight during residual quantization.
For better explanation and description of the pipelined successive approximation type analog-to-digital conversion circuit, referring to fig. 1, a schematic diagram of the overall structure of the pipelined successive approximation type analog-to-digital conversion circuit according to an embodiment of the present invention is shown. The coarse quantization SAR module in fig. 1 comprises: the device comprises a capacitive full-differential SAR-ADC structure, a voltage-to-current amplifying unit, a coarse quantization logic unit, a judgment latch unit and a coarse quantization integration unit. In the coarse quantization SAR module, the specific structures of the capacitive fully-differential SAR-ADC structure, the coarse quantization logic unit and the judgment latch unit are basically the same as those of the prior known SAR-ADC. A voltage-to-current amplifying unit and a coarse quantization integrating unit are additionally added.
In a preferred implementation, referring to the schematic structural diagram of the coarse quantization SAR module shown in fig. 2, the voltage-to-current amplification unit is denoted by Gm in fig. 2, and the coarse quantization integration unit includes: two reset switches RST on the right side of Gm 1 、RST 2 And two integrating capacitances C 1 、C 2 Is a structure of (a).
The capacitive fully differential SAR-ADC structure comprises: m-bit fully differential SAR-ADC, each bit capacitor with its lower plate connected to 3 switches (SH is used in FIG. 2 1 、SH 4 Representation) respectively receives a fully differential input voltage V INN 、V INP Reference voltage V RH And (3) grounding. The unit capacitance in the capacitor array is C u1 The total capacitance is 2 M C u1 And adopting a lower polar plate sampling technology. The upper polar plate of the capacitor array passes through a switch SH 2 、SH 3 Receiving common-mode voltage V CM Simultaneously the upper polar plate of the capacitor array and two input ends of the Gm moduleAnd (5) connection.
In the coarse quantization stage, a capacitive fully differential SAR-ADC structure for inputting a voltage V INN 、V INP Integrating to obtain positive input terminal voltage V X And negative input terminal voltage V Y And the successive approximation quantization is carried out according to the on-off condition of a capacitor array switch in the capacitor type full-differential SAR-ADC structure, so as to obtain a coarse quantization result.
The coarse quantization stage is divided into a sampling stage and a coarse quantization stage. Sampling stage, switch SH 1 、SH 2 、SH 3 、SH 4 Reset switch RST 1 、RST 2 Closing, the lower polar plates of the capacitor array are respectively connected with voltage V INP 、V INN Electrode plate of capacitor array is connected with common mode voltage V CM Integrating capacitor C 1 、C 2 The upper plate ground is reset to 0.
Quantization stage, switch SH 1 、SH 2 、SH 3 、SH 4 Reset switch RST 1 、RST 2 Off, voltage V INP 、V INN Is sampled to the lower polar plate of the capacitor, and the voltage of the upper polar plate of the capacitor array connected with the positive input end of Gm is V CM The voltage of the lower polar plate is V INP Then the charge Q sampled at this time + ＝(V CM -V INP )2 M C u1 。
In SAR logic, 2 will be the first time M-1 C u1 The lower polar plate of the capacitor is grounded, and the lower polar plates of the other capacitors are grounded at a reference voltage V RH Due to conservation of charge, gm is now the positive input terminal voltage V X The relation is:
2 M-1 (V x -0)C u1 +2 M-1 (V x -V RH )C u1 ＝Q + ＝(V CM -V INP )2 M C u1
then it is possible to obtain:
similarly, the voltage of the upper polar plate of the capacitor array connected with the negative input end of the sampling stage Gm is V CM The voltage of the lower polar plate is V INN Then the charge Q sampled at this time _ ＝(V CM -V INN )2 M C u1 . In SAR logic, 2 will be the first time M-1 C u1 The lower polar plate of the capacitor is connected with a reference voltage V RH The lower electrode plate of the rest capacitor is grounded, and the voltage V of the Gm negative input end is kept due to conservation of charge Y The relation is:
2 M-1 (V Y -0)C u1 +2 M-1 (V Y -VTH)C u1 ＝Q - ＝(V CM -V INN )2 M C u1
then it is possible to obtain:
V X and V Y Two kinds of simultaneous connection can be obtained:
V X -V Y ＝V INN -V INP
if the input voltage is fully differential V INP >V INN Then there is V Y >V X . The voltage-to-current amplifying unit is used for converting and amplifying the positive input end voltage and the negative input end voltage into two paths of corresponding output currents and outputting the two paths of corresponding output currents to the coarse quantization integrating unit and the residual quantization SAR module.
That is, gm module vs. voltage V X 、V Y Amplifying the voltage and current, and amplifying the voltage and current in an integrating capacitor C 1 、C 2 And integrating. The coarse quantization integration unit is used for integrating the two paths of output currents to obtain two integrated voltages V A 、V B And output to the judgment latch unit. The judgment latch unit is used for integrating the voltage V for two coarse quantization A 、V B And outputs a second resulting signal to a coarse quantization logic unit (represented by SAR logic 1 in fig. 2).
The coarse quantization logic unit is used for according to the firstTwo result signals, generate coarse quantization control signals, and further control a capacitor array switch SH in a capacitor type full-differential SAR ADC structure 1 、SH 2 、SH 3 、SH 4 Is provided. If V INP >V INN Then there is V Y >V X Then SAR logic 1 outputs a logic value 0, switch RST 1 、RST 2 Closing, for integrating capacitance C 1 、C 2 Reset, then the weight of Gm negative input terminal is 2 M-1 C u1 The lower polar plate of the capacitor is grounded, 2 M-2 C u1 The lower polar plate of the capacitor is connected with V RH The lower electrode plate of the rest capacitor is grounded. The weight of the Gm positive input end is 2 M-1 C u1 The lower polar plate of the capacitor is connected with V RH ，2 M-2 The lower polar plate of the Cu1 capacitor is grounded, and the lower polar plates of the other capacitors are connected with V RH 。
If V INP <V INN Then 2 M-1 C u1 The lower polar plates of the capacitor are all kept unchanged, 2 M-2 C u1 The lower plate of the capacitor is the same as the one described above (V INP >V INN And then repeating the process to finish the coarse quantization of M-bit. The rough quantization timing diagram is shown in FIG. 3, wherein the high level indicates that the switch is closed, and the voltage V in SAR process is rough quantized X 、V Y The change diagram is shown in FIG. 4, and the V after 5 comparisons is shown in FIG. 4 X 、V Y Voltage, time t, V on abscissa DD Representing the supply voltage. It can be seen that V X 、V Y The voltage gradually approaches the common-mode voltage V CM There is still a residual voltage, which is processed by the residual quantization SAR module.
In a preferred implementation, referring to the schematic structure diagram of the residual quantization SAR module shown in fig. 5, the residual quantization logic unit is denoted by SAR logic 2, the comparator is denoted by CMP, and the remainder is the residual quantization capacitor array. In fig. 5, for better understanding of the residual quantization process, an overall structure diagram at the time of residual quantization is exemplarily shown.
The residual quantization capacitor array includes: a first half unit and a second half unit; the first half unit receives a first output current of the two paths of output currents, and the second half unit receives a second output current of the two paths of output currents.
The first half unit includes: first residual quantization capacitor array (and first reset switch RST 3 Parallel capacitor array of 2 n-k C U2 Represented), a second residual quantization capacitor array (with a first reset switch RST 3 Parallel capacitor array of 2 k C U2 Representation), a first switch SH 5 Second switch SH 7 Third switch phi 1 Fourth switch Guan 3 First reset switch RST 3 。
First switch SH 5 A first end receiving a first output current, a second end and a first reset switch RST 3 The second end of the first residual quantized capacitor array, the upper electrode plate of the second residual quantized capacitor array and the positive input end of the comparator CMP are respectively connected.
First reset switch RST 3 Is connected with the lower polar plate of the first residual error quantization capacitor array and is grounded; lower polar plate of second residual quantized capacitor array and second switch SH 7 A second terminal, a third switch phi 1 Second end of (5) fourth opening Guan 3 Are respectively connected with the second ends of the two parts; second switch SH 7 First and fourth openings Guan 3 Is grounded; third switch phi 1 Is connected to the output of a reference voltage selection module (not shown in fig. 5).
The second half unit includes: third residual quantization capacitor array (and second reset switch RST) 4 Parallel capacitor array of 2 n-k C U2 Representation), a fourth residual quantization capacitor array (with a second reset switch RST 4 Parallel capacitor array of 2 k C U2 Indicated), fifth switch SH 6 Sixth switch SH 8 Seventh opening Guan 2 Eighth opening Guan 4 Second reset switch RST 4 。
Fifth switch SH 6 A first terminal receiving the second output current, a second terminal and a second reset switch RST 4 First end, second end of (a)The upper polar plate of the three residual quantized capacitor array, the upper polar plate of the fourth residual quantized capacitor array and the negative input end of the comparator CMP are respectively connected.
Second reset switch RST 4 The second end of the third residual quantization capacitor array is connected with the lower polar plate of the third residual quantization capacitor array and grounded; lower polar plate of fourth residual error quantization capacitor array and sixth switch SH 8 First end of seventh opening Guan 2 First end of (a) eighth opening Guan 4 Are respectively connected with the first ends of the two parts; fifth switch SH 6 Second end of (a) eighth opening Guan 4 Is grounded; seventh opening Guan 2 The second end of the voltage regulator is connected with the output end of the reference voltage selection module; the output of the comparator CMP is connected to the residual quantization logic unit SAR logic 2.
The first residual quantization capacitor array and the third residual quantization capacitor array each include: 2 n-k A unit capacitance; the second residual quantization capacitor array and the fourth residual quantization capacitor array each include: 2 k A number of unit capacitors, n > k; the sum of the number of unit capacitors in the first residual quantization capacitor array and the number of unit capacitors in the second residual quantization capacitor array is: 2 n A unit capacitance; the sum of the number of the unit capacitors in the third residual quantized capacitor array and the number of the unit capacitors in the fourth residual quantized capacitor array is: 2 n A unit capacitance.
For the reference voltage selection module, it is used for the reference voltage selection from 2 L Selecting any one of the reference voltages and outputting the selected voltage to a first end of the third switch and a second end of the seventh switch; either voltage V DAC The expression of (2) is:
in the above, V ref Representing the reference voltage.
The following relationship exists for each switch:
first switch SH 5 Second switch SH 7 Fifth switch SH 6 Sixth switch SH 8 Simultaneously closing or simultaneously opening; first, theA reset switch RST 3 And a second reset switch RST 4 Simultaneously closing or simultaneously opening; third switch phi 1 And eighth opening Guan 4 Simultaneously closing or simultaneously opening; fourth switch phi 3 And seventh opening Guan 2 Simultaneously closed or simultaneously opened.
Wherein the residual quantization stage also comprises: an integration stage and a quantization stage; in the coarse quantization phase, the first switch is opened, and it is naturally understood that the second switch, the fifth switch, and the sixth switch are also opened.
An integration phase in the residual quantization phase, a first switch SH 5 Closed, as will be naturally understood, the second switch SH 7 Fifth switch SH 6 Sixth switch SH 8 Is also closed.
At the first switch SH 5 While being closed, the first reset switch RST 3 Second reset switch RST 4 Also closed, after resetting all unit capacitances in the residual quantization capacitance array, a first reset switch RST 3 Second reset switch RST 4 Immediately disconnect.
In the quantization phase of the residual quantization phase, if the first output current is greater than the second output current, the fourth switch Guan 3 Closing, third switch phi 1 Disconnection, it will be naturally understood that the seventh opening Guan 2 Closing, eighth switch phi 4 And (5) disconnecting.
In the quantization phase of the residual quantization phase, if the first output current is smaller than the second output current, a third switch phi 1 Closing, fourth switch phi 3 Disconnection, it is naturally understood that eighth opening Guan 4 Closed, seventh opening Guan 2 And (5) disconnecting.
First switch SH 5 And a fifth switch SH 6 When closed, the capacitor is 2 n C u2 Is indirectly connected to the output end of the Gm module, capacitor 2 n C u2 Far greater than the integrating capacitor C in the coarse quantization SAR module 1 、C 2 So that C 1 、C 2 The capacitance of (2) does not affect the capacitance weight at residual quantization.
For capacitor array in residual quantization SAR module, 2 n C u2 2 in the unit capacitance n-k C u2 The lower electrode plate of each unit capacitor is directly grounded, 2 k The lower polar plate of each unit capacitor is connected with V DAC Or to ground, each switch SH is controlled by SAR logic 2 5 、SH 6 、SH 7 、SH 8 、RST 3 、RST 4 、φ 1 、φ 2 、φ 3 、φ 4 Is opened or closed.
All the switch states of the capacitor array in the coarse quantization SAR module are determined after the coarse quantization stage, and at the moment, residual voltage DeltaV exists at the input end of the Gm module 1 ＝V X -V Y After voltage and current amplification, at 2 n C u2 Integration is performed on the unit capacitance, and the capacitance 2 n C u2 The upper polar plate is connected with the Gm output end, and the lower polar plate is grounded.
The first output current and the second output current both pass through t 1 After time integration, the integrated voltage V is obtained A 、V B The following steps are:
in the above, G m Representing the voltage-to-current amplification factor, C u2 Representing the capacitance value of the unit capacitance.
If at this time V A >V B If the residual is quantized to L-bit, any voltage V is obtained before the first comparison of successive approximation quantization in the quantization stage of the residual quantization stage DAC Selecting an intermediate level of the reference voltage, namely:
in the above, V ref Representing the reference voltage.
For the first comparison, the voltage V is integrated A UnchangedIntegral voltage V B Rise of voltage value of (2)Then again compare the integrated voltage V A 、V B If the magnitude relation of V A >V B Either voltage V DAC The process is as follows:
if at this time V A ＜V B Either voltage V DAC The process is as follows:
taking L bit as 8bit as an example, if V A >V B Voltage V DAC Selecting one half of the reference voltage, and integrating the voltage V when the first comparison is performed A Unchanged, integral voltage V B The voltage value of (2) rises by three-fourths of the reference voltage, and if V is the second comparison A >V B Then integrate the voltage V A Unchanged, integral voltage V B The voltage value of (2) rises by seven reference voltages of eight. And by analogy, L times of comparison are carried out, and an L-bit residual error quantization result is obtained. And finally finishing the analog-digital conversion of M+L bits.
Voltage V in residual quantization successive approximation process A 、V B As shown in FIG. 6, the voltage V is exemplified in FIG. 6 A 、V B Comparison 6 times is shown as an example. The overall timing diagram of the successive approximation analog-to-digital conversion circuit in the residual quantization shown in fig. 7 can be combined to better understand the capacitor array switch SH in the coarse quantization SAR module 1 Reset switch RST 1 First switch SH in residual quantized SAR module 5 First reset switch RST 3 On-off conditions of (c), and successive approximation quantization.
In an embodiment of the present invention, based on the pipelined successive approximation type analog-to-digital converter circuit, an analog-to-digital converter is further provided, where the analog-to-digital converter includes: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any preceding claim.
In an embodiment of the present invention, based on the above-mentioned pipelined successive approximation type analog-to-digital conversion circuit, an electronic device is further provided, where the electronic device includes: a comparator; the comparator includes: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any preceding claim.
In summary, the pipelined successive approximation analog-to-digital conversion circuit of the present invention includes: a coarse quantization SAR module and a residual quantization SAR module; in the coarse quantization stage, the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module.
The residual quantization SAR module comprises: a residual quantization capacitor array, a residual quantization logic unit, and a comparator; in the residual quantization stage, the residual quantization capacitor array is used for integrating two paths of output currents to obtain two residual quantization integrated voltages and outputting the two residual quantization integrated voltages to the comparator, and the residual quantization capacitor array is used for executing successive approximation quantization according to the on-off condition of a residual quantization capacitor array switch to obtain a residual quantization result.
The comparator is used for comparing the magnitudes of the two residual quantized integral voltages and outputting a first result signal to the residual quantized logic unit; the residual quantization logic unit is used for generating a residual quantization control signal according to the first result signal so as to control the on-off of the residual quantization capacitor array switch; the method comprises the steps that in a current coarse quantization period, a coarse quantization SAR module completes coarse quantization of a fully differential input voltage, and meanwhile, a residual quantization SAR module completes residual quantization of residual voltage of a previous coarse quantization period; the capacitance value of the integrating capacitor in the coarse quantization SAR module is far smaller than that of the capacitor in the residual quantization capacitor array.
The pipelined successive approximation type analog-to-digital conversion circuit provided by the invention reduces the problem that the sampling speed cannot be raised because full bit quantization is required to be carried out in the same quantization period in the traditional high-precision SAR-ADC. The power consumption problem caused by the fact that the pipeline and the Gm share the same mode is reduced, the working mode of the pipeline reduces the problem that single comparison period time margin is small, and error codes and comparison misjudgment are caused by incomplete signal establishment; the residual quantization mode is adopted, so that the problem of overhigh power consumption caused by overlarge capacitance value of the capacitor in the capacitor array in the traditional high-precision SAR-ADC is solved, meanwhile, the reduction of the number of the capacitors is realized, the precision reduction probability caused by process production mismatch is reduced, and the high-precision SAR-ADC capacitor has high practicability.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. A pipelined successive approximation analog-to-digital conversion circuit, the successive approximation analog-to-digital conversion circuit comprising: a coarse quantization SAR module and a residual quantization SAR module;
in a coarse quantization stage, the coarse quantization SAR module is used for performing approximation quantization on the fully-differential input voltage obtained by sampling to obtain a coarse quantization result, generating two paths of output currents corresponding to the fully-differential input voltage, and outputting the two paths of output currents to the residual quantization SAR module;
the residual quantization SAR module comprises: a residual quantization capacitor array, a residual quantization logic unit, and a comparator;
in the residual quantization stage, the residual quantization capacitor array is used for integrating two paths of output currents to obtain two residual quantization integrated voltages and outputting the two residual quantization integrated voltages to the comparator, and performing successive approximation quantization according to the on-off condition of a residual quantization capacitor array switch to obtain a residual quantization result;
the comparator is used for comparing the magnitudes of two residual quantized integral voltages and outputting a first result signal to the residual quantized logic unit;
the residual quantization logic unit is used for generating a residual quantization control signal according to the first result signal so as to control the on-off of the residual quantization capacitor array switch;
the coarse quantization SAR module completes coarse quantization of the fully-differential input voltage in the current coarse quantization period, and simultaneously completes residual quantization of residual voltage in the previous coarse quantization period;
the capacitance value of the integrating capacitor in the coarse quantization SAR module is far smaller than that of the capacitor in the residual quantization capacitor array.
2. The successive approximation analog-to-digital conversion circuit of claim 1, wherein the coarse quantization SAR module comprises: the device comprises a capacitive full-differential SAR ADC structure, a voltage-to-current amplifying unit, a coarse quantization logic unit, a judgment latch unit and a coarse quantization integration unit;
in the coarse quantization stage, the capacitive full-differential SAR ADC structure is configured to integrate the full-differential input voltage to obtain a positive input end voltage and a negative input end voltage, and output the positive input end voltage and the negative input end voltage to the positive input end and the negative input end of the voltage-to-current amplifying unit, respectively, and perform successive approximation quantization according to the on-off condition of a capacitive array switch in the capacitive full-differential SAR ADC structure, so as to obtain the coarse quantization result;
the voltage-to-current amplifying unit is used for converting and amplifying the positive input end voltage and the negative input end voltage into two paths of corresponding output currents and outputting the two paths of corresponding output currents to the coarse quantization integrating unit and the residual quantization SAR module;
the coarse quantization integration unit is used for integrating the two paths of output currents to obtain two integrated voltages and outputting the two integrated voltages to the judgment latch unit;
the judgment latch unit is used for comparing the magnitudes of the two coarse quantization integral voltages and outputting a second result signal to the coarse quantization logic unit;
and the coarse quantization logic unit is used for generating a coarse quantization control signal according to the second result signal so as to control the on-off of a capacitor array switch in the capacitor type full-differential SAR ADC structure.
3. The successive approximation analog-to-digital conversion circuit of claim 1, wherein the residual quantization capacitor array comprises: a first half unit and a second half unit;
the first half unit receives a first output current of the two paths of output currents, and the second half unit receives a second output current of the two paths of output currents;
the first half unit includes: the first residual quantization capacitor array, the second residual quantization capacitor array, the first switch, the second switch, the third switch, the fourth switch and the first reset switch;
the first end of the first switch receives the first output current, and the second end of the first switch is respectively connected with the second end of the first reset switch, the upper polar plate of the first residual quantized capacitor array, the upper polar plate of the second residual quantized capacitor array and the positive input end of the comparator;
the first end of the first reset switch is connected with the lower polar plate of the first residual error quantization capacitor array and grounded;
the lower polar plate of the second residual error quantification capacitor array is respectively connected with the second end of the second switch, the second end of the third switch and the second end of the fourth switch;
the first end of the second switch and the first end of the fourth switch are grounded;
the first end of the third switch is connected with the output end of the reference voltage selection module.
4. A successive approximation analog-to-digital conversion circuit as claimed in claim 3, wherein the second half unit comprises: a third residual quantization capacitor array, a fourth residual quantization capacitor array, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a second reset switch;
the first end of the fifth switch receives the second output current, and the second end of the fifth switch is respectively connected with the first end of the second reset switch, the upper polar plate of the third residual quantized capacitor array, the upper polar plate of the fourth residual quantized capacitor array and the negative input end of the comparator;
the second end of the second reset switch is connected with the lower polar plate of the third residual error quantization capacitor array and grounded;
the lower polar plate of the fourth residual quantization capacitor array is respectively connected with the first end of the sixth switch, the first end of the seventh switch and the first end of the eighth switch;
the second end of the fifth switch and the first end of the eighth switch are grounded;
the second end of the seventh switch is connected with the output end of the reference voltage selection module;
and the output end of the comparator is connected with the residual error quantization logic unit.
5. The successive approximation analog-to-digital conversion circuit of claim 4, wherein the first residual quantization capacitor array and the third residual quantization capacitor array each comprise: 2 n-k A unit capacitance;
the second residual quantization capacitor array and the fourth residual quantization capacitor array each include: 2 k A number of unit capacitors, n > k;
the sum of the number of the unit capacitors in the first residual quantized capacitor array and the number of the unit capacitors in the second residual quantized capacitor array is as follows: 2 n A unit capacitance;
the sum of the number of the unit capacitors in the third residual quantization capacitor array and the number of the unit capacitors in the fourth residual quantization capacitor array is as follows: 2 n A unit capacitance.
6. The successive approximation analog-to-digital conversion circuit of claim 4, wherein the reference voltage selection module is configured to select from 2 L Selecting any one of the reference voltages and outputting the selected reference voltage to a first end of the third switch and a second end of the seventh switch;
said arbitrary voltage V DAC The expression of (2) is:
in the above, V ref Representing the reference voltage.
7. The successive approximation analog-to-digital conversion circuit according to claim 4, wherein the first switch, the second switch, the fifth switch, and the sixth switch are simultaneously closed or simultaneously opened;
the first reset switch and the second reset switch are simultaneously closed or simultaneously opened;
the third switch and the eighth switch are simultaneously closed or simultaneously opened;
the fourth switch and the seventh switch are simultaneously closed or simultaneously opened;
wherein the residual quantization stage comprises: an integration stage and a quantization stage;
during the coarse quantization phase, the first switch is open;
during the integration phase, the first switch is closed;
the first reset switch is closed when the first switch is closed, and is opened after all unit capacitors in the residual quantized capacitor array are reset;
in the quantization stage, if the first output current is greater than the second output current, the fourth switch is closed, and the third switch is opened;
in the quantization stage, if the first output current is smaller than the second output current, the third switch is closed, and the fourth switch is opened.
8. The successive approximation analog-to-digital conversion circuit of claim 6, wherein the first output current and the second output current each pass through t 1 After time integration, the integrated voltage V is obtained A 、V B The following steps are:
in the above, G m Representing the voltage-to-current amplification factor, C u2 Representing the capacitance value of the unit capacitor;
if V A >V B The residual is quantized to L-bit, and then in the quantization stage, any voltage V is obtained before the first comparison of successive approximation quantization DAC Selecting an intermediate level of the reference voltage, namely:
in the above, V ref Representing the reference voltage;
for the first comparison, the voltage V is integrated A Unchanged, integral voltage V B Rise of voltage value of (2)Then again compare the integrated voltage V A 、V B If V is the magnitude relation of A >V B Then any voltage V DAC The process is as follows:
if at this time V A ＜V B Then any voltage V DAC The process is as follows:
and by analogy, L times of comparison are carried out, and an L-bit residual error quantization result is obtained.
9. An analog-to-digital converter, the analog-to-digital converter comprising: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any one of claims 1 to 8.
10. An electronic device, the electronic device comprising: a comparator;
the comparator includes: a pipelined successive approximation analog-to-digital conversion circuit as claimed in any one of claims 1 to 8.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107528594A (en) * 2017-08-25 2017-12-29 中国电子科技集团公司第二十四研究所 Charge type streamline gradual approaching A/D converter and its control method
CN109194333A (en) * 2018-08-09 2019-01-11 电子科技大学 A kind of composite construction gradually-appoximant analog-digital converter and its quantization method
WO2020098467A1 (en) * 2018-11-16 2020-05-22 深圳锐越微技术有限公司 Residue transfer loop, successive approximation analog-to-digital converter, and gain calibration method
CN111446964A (en) * 2020-04-10 2020-07-24 上海交通大学 Novel fourteen-bit assembly line-successive approximation type analog-digital converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107528594A (en) * 2017-08-25 2017-12-29 中国电子科技集团公司第二十四研究所 Charge type streamline gradual approaching A/D converter and its control method
CN109194333A (en) * 2018-08-09 2019-01-11 电子科技大学 A kind of composite construction gradually-appoximant analog-digital converter and its quantization method
WO2020098467A1 (en) * 2018-11-16 2020-05-22 深圳锐越微技术有限公司 Residue transfer loop, successive approximation analog-to-digital converter, and gain calibration method
CN111446964A (en) * 2020-04-10 2020-07-24 上海交通大学 Novel fourteen-bit assembly line-successive approximation type analog-digital converter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种Vcm-Based10位16M采样率低功耗逐次逼近型模数转换器;刘滢浩;刘宏;徐乐;田彤;;微电子学与计算机;20171105(11);全文 *

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