CN210986085U

CN210986085U - Low-power-consumption successive approximation type analog-to-digital converter

Info

Publication number: CN210986085U
Application number: CN201922348663.3U
Authority: CN
Inventors: 邬亮; 张烨; 李钰静; 刘宗文; 其他发明人请求不公开姓名
Original assignee: Chutian Dragon Co ltd
Current assignee: Chutian Dragon Co ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2020-07-10
Anticipated expiration: 2029-12-24

Abstract

A low-power-consumption successive approximation type analog-to-digital converter comprises a first capacitor array, a second capacitor array, a comparator and a successive approximation logic control circuit, wherein the reference voltage of the second capacitor array is half of the maximum input voltage, and the successive approximation logic control circuit adopts a monotonous switch switching strategy, so that the power consumption of analog-to-digital conversion is reduced. The successive approximation type analog-to-digital converter disclosed by the application can solve the problem that an SAR ADC with a traditional structure in the prior art is high in energy consumption.

Description

Low-power-consumption successive approximation type analog-to-digital converter

Technical Field

The present application relates generally to the field of integrated circuits, and more particularly to a successive approximation analog-to-digital converter.

Background

A Successive Approximation Analog-to-Digital Converter (SAR ADC) is an ADC based on a binary search Approximation algorithm, and the basic working principle is to attenuate a reference voltage by using a binary-weighted capacitor array to achieve the purpose of binary division of total charge on the capacitor array, thereby implementing the binary Approximation search algorithm.

A conventional charge redistribution type SAR ADC mainly includes a capacitor array, a comparator, and a successive approximation logic control circuit. The capacitor array is one of important sources of SAR ADC energy consumption, and the capacitor array and the switch scheme adopted by the SARADC with the traditional structure have the problem of high power consumption.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks and deficiencies in the prior art, it is desirable to provide a successive approximation type analog-to-digital converter with low power consumption, which can solve the problem of high power consumption in the prior art.

In a first aspect, the present application provides an n-bit successive approximation type analog-to-digital converter, including a first capacitor array, a second capacitor array, a comparator, and a successive approximation logic control circuit, where the first capacitor array is connected to a first input end of the comparator and the successive approximation logic circuit, the second capacitor array is connected to a second input end of the comparator and the successive approximation logic circuit, an output end of the comparator is connected to the successive approximation logic control circuit, and the successive approximation logic control circuit outputs a digital signal;

the first capacitor array comprises capacitors C connected in parallel_a0～C_a(n-1)The second capacitor array comprises capacitors C connected in parallel_b0～C_b(n-1)In which C is_a0＝C_b0＝C，C_ai＝C_bi＝2^i-1C, i is 1 to (n-1), and C is a basic unit of capacitance;

all upper polar plates of the first capacitor array are connected with a first input end of the comparator, and the first input end of the comparator is connected with a switch S_a0And an input voltage signal V_INConnected to a capacitor C_a0The lower pole plate is connected with a reference voltage signal V_REFCapacitor C_a1～C_a(n-1)Respectively through a switch S_a1～S_a(n-1)Is connected with a reference voltage signal V_REFAll upper electrode plates of the second capacitor array are connected with a second input end of the comparator, and the second input end of the comparatorBy means of a switch S_b0And a reference voltage signal V_REFConnected to a capacitor C_b0The lower pole plate is connected with a reference voltage signal V_REFCapacitor C_b1～C_b(n-1)Respectively through a switch S_b1～S_b(n-1)Is connected with a reference voltage signal V_REF；

The successive approximation logic control circuit outputs a control signal to control the switch S according to the comparison result of the comparator_a1～S_a(n-1)And S_b1～S_b(n-1)The handover of (2).

According to the n-bit successive approximation type analog-to-digital converter, the capacitor array adopts half of the maximum input voltage as the reference voltage, so that the voltage swing on the capacitor is reduced, the energy consumed by charging and discharging the capacitor is reduced, a monotonous switch switching strategy is adopted, the charge loss caused by the search failure of the traditional SAR ADC is avoided, the power consumption of analog-to-digital conversion is reduced, and the problem that the energy consumption of the SAR ADC with the traditional structure in the prior art is high is solved.

Drawings

Fig. 1 is a block diagram of a successive approximation type analog-to-digital converter SAR ADC according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a capacitor array according to an embodiment of the present application;

FIG. 3 is a circuit configuration diagram of a comparator in an embodiment of the present application;

FIG. 4 is a circuit diagram of a pre-op-amp in an embodiment of the present application;

FIG. 5 is a circuit diagram of a dynamic comparator according to an embodiment of the present application;

FIG. 6 is a flow chart of an analog-to-digital conversion method in an embodiment of the present application;

fig. 7 is a flowchart of determining valid values of digital signals by successive comparisons according to an embodiment of the present application.

Detailed Description

In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following description is given in conjunction with the embodiments and the accompanying drawings.

Description of the symbols

ADC: Analog-to-Digital Converter

SAR: successive Approximation Register (SAR)

CMOS: complementary Metal Oxide Semiconductor (CMOS)

MSB: most Significant Bit of Most Significant Bit

L SB L east Significant Bit, least Significant Bit

EOC: end of Conversion

V_P: first capacitor array upper plate voltage

V_N: second capacitor array upper electrode plate voltage

V_IN: input voltage

V_IN-MAX: maximum input voltage, full range input voltage

V_REF: reference voltage

Preamp: pre-amplifier, Pre-op amp

C L KC clock signal

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In an embodiment of the present application, an n-bit successive approximation type analog-to-digital converter SAR ADC is provided, as shown in fig. 1, which is a structural block diagram of a 12-bit successive approximation type analog-to-digital converter SAR ADC in an embodiment of the present application. It should be understood that, in this embodiment, the application is described by taking a 12-bit SAR ADC as an example, the successive approximation type SAR ADC provided by the application can be applied to different resolutions, such as 8 bits, 10 bits, n bits, etc., and the disclosure herein does not limit the application scope of the application.

As shown in fig. 1, a 12-bit successive approximation type analog-to-digital converter SAR ADC 100 includes but is not limited to: a capacitor array 110, a comparator 120, and a successive approximation logic control circuit 130. Wherein the capacitive array 110 includes a first capacitive array 111 and a second capacitive array 112. The first capacitor array 111 is connected to the first input terminal of the comparator 120 and the successive approximation logic control circuit 130, and the second capacitor array 112 is connected to the second input terminal of the comparator 120 and the successive approximation logic control circuit 130. The output of the comparator 120 is connected to a successive approximation logic control circuit 130.

The capacitor array 110 is used for the input voltage V_INSampling and holding are performed. The comparator 120 is used for comparing the output voltage of the first capacitor array 111 with the output voltage of the second capacitor array 112. The successive approximation logic control circuit 130 outputs a control signal for controlling the switches in the capacitor array 110 according to the comparison output result of the comparator 120. The successive approximation logic control circuit 130 outputs a digital signal D after the ADC conversion is completed₁₁～D₀And an End of conversion (EOC) signal to the back-End circuit ADC that the conversion has been completed.

Fig. 2 is a schematic structural diagram of the capacitor array 110. The first capacitor array 111 comprises 12 capacitors C connected in parallel_a0～C_a11The second capacitor array 112 includes 12 capacitors C connected in parallel_b0～C_b11，C_a0＝C_boC is the basic unit of capacitance, C_ai＝C_bi＝2^i-1C, i is 1-11. It should be understood that fig. 2 is only a schematic structural diagram of the capacitor array in the 12-bit successive approximation type analog-to-digital converter, and does not limit the application scope of the present application, and it is easily obtained by a person skilled in the art that the n-bit successive approximation type analog-to-digital converter includes two capacitor arrays, and the first capacitor array includes n capacitors C connected in parallel_a0～C_a(n-1)The second capacitor array comprises n capacitors C connected in parallel_b0～C_b(n-1)In which C is_a0＝C_b0＝C，C_ai＝C_bi＝2^i-1C, i is 1 to (n-1), and C is a basic unit of capacitance, and the total capacitance value C of the first capacitor array 111 and the second capacitor array 112 is known_a＝C_b＝2¹¹C。

All upper plates of the first capacitor array 111 are connected to the first input terminal of the comparator 120, i.e. the upper plate voltage V of the first capacitor array 111_PAs a signal at a first input of the comparator 120, the first input of the comparator 120 is passed through a switch S_a0And an input voltage signal V_INConnected to a capacitor C_a0The lower pole plate is connected with a reference voltage signal V_REF，C_a1～C_a(n-1)The capacitors pass through switches S respectively_a1～S_a11Is connected with a reference voltage signal V_REFOr to ground. All the upper plates of the second capacitor array 112 are connected to the second input terminal of the comparator 120, i.e. the upper plate voltage V of the second capacitor array 112_NAs a signal at a second input of the comparator 120. A second input of the comparator 120 is connected via a switch S_b0And a reference voltage signal V_REFIs connected to C_b0The lower plate of the capacitor is connected with a reference voltage signal V_REF，C_b1～C_b(n-1)The capacitors pass through switches S respectively_b1～S_b11Is connected with a reference voltage signal V_REFOr to ground. The successive approximation logic control circuit 130 outputs a control signal for controlling the switch S according to the comparison result of the comparator 120_a1～S_a11And S_b1～S_b11。

In an embodiment of the present application, since the first capacitor array 111 and the second capacitor array 112 adopt an upper plate sampling technique for sampling, the influence of the parasitic capacitance of the lower plate of the capacitor on the accuracy of the SAR ADC is reduced. In addition, a reference voltage signal V_REFIs the maximum input voltage V_IN-MAXHalf of that, the successive approximation analog-to-digital converter SAR ADC 100 only requires the maximum input voltage V_IN-MAXIs used as a reference voltage signal V_REFI.e. the input voltage V can be realized_INThe full-scale input of the capacitor reduces the voltage swing on the capacitor, thereby reducing the energy consumed by charging and discharging the capacitor.

In an embodiment of the present application, the switches in the capacitor array 110 are implemented by CMOS switches, which have a full swing voltage input range, a small layout area, and a certain suppression effect on the channel charge injection effect and the clock feedthrough effect. Switch S in first capacitor array 111_a1～S_a11The size of the capacitor is reduced from high position to low position in proportion, and the time constant of an RC network formed by a single capacitor and a corresponding switch is close to the time constant of the RC network. Similarly, switch S in second capacitor array 112_b1～S_b11The size of the capacitor is reduced from high position to low position in proportion, and the time constant of an RC network formed by a single capacitor and a corresponding switch is close to the time constant of the RC network.

Fig. 3 is a circuit configuration diagram of the comparator 120 according to an embodiment of the present application. The comparator 120 includes three identical preamplifiers (preamps) Preamp121, Preamp122, Preamp123 and a dynamic comparator 124 connected in sequence. The upper plate voltage VP of the first capacitor array 111 and the upper plate voltage VN of the second capacitor array 112 are input signals, and VOUT is an output signal. The front-end operational amplifier has low gain and high bandwidth, wherein the high bandwidth improves the comparison speed of the comparator, and simultaneously improves the gain by an operational amplifier cascade mode, and improves the resolution of the comparator to input voltage. Meanwhile, the comparator adopts the input offset elimination and output offset elimination technology, so that the offset voltage of the comparator is reduced.

Fig. 4 is a circuit diagram of a Preamp in an embodiment of the present application. PM2, PM3 are input tubes, NM 1-NM 4 constitute the load of the amplifier, NM2, NM3 are connected in a cross coupling mode, the gain of the amplifier can be improved, and the size of NM1 is larger than that of NM2, so that the amplifier can be prevented from entering a latch state. NM5, NM6 are connected to the circuit in a diode connection mode, and clamp the output voltage, so that the reset time of the comparator can be reduced, and the comparison speed can be improved.

Fig. 5 is a circuit configuration diagram of a dynamic comparator according to an embodiment of the present application. The function of the dynamic comparator 124 is to amplify the output of the preamplifier to a high or low level recognizable by the digital circuit. The circuit of the dynamic comparator 124 includes a tail current source PM1, differential input PMOS transistors PM2, PM3, cross-coupled inverters PM8, NM3 and PM9, NM4, NMOS switches NM5, NM6, and inverters PM4, NM1 and PM5, NM 2. The functions of the dynamic comparator 124 include reset and comparison.

Resetting, wherein the clock signal C L KC is 1, the circuit is reset, the switches NM5 and NM6 are conducted, and the input and output levels of the load of the inverter are pulled to 0;

comparing, when the clock signal C L KC is 0, the switches NM5 and NM6 are turned off, the circuit compares the input voltage, when V is_PGreater than V_NThe current flowing through PM2 is less than the current flowing through PM4, the voltage at V3 rises faster than at V4, V3 is pulled down to ground, V4 is pulled up to VDD through the positive feedback of the cross-coupled inverters, VOUT is pulled up to VDD through the inverter output, i.e., digital signal 1, VNOUT is pulled down to ground, i.e., digital level 0; when V is_PLess than V_NMeanwhile, similarly, VOUT is pulled down to ground, i.e., digital level 0, VNOUT is pulled up to VDD, i.e., digital signal 1, and there is no static power consumption in the whole operation process.

Fig. 6 is a flowchart illustrating an analog-to-digital conversion method according to an embodiment of the present application, where the analog-to-digital conversion method is applied to the successive approximation type analog-to-digital converter shown in fig. 1.

S601, resetting the successive approximation logic control circuit and storing offset voltage of the comparator. The successive approximation logic control circuit 130 performs a reset operation under the action of the reset signal to reset D₁₁～D₀Set to 0 and switch S_a1～S_a11And S_b1～S_b11All are set to 1, so that the lower plates of all capacitors are connected with a reference voltage V_REF. At the same time, the offset voltage of the comparator is stored.

And S602, sampling and holding. First, switch S_a0、S_b0Closed, the upper plate of the capacitor in the first capacitor array 111 and the input voltage signal V_INThe upper plate of the capacitor in the second capacitor array 112 is connected to the reference voltage signal V_REFIn turn, the voltage of the upper plate of the first capacitor array 111 is charged to V_INThe voltage of the upper plate of the second capacitor array 112 is charged to V_REF. Then, S_a0、S_b0When the ADC is in hold stage, the voltage V of the upper plate of the first capacitor array 111 is cut off_PTotal charge amount Q_PAnd the voltage V of the upper plate of the second capacitor array 112_NTotal charge amount Q_NRespectively shown as the following formula:

V_P＝V_IN

Q_P＝(V_IN-V_REF)×C_P＝(V_IN-V_REF)×2¹¹C

V_N＝V_REF

Q_N＝0

s603, each significant digit value of the digital signal is determined by successive comparison.

In an embodiment of the present application, a specific procedure for successively comparing and determining each significant digit value of a digital signal is performed, and first, as shown in fig. 7, the comparator 120 directly performs the first comparison V (where k is 1 and k represents the number of comparisons)_PAnd V_NThe Most Significant Bit (MSB) is obtained.

If V_P＞V_NI.e. V_IN＞V_REFThen the MSB value is 1; otherwise the MSB value is 0.

If the MSB is 1, the successive approximation logic control circuit 130 generates a control signal that switches the switch S_a11Set to 0, the rest switches are kept unchanged, and then the capacitor C_a11The lower plate of the first capacitor array 111 is connected to ground, and the total charge of the upper plate of the first capacitor array is:

Q_P＝(V_p-V_REF)×(C_P-C_a11)+V_P×C_a11

the simultaneous formula can be given as:

and then V_N＝V_REFThe comparator 120 compares V again accordingly_PAnd V_NDetermines the value of the next most significant bit.

Otherwise, if the MSB is 0, the successive approximation logic control circuit 130 generates controlControl signal to switch S_b11Set to 0, the rest switches are kept unchanged, and then the capacitor C_b11The lower plate of the second capacitor array 112 is connected to ground, and the total charge of the upper plate of the second capacitor array 112 is:

Q_N＝(V_N-V_REF)×(C_N-C_b11)+V_N×C_b11

the simultaneous formula can be given as:

and then V_P＝V_INThe comparator 120 compares V again accordingly_PAnd V_NDetermines the value of the next most significant bit.

And so on at k (k)<12) After the second comparison, if D_(12-k)Is 1, then C is_a(12-k)After the lower pole plate is grounded, (k +1) th comparison is carried out, otherwise, C is compared_b(12-k)The (k +1) th comparison is made after the lower plate of (a) is grounded, (L east signifiant Bit, L SB) the least Significant Bit is generated when k equals 12₁₁～D₀The values are determined one by one.

When the last comparison is completed, the total amount of voltage charge Q of the upper plate of the first capacitor array 111_PAnd the total amount of voltage charge Q of the upper plate of the second capacitor array 112_NRespectively shown as the following formula:

it can be found that:

when the successive approximation process is finished, V_PAnd V_NThe values of (a) are equal, then:

c is to be_P、C_N、C_aiAnd C_biThe value of (i ═ 0 to 11) can be substituted into the above formula:

it should be understood that the above description is given by taking a 12-bit successive approximation type analog-to-digital converter as an example, and those skilled in the art will understand without inventive work that in the working flow of an n-bit successive approximation type analog-to-digital converter, k (k) is the integer<n) after comparison, if D_(n-k)Is 1, then C is_a(n-k)After the lower pole plate is grounded, (k +1) th comparison is carried out, otherwise, C is compared_b(n-k)The (k +1) th comparison is made after the lower plate of (a) is grounded, (L east signifiant Bit, L SB) the least Significant Bit is generated when k is equal to n_n-1～D₀The values are determined one by one.

When the last comparison of the n-bit successive approximation type analog-to-digital converter is completed, the total voltage charge quantity Q of the upper plate of the first capacitor array 111_PAnd the total amount of voltage charge Q of the upper plate of the second capacitor array 112_NRespectively shown as the following formula:

it can be found that:

c is to be_P、C_N、C_aiAnd C_biThe value of (i ═ 0 to (n-1)) can be substituted into the above formula:

s604, outputting the digital signal and the conversion end signal.

Returning to fig. 6, after the determination of the respective significant digit values of the digital signal is completed in step 603, in step 604, the digital signal is output and an end of conversion EOC signal is output to notify the back-end circuit ADC that the conversion has been completed.

The SAR ADC with the traditional differential structure adopts the lower pole plate of a capacitor array to sample input voltage, the sampling is completed, all capacitor lower pole plate switches are grounded, and the upper pole plate switches are disconnected. After entering the conversion stage, the MSB is judged firstly, the lower plate switch of the highest-order capacitor is connected to Vref, and the comparator compares the input voltage. If the former is larger than the latter, the MSB is equal to 1, the plate switch of the highest capacitor lower level is kept unchanged, the plate switch of the next highest capacitor lower level is connected with Vref, and the next highest level is judged; if the former is smaller than the latter, the MSB is equal to 0, the plate switch at the lower level of the highest position is grounded again, then the plate switch at the lower level of the next highest position capacitor is connected with Vref, and the next highest position is judged. And analogizing in turn until the conversion is finished, wherein the operation times of the switch in the conversion process are [ i +2 (12-i)]Where i is D in the output digital signal₀～D₁₁Number of 1 in (1).

The application provides the analog-to-digital conversion process suitable for the 12-bit successive approximation type analog-to-digital converterA total of 12 comparison operations and 11 switching operations were performed. Compared with the traditional differential SARADC, the capacitor array 110 of the SAR ADC provided by the application adopts upper plate sampling, the value of the MSB is obtained without any switching operation, and the dynamic power consumption of the step of obtaining the MSB by adopting lower plate sampling in the traditional structure is eliminated. Moreover, in the successive approximation process, the successive approximation logic control circuit 130 controls the switches in the first capacitor array 111 or the second capacitor array 112 to be grounded and only one charge flows by using a monotonic switching strategy according to the comparison result of the previous bit, so that the condition that the switches of the lower-level plates of the capacitors in the conventional structure control logic are connected with the voltage V is avoided_REFThen according to the comparison result, the earth is needed to be grounded again. In one embodiment of the present application, reference voltage signal V_REFTaking the maximum input voltage V_IN-MAXIs one half of (i.e. V)_REF＝V_IN-MAXThe reference voltage of the conventional differential SAR ADC is equal to the maximum input voltage. Therefore, the SAR ADC provided by the application only needs the maximum input voltage V_IN-MAXIs used as a reference voltage signal V_REFTherefore, the full-scale input of the input voltage can be realized, and the voltage swing on the capacitor is reduced, so that the energy consumed by charging and discharging the capacitor is reduced.

In summary, the successive approximation type analog-to-digital converter provided by the application adopts half of the maximum input voltage as the reference voltage, and is combined with a monotonic switching strategy, so that the power consumption of each analog-to-digital conversion is low, and compared with the traditional structure, the dynamic energy consumption is greatly reduced.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A low-power-consumption successive approximation type analog-to-digital converter comprises a first capacitor array, a second capacitor array, a comparator and a successive approximation logic control circuit, wherein the first capacitor array is connected with a first input end of the comparator and the successive approximation logic circuit, the second capacitor array is connected with a second input end of the comparator and the successive approximation logic circuit, an output end of the comparator is connected with the successive approximation logic control circuit, and the successive approximation logic control circuit outputs digital signals, and is characterized in that:

all upper polar plates of the first capacitor array are connected with a first input end of the comparator, and the first input end of the comparator is connected with a switch S_a0And an input voltage signal V_INConnected to a capacitor C_a0The lower pole plate is connected with a reference voltage signal V_REFCapacitor C_a1～C_a(n-1)Respectively through a switch S_a1～S_a(n-1)Is connected with a reference voltage signal V_REFAll upper polar plates of the second capacitor array are connected with a second input end of the comparator, and the second input end of the comparator is connected with a switch S_b0And a reference voltage signal V_REFConnected to a capacitor C_b0The lower pole plate is connected with a reference voltage signal V_REFCapacitor C_b1～C_b(n-1)Respectively through a switch S_b1～S_b(n-1)Is connected with a reference voltage signal V_REF；

2. Analog-to-digital converter according to claim 1, characterized in that the reference voltage signal V_REFIs half of the maximum input voltage signal.

3. Analog-to-digital conversion according to claim 1Characterized by the switch S_a0、S_a1～S_a(n-1)、S_b0、S_b1～S_b(n-1)CMOS switches are used.

4. The analog-to-digital converter according to claim 1, characterized in that said comparator comprises three identical preamplifiers and one dynamic comparator connected in series.

5. The analog-to-digital converter according to claim 4, wherein the comparator employs input and output offset cancellation techniques.

6. The analog-to-digital converter according to claim 1, wherein the successive approximation logic control circuit outputs a control signal to control the switch S according to the comparison result of the comparator_a1～S_a(n-1)And S_b1～S_b(n-1)The switching specifically includes:

the comparator performs a k-th comparison, k<n, when the output result of the comparator is 1, the control signal switches the switch S_a(n-k)Grounding, when the output result of the comparator is 0, the control signal switches the switch S_b(n-k)And (4) grounding.