CN109194333A - A kind of composite construction gradually-appoximant analog-digital converter and its quantization method - Google Patents
A kind of composite construction gradually-appoximant analog-digital converter and its quantization method Download PDFInfo
- Publication number
- CN109194333A CN109194333A CN201810900483.9A CN201810900483A CN109194333A CN 109194333 A CN109194333 A CN 109194333A CN 201810900483 A CN201810900483 A CN 201810900483A CN 109194333 A CN109194333 A CN 109194333A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- switch
- serial
- digital
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
Abstract
A kind of composite construction gradually-appoximant analog-digital converter and its quantization method, belong to Analog-digital Converter technical field.Including digital-to-analogue conversion module, comparison module and Approach by inchmeal logic module, digital-to-analogue conversion module includes capacitor Weighting type D/A conversion unit and serial capacitance digital analog-converted unit, and Approach by inchmeal logic module includes that capacitor Weighting type Approach by inchmeal logic unit and serial Approach by inchmeal logic unit are respectively used to control capacitor Weighting type D/A conversion unit and serial capacitance digital analog-converted unit.The present invention is sampled using capacitor Weighting type D/A conversion unit and realizes the quantization to simulation input by two-step conversion, for the voltage signal that comparison module exports digital-to-analogue conversion module compared with reference signal, obtained comparison result is converted into the output code of composite construction gradually-appoximant analog-digital converter by Approach by inchmeal logic module.The present invention has many advantages, such as high area efficiency, low-power consumption and faster conversion speed.
Description
Technical field
The invention belongs to Analog-digital Converter technical field, in particular to the Approach by inchmeal analog-to-digital conversion of a kind of composite construction
Device and its quantization method.
Background technique
Analog-digital converter is widely used in the fields such as image procossing, digital video and biologic medical.And for application
For more and more extensive handhold mobile terminal equipment (such as imaging sensor), service life of the low-power consumption for product battery
There is vital effect.Simultaneously as people are more careful to the requirements at the higher level of the sensory experiences such as image quality, and pursuit
Data information, this requires analog-to-digital converters to need to have faster conversion speed and higher resolving accuracy.
Traditional N binary capacitor Weighting type gradual approaching A/D converter is as shown in Fig. 1, includes binary capacitor
Weighting type digital analog converter C-DAC101, sampling hold circuit S/H102, comparator CMP103 and Approach by inchmeal logic
SARLogic104.Wherein, binary capacitor Weighting type digital analog converter C-DAC101 output end is connected to comparator
The input negative terminal of CMP103, sampling hold circuit S/H102 output end are connected to the input anode of comparator CMP103, comparator
The output end of CMP103 is connected to the input terminal of Approach by inchmeal logic SAR Logic104, Approach by inchmeal logic SAR Logic104
Output end output binary capacitor Weighting type digital analog converter C-DAC101 switch control signal
Binary capacitor Weighting type successive approximation simulation digital quantizer in, timing control include sample phase and
Quantization stage.Sample phase samples input signal by sampling hold circuit S/H102.Quantization stage, in the driving of clock CLK
Under, since highest order quantifies capacitor, control logic is provided by Approach by inchmeal logic 104 and makes binary capacitor Weighting type digital
101 output end voltage of analog converter C-DAC switches, and then passes through comparator CMP103 for binary capacitor Weighting type
The sampled voltage V of 101 output end voltage of digital analog converter C-DAC and sampling hold circuit S/H102 outputHCompare, and
Comparator results are provided, Approach by inchmeal logic SAR Logic104 judges that this quantifies capacitor further according to the secondary comparison result at this time
Switchback whether is needed, and provides the control logic of next bit quantization capacitor, is so recycled, until lowest order quantization capacitor is completed
Switching.
As it can be seen that for binary capacitor Weighting type digital analog converter C-DAC101, the number of specific capacitance and
Area is exponentially increased with resolution, N, and huge capacitor number will lead to excessively high power consumption and area, the general this position tradition N two
The resolution ratio that system capacitor Weighting type gradual approaching A/D converter structure is realized is no more than 10.
It is as shown in Fig. 2 for the N serial gradual approaching A/D converters of condenser type, it include serial capacitance digital mould
Quasi- converter Serial-DAC201 (C1=C2), sampling hold circuit S/H202, comparator CMP203, serial Approach by inchmeal logic
204.Wherein, serial capacitance digital analog converter Serial-DAC201 output end is connected to the input of comparator CMP203
Negative terminal, sampling hold circuit S/H202 output end are connected to the input anode of comparator CMP203, the output of comparator CMP203
End is connected to the input terminal of serial Approach by inchmeal logic 204, and the output end of serial Approach by inchmeal logic 204 exports serial condenser type
The switch control signal of digital analog converter Serial-DAC201.
In the serial successive approximation simulation digital quantizer of condenser type, timing control equally includes sample phase and amount
The change stage.Sample phase samples input signal by sampling hold circuit S/H202.Quantization stage, in the driving of clock CLK
Under, serial Approach by inchmeal logic 204 to the concrete operations process of serial capacitance digital analog converter Serial-DAC201 such as
Shown in lower:
1) reseting stage.To the first serial capacitor C1Charging, the second serial capacitor C2It resets, switch motion are as follows: disconnect first
Switch S1, third switch S3With the 4th switch S4, it is closed second switch S2With the 5th switch S5。
2) charge allocated phase.If skipping the step at this time to quantify for the first time.Otherwise need according to it is upper several times
Quantized result is controlled with the serial output mode of first in first out to the first serial capacitor C1Charge or discharge operation.Switch motion:
Disconnect first switch S1With the 4th switch S4, it is closed the 5th switch S5, when last time quantization output code is 0, disconnect second switch
S2, it is closed third switch S3；When last time quantization output code is 1, third switch S is disconnected3, it is closed second switch S2。
3) the charge share stage.It will be stored in the first serial capacitor C on last stage1With the second serial capacitor C2Total electrical charge
Again it is evenly distributed on the two capacitors.Switch motion are as follows: disconnect second switch S2, third switch S3, the 4th switch S4With
Five switch S5, it is closed first switch S1。
4) voltage comparison phase.By the second serial capacitor C2Top crown output voltage be connected to the defeated of comparator CMP203
Enter negative terminal and the sampled voltage V with comparator CMP203 input anodeHRelatively and provide comparator results.Switch motion are as follows: disconnected
Open first switch S1, second switch S2, third switch S3With the 5th switch S5, it is closed the 4th switch S4。
Since highest order code value, according to above-mentioned control logic, loop back and forth like this, until lowest order code value output at
Function.Although for serial capacitance digital analog converter Serial-DAC201, no matter the serial successive approximation of condenser type
How the resolution, N of analog-digital converter increases, and specific capacitance number always remains 2, has very high area efficiency and low
The two excellent characteristics of power consumption.But in comparison with N binary capacitor Weighting type successive approximation simulation digital quantizers,
The periodicity of its quantization stage is promoted from N number of period before to existingA period.Higher resolution ratio means
More change-over periods, this proposes serious challenge to realization High Speed Analog digital quantizer.Worse in serial electricity
In appearance formula digital analog converter C-DAC201, since switch is directly connected with capacitor top crown, when switch disconnects closure
Additional channel charge will be introduced to capacitor, so that capacitor C2Output end voltage VDACGenerate it is non-linear, thus limit modulus turn
The various performances of parallel operation ADC, including integral nonlinearity (INL), differential nonlinearity (DNL), spurious-free dynamic range (SFDR), effectively
Digit (ENOB) etc.；Therefore the resolution ratio that the serial successive approximation simulation digital quantizer of general condenser type is realized is no more than 8.
Digital quantizer is simulated for the successive approximation of above two traditional structure, if it is considered that having used additionally
The input common mode electrical level of sampling hold circuit, comparator must satisfy input reference signal.However the limited common mode suppression of comparator
Ratio processed, the input imbalance for resulting in comparator is with input common mode electrical level correlation, to be degrading the whole of analog-digital converter
Body index.In general, the resolution ratio that the successive approximation simulation digital quantizer under this kind of sampling configuration is realized is no more than 8
Position.
Summary of the invention
For low area efficiency existing for above-mentioned traditional binary capacitor Weighting type successive approximation simulation digital quantizer
It is adopted with low speed and introducing channel charge existing for high power consumption, the serial successive approximation simulation digital quantizer of condenser type and tradition
For comparator input common mode electrical level with a series of shortcomings such as input signal correlation, the invention proposes a kind of compound under original mold formula
The gradually-appoximant analog-digital converter and its quantization method of structure, the composite construction gradually-appoximant analog-digital converter use capacitor weight
Formula D/A conversion unit 302 carries out sampling and realizes the quantization to simulation input by two-step conversion, and the first step is with electricity
Holding Weighting type D/A conversion unit 302 is that core is realized to high-order quantization；Second step is simulated with serial capacitance digital
Based on converting unit 301, by the second serial capacitor C in serial capacitance digital analog-converted unit 3012The charge of storage turns
It moves on on capacitor Weighting type D/A conversion unit 302, thus in the height of condenser type Weighting type D/A conversion unit 302
Position output end generates smaller plateau voltage to realize the conversion to low level；After electric charge transfer, since switch is opened or is closed
The channel charge for closing and introducing is inhibited well, therefore integrated circuit absorbs two kinds of conventional successives and approaches type analog-to-digital converter
The advantages of high area efficiency, low-power consumption and faster conversion speed, simultaneously because the optimization of sample mode is so that compare mould
The input common mode electrical level of block 303 ensure that the input imbalance of comparison module 303 is unrelated with input signal independently of input signal.
The technical solution of the present invention is as follows:
A kind of composite construction gradually-appoximant analog-digital converter, including digital-to-analogue conversion module, comparison module 303 and gradually
Logic module 304 is approached,
The digital-to-analogue conversion module includes capacitor Weighting type D/A conversion unit 302 and serial capacitance digital
The low level output end of analog-converted unit 301, the capacitor Weighting type D/A conversion unit 302 connects the serial capacitor
The output end of formula D/A conversion unit 301, high-order output end connect the input terminal of the comparison module 303；
Voltage signal that the comparison module 303 exports the capacitor Weighting type digital analog converter unit 302 with
Reference signal is compared, and obtained comparison result is converted into the composite construction by the Approach by inchmeal logic module 304
The output code of gradually-appoximant analog-digital converter；
The Approach by inchmeal logic module 304 includes that capacitor Weighting type Approach by inchmeal logic unit and serial Approach by inchmeal are patrolled
Unit is collected, the capacitor Weighting type Approach by inchmeal logic unit is for controlling the capacitor Weighting type D/A conversion unit
Switch in 302, the serial Approach by inchmeal logic unit is for controlling the serial capacitance digital analog-converted unit 301
In switch.
Specifically, the serial capacitance digital analog-converted unit 301 includes the first serial capacitor C1, the second serial electricity
Hold C2, first switch S1, second switch S2, third switch S3, the 4th switch S4With the 5th switch S5, wherein the first serial capacitor C1
With the second serial capacitor C2Capacitance it is equal；
First switch S1It connects in the first serial capacitor C1Top crown and the second serial capacitor C2Top crown between；
Second switch S2It connects in the first serial capacitor C1Top crown and high reference voltage VTBetween；
Third switch S3It connects in the first serial capacitor C1Top crown and low reference voltage VBBetween；
4th switch S4One end connect the second serial capacitor C2Top crown, the other end is as the serial condenser type number
Type matrix intends the output end of converting unit 301；
5th switch S5It connects in the second serial capacitor C2Top crown and low reference voltage VBBetween；
First serial capacitor C1With the second serial capacitor C2Bottom crown connect low reference voltage VB。
Specifically, the capacitor Weighting type D/A conversion unit 302 includes high section capacitor array, low section of capacitor battle array
Column, coupled capacitor CSAnd reset switch；
The high section capacitor array includes multiple capacitors, and the top crown of high all capacitors of section capacitor array is all connected with institute
The high-order output end of capacitor Weighting type D/A conversion unit 302 is stated, bottom crown passes through switch respectively and connects low reference voltage
VB, high reference voltage VTOr input voltage VIN；
The low section of capacitor array includes multiple capacitors, wherein the top crown of the low section of capacitor array lowest order capacitor is logical
The top crown of the low section of capacitor array remaining capacitor is connected after crossing switch and connects the capacitor Weighting type digital-to-analogue conversion
The low level output end of unit 302, bottom crown connect low reference voltage VB；The lower pole of remaining capacitor of the low section of capacitor array
Plate connects low reference voltage V after passing through switch respectivelyBOr high reference voltage VT；
Coupled capacitor CSConnect high-order output end and the low level output in the capacitor Weighting type D/A conversion unit 302
Between end；
The reset switch includes high section reset switch SHWith low section of reset switch SL, the high section reset switch SHIt connects
The high-order output end and high reference voltage V of the capacitor Weighting type D/A conversion unit 302TBetween, the low section of reset
Switch SLConnect the low level output end and low reference voltage V in the capacitor Weighting type D/A conversion unit 302BBetween.
A kind of quantization method of composite construction gradually-appoximant analog-digital converter, the composite construction Approach by inchmeal analog-to-digital conversion
Device includes digital-to-analogue conversion module, and the digital-to-analogue conversion module includes capacitor Weighting type D/A conversion unit 302
With serial capacitance digital analog-converted unit 301；
The serial capacitance digital analog-converted unit 301 includes the first serial capacitor C1, the second serial capacitor C2,
One switch S1, second switch S2, third switch S3, the 4th switch S4With the 5th switch S5, wherein the first serial capacitor C1With second
Serial capacitor C2Capacitance it is equal；
First switch S1It connects in the first serial capacitor C1Top crown and the second serial capacitor C2Top crown between；
Second switch S2It connects in the first serial capacitor C1Top crown and high reference voltage VTBetween；
Third switch S3It connects in the first serial capacitor C1Top crown and low reference voltage VBBetween；
4th switch S4One end connect the second serial capacitor C2Top crown, the other end is as the serial condenser type number
Type matrix intends the output end of converting unit 301；
5th switch S5It connects in the second serial capacitor C2Top crown and low reference voltage VBBetween；
First serial capacitor C1With the second serial capacitor C2Bottom crown connect low reference voltage VB；
The capacitor Weighting type D/A conversion unit 302 includes high section capacitor array and low section of capacitor array；
The high section capacitor array includes M+1 quantization capacitor, and the top crown of the M+1 quantization capacitor is all connected with described
The high-order output end of capacitor Weighting type D/A conversion unit 302, bottom crown pass through switch respectively and connect low reference voltage
VB, high reference voltage VTOr input voltage VIN；
The low section of capacitor array includes L quantization capacitor, the upper pole of the low section of capacitor array lowest order quantization capacitor
Plate quantifies capacitor top crown switch S by lowest orderTConnecting the low section of capacitor array afterwards, remaining quantifies the top crown of capacitor simultaneously
The low level output end of the capacitor Weighting type D/A conversion unit 302 is connected, bottom crown connects low reference voltage VB；Institute
State low section of capacitor array remaining quantization capacitor bottom crown pass through respectively switch after connect low reference voltage VBOr high reference voltage
VT；
The reset switch includes high section reset switch SHWith low section of reset switch SL, the high section reset switch SHIt connects
The high-order output end and high reference voltage V of the capacitor Weighting type D/A conversion unit 302TBetween, the low section of reset
Switch SLConnect the low level output end and low reference voltage V in the capacitor Weighting type D/A conversion unit 302BBetween；
The composite construction gradually-appoximant analog-digital converter carries out P+Q quantization, and P=M+L, Q are positive integer, the mistake of quantization
Journey includes the following steps:
A, the 4th switch S is disconnected4, the digital-to-analogue conversion module only includes the capacitor Weighting type digital-to-analogue conversion
Unit 302 is quantified to obtain the composite construction Approach by inchmeal mould to the capacitor Weighting type D/A conversion unit 302
High P of number converter output code；
B, it is closed the 4th switch S4, the digital-to-analogue conversion module includes the capacitor Weighting type digital-to-analogue conversion list
Member 302 and serial capacitance digital analog-converted unit 301 successively carry out low Q quantization to the digital-to-analogue conversion module
Low Q of the composite construction gradually-appoximant analog-digital converter output code are obtained, wherein specific step is as follows for jth time quantization, j
For positive integer and P+1≤j≤P+Q:
B1, first switch S is disconnected1, third switch S3With the 4th switch S4, it is closed second switch S2With the 5th switch S5, will
First serial capacitor C1Charge be precharged to CU×(VT-VB), the second serial capacitor C2Charge initialize to 0；
B2, second switch S is disconnected2, third switch S3, the 4th switch S4With the 5th switch S5, it is closed first switch S1, by
One serial capacitor C1With the second serial capacitor C2Total electrical charge be evenly distributed to the first serial capacitor C1With the second serial capacitor C2
On；
It is b3, the connection of the bottom crowns of all quantization capacitors in the capacitor Weighting type D/A conversion unit 302 is low
Reference voltage VB, it is closed the high section reset switch SHWith low section of reset switch SLBy the capacitor Weighting type digital-to-analogue conversion
The top crown of all quantization capacitors of low section of capacitor array connects low reference voltage V in unit 302B, by the high section capacitor battle array
The top crown of all quantization capacitors of column connects high reference voltage VT；
Step b5 is carried out when progress step b6, j > P+1 when b4, j=P+1；
B5, until P+1 it is since jth -1 of the composite construction gradually-appoximant analog-digital converter output code
Only, successively judge it is serial to first according to s numerical value of the composite construction gradually-appoximant analog-digital converter output code
Capacitor C1Charge or discharge are carried out, wherein s is positive integer, P+1≤s≤j-1, specific judgment method are as follows:
B51, when s of the composite construction gradually-appoximant analog-digital converter output code being 0, disconnect second switch
S2, it is closed third switch S3, by the first serial capacitor C1Charge be discharged to 0；When the composite construction Approach by inchmeal analog-to-digital conversion
When s of device output code are 1, third switch S is disconnected3, it is closed second switch S2, by the first serial capacitor C1Charge charging
To CU×(VT-VB)；
B52, step b2 is repeated；
B6, the high section reset switch S is successively disconnectedH, lowest order quantify capacitor top crown switch STWith low section of reset switch
SL；
B7, first switch S is disconnected1With the 5th switch S5, it is closed the 4th switch S4, by the second serial capacitor C2Described in access
Capacitor Weighting type D/A conversion unit 302 obtains the high-order output of the capacitor Weighting type digital analog converter unit 302
The output signal at end；
B8, the output signal of the high-order output end of the capacitor Weighting type digital analog converter unit 302 and reference are believed
It number is compared, obtains the jth position output code of the composite construction gradually-appoximant analog-digital converter.
The invention has the benefit that digital-to-analogue conversion module of the invention includes capacitor Weighting type digital-to-analogue conversion
Unit 302 and serial capacitance digital analog-converted unit 301, so that entire quantizing process is divided into two steps, the first step with
Capacitor Weighting type D/A conversion unit 302 is that core realizes that second step is to high P of quantization with serial capacitance digital mould
Based on quasi- converting unit 301, by reasonable timing by the second serial capacitor C2The electric charge transfer of storage is to capacitor Weighting type
On D/A conversion unit, so that the output end in digital-to-analogue conversion module generates smaller plateau voltage to realize to low
Q conversions；And the channel charge introduced due to opening or closing is because the transfer effect of charge turns in digital simulation
The output end of mold changing block is inhibited well, therefore specific capacitance sum is by N condenser type binary weights successive approximations
The 2 of analog-digital converterNIt is down to 2M+2L+ 2, the change-over period is by N serial gradual approaching A/D converters of condenser typeIt is reduced toTherefore the present invention has very high area efficiency, low-power consumption and faster conversion speed
Degree.Since the composite construction gradually-appoximant analog-digital converter uses section electricity high in capacitor Weighting type D/A conversion unit 302
Hold sampling, so that the input common mode electrical level of comparator independently of input signal, ensure that comparator input imbalance is believed with input
It is number unrelated.
Detailed description of the invention
Fig. 1 is the circuit diagram of N condenser type binary weights gradual approaching A/D converters of tradition.
Fig. 2 is the circuit diagram of the N serial gradual approaching A/D converters of condenser type of tradition.
Fig. 3 is a kind of structural schematic diagram of composite construction gradually-appoximant analog-digital converter proposed by the present invention.
Fig. 4 is a kind of composite construction fully differential gradually-appoximant analog-digital converter structural schematic diagram proposed by the present invention.
Fig. 5 is a kind of dynamic property Monte Carlo simulation of composite construction gradually-appoximant analog-digital converter proposed by the present invention
Result schematic diagram.
Fig. 6 is a kind of static properties Monte Carlo simulation of composite construction gradually-appoximant analog-digital converter proposed by the present invention
Result schematic diagram.
Fig. 7 is that a kind of capacitor of composite construction gradually-appoximant analog-digital converter proposed by the present invention switches power consumption simulation result
Schematic diagram.
Specific embodiment
With reference to the accompanying drawing, technical solution of the present invention is further illustrated by embodiment.
The overall structure diagram of composite construction gradually-appoximant analog-digital converter proposed by the present invention a kind of as shown in figure 3,
Including digital-to-analogue conversion module, comparison module 303 and Approach by inchmeal logic module 304.Wherein digital-to-analogue conversion module packet
Include capacitor Weighting type D/A conversion unit 302 and serial capacitance digital analog-converted unit 301, capacitor Weighting type number
The low level output end of analog-converted unit 302 connects the output end of serial capacitance digital analog-converted unit 301, and a high position is defeated
The input terminal of outlet connection comparison module 303.Comparison module 303 is high-order by capacitor Weighting type digital analog converter unit 302
The voltage signal of output end output is compared with reference signal, and obtained comparison result passes through Approach by inchmeal logic module 304
It is converted into the output code of composite construction gradually-appoximant analog-digital converter.Wherein Approach by inchmeal logic module 304 includes capacitor weight
Formula Approach by inchmeal logic unit and serial Approach by inchmeal logic unit, capacitor Weighting type Approach by inchmeal logic unit are exported for controlling
The switch control signal switched in capacitor Weighting type D/A conversion unit 302 processed, serial Approach by inchmeal logic unit output
For controlling the switching signal switched in serial capacitance digital analog-converted unit 301.
The structure of serial capacitance digital analog-converted unit 301 is as shown in figure 3, include the first serial capacitor C1, second
Serial capacitor C2, first switch S1, second switch S2, third switch S3, the 4th switch S4With the 5th switch S5, wherein first is serial
Capacitor C1With the second serial capacitor C2Capacitance it is equal, the first serial capacitor C in the present embodiment1With the second serial capacitor C2All
For unit capacitor CU, bottom crown is all connected with low reference voltage VB.Second switch S2For charge charging switch, connect serial first
Capacitor C1Top crown and high reference voltage VTBetween, third switch S3For charge discharge switch, connect in the first serial capacitor C1's
Top crown and low reference voltage VBBetween, second switch S2With third switch S3For controlling to the first serial capacitor C1Charge and discharge；
First switch S1For charge redistribution switch, connect in the first serial capacitor C1With the second serial capacitor C2Top crown between, be used for
Control the first serial capacitor C1With the second serial capacitor C2Upper charge is redistributed；4th switch S4For output switch, one end
Connect the second serial capacitor C2Top crown, output end of the other end as serial capacitance digital analog-converted unit be used for
The output of serial capacitance digital analog-converted unit is connected to capacitor Weighting type D/A conversion unit；5th switch S5
For reset switch, connect in the second serial capacitor C2Top crown and low reference voltage VBBetween, for the second serial capacitor C2Into
Row resets.
Capacitor Weighting type digital analog converter module 302 includes capacitor array, and capacitor array can be segmental structure
Can be not segmental structure, connected the capacitor array of segmentation by coupled capacitor in segmental structure, in the present embodiment with
The connection of its structure and the course of work are described in detail for the capacitor Weighting type digital analog converter module 302 of segmentation structure.
The structure of segmented capacitive array is given as shown in Figure 3, and capacitor Weighting type digital analog converter module 302 is wrapped
Include capacitor array, the coupled capacitor C of segmentedSAnd reset switch.Capacitor array includes high section capacitor array and low section of capacitor battle array
Column, wherein high section of capacitor array includes M+1 quantization capacitor, M is positive integer, high all quantization capacitor top crowns of section capacitor array
It is all connected with the high-order output end of capacitor Weighting type D/A conversion unit 302, its bottom crown passes through respectively in quantizing process
Switch connects low reference voltage VBOr high reference voltage VT；Due to being sampled using high section capacitor, its bottom crown is needed in sampling process
Input signal V is connected to by sampling switchIN.Low section of capacitor array includes L quantization capacitor, and L is positive integer, wherein low section
The top crown of the lowest order quantization capacitor of capacitor array passes through switch STCapacitor Weighting type D/A conversion unit 302 is connected afterwards
Low level output end, bottom crown connects low reference voltage VB；The top crown of remaining quantization capacitor of low section of capacitor array connects
The low level output end of capacitor Weighting type D/A conversion unit 302 is connect, bottom crown connects low reference electricity after passing through switch respectively
Press VBOr high reference voltage VT；Coupled capacitor CSIt connects in the high-order output end of capacitor Weighting type D/A conversion unit 302 and low
Between the output end of position.Reset switch includes high section reset switch SHWith low section of reset switch SL, high section reset switch SHIt connects in capacitor
The high-order output end and high reference voltage V of Weighting type D/A conversion unit 302TBetween, low section of reset switch SLIt connects in capacitor
The low level output end of Weighting type D/A conversion unit 302 and low reference voltage VBBetween.
To all quantization capacitors in the capacitor Weighting type D/A conversion unit 302 of segmented according to highest order Ca21It arrives
Lowest order Ca2M+L+1It is numbered, remembers Ca2i(i=1,2,3 ..., M+L+2), capacitance size, as shown in formula (1):
Wherein CUFor unit capacitance, in order to guarantee the weight of segmented capacitive Weighting type D/A conversion unit 302
Equal ratios, coupled capacitor CSCapacitance be
The weight Weight of high section capacitor arrayMSB(i) with the weight Weight of low section of capacitor arrayLSB(i) relationship is such as
Shown in formula (2):
Wherein CMSB_TotFor the sum of the quantization capacitance of high section capacitor array, CLSB_TotFor the quantization electricity of low section of capacitor array
The sum of capacitance, CSFor the capacitance of coupled capacitor.
When the present invention is applied in single-ended analog-digital converter, an input terminal of comparison module 303 connects capacitor Weighting type
The voltage signal V of the high-order output end output of digital analog converter module 302dach, it is electric that another input terminal connects high reference
Press VTAs reference signal.
In addition to the application in single-ended analog-digital converter, the gradually-appoximant analog-digital converter of composite construction proposed by the present invention is also
It can be used for the quantization to fully differential signal, the two of comparison module input terminal is separately connected the digital simulation of differential configuration at this time
The difference output end of conversion module, differential input signal are defeated by the generation of capacitor Weighting type D/A conversion unit 402 difference
The difference of differential output signal is compared by signal out, comparison module with reference voltage, and reference voltage is 0 at this time.Shown in Fig. 4
For composite construction fully differential gradually-appoximant analog-digital converter structural schematic diagram, digital-to-analogue conversion module including differential configuration,
Comparison module 403 and Approach by inchmeal logic module 404.Wherein the digital-to-analogue conversion module of differential configuration includes differential configuration
The capacitor Weighting type D/A conversion unit 402 of serial capacitance digital analog-converted unit 401 and differential configuration.Capacitor power
The difference output end of weight formula D/A conversion unit 402 is connected to two input terminals of comparison module 403, comparison module
403 compare 402 differential output signal V of capacitor Weighting type digital analog converter unitdach,nWith Vdach,n, the comparison knot that will obtain
Fruit is converted into the output code of composite construction gradually-appoximant analog-digital converter by Approach by inchmeal logic module 404.Similarly in single-ended
Analog-digital converter structure, Approach by inchmeal logic module 404 include capacitor Weighting type Approach by inchmeal logic unit and serially gradually force
Nearly logic unit, capacitor Weighting type Approach by inchmeal logic unit export the capacitor Weighting type digital simulation for controlling differential configuration
The switch control signal switched in converting unit 402, serial Approach by inchmeal logic unit export the string for controlling differential configuration
The switching signal switched in row capacitance digital analog-converted unit 401.
The quantization digit of composite construction gradually-appoximant analog-digital converter proposed by the present invention is P+Q, and quantization method is divided into
Two parts, first part are high P of quantization, and second part is low Q of quantization, and wherein P and Q is positive integer, and P is by capacitor
Weighting type D/A conversion unit determines, with capacitor Weighting type D/A conversion unit 302 shown in Fig. 3 using segmentation knot
The process for illustrating quantization for the single-ended gradually-appoximant analog-digital converter of structure, due to capacitor Weighting type D/A conversion unit
A 302 high section capacitor arrays include M+1 quantization capacitor, and low section of capacitor array includes L quantization capacitor, then P=M+L.
When first part carries out high P of quantization, by the 4th switch S4It disconnects, digital-to-analogue conversion module is only wrapped at this time
Capacitor Weighting type D/A conversion unit 302 is included, Approach by inchmeal logic module 304 also only has capacitor Weighting type Approach by inchmeal to patrol
Cell operation is collected, high P of quantization is identical as traditional quantification manner of capacitor Weighting type gradual approaching A/D converter,
Under the driving of clock CLK, since highest order capacitor, control logic is provided by capacitor Weighting type Approach by inchmeal logic unit and is made
302 output end voltage of capacitor Weighting type D/A conversion unit switches, and then passes through comparator module 303 and high reference
Voltage VTCompare, obtains comparison result, while capacitor Weighting type Approach by inchmeal logic unit judges further according to the secondary comparison result
Whether this capacitor needs switchback, and provides the control logic of next bit capacitor, so recycles, until lowest order capacitor is completed
Switching, Approach by inchmeal logic module 304 obtain composite construction Approach by inchmeal modulus according to the comparison result switched each time
High P of converter output code.
After high P of quantization is completed, encoded according to low bit quantification in serial capacitance digital analog-converted unit
Second serial capacitor C2It charged, discharged and charge redistributes operation, be closed the 4th switch S4, by serial capacitance digital
Analog-converted unit 301 is added in digital-to-analogue conversion module, will be stored in the second serial capacitor C2On charge pass through electricity
The mode for holding exchange is transferred in capacitor Weighting type D/A conversion unit 302, to turn in capacitor Weighting type digital simulation
The output end for changing unit 302 generates smaller plateau voltage and realizes Q of quantization low to second part, and wherein jth time quantifies
Specific step is as follows, and j is positive integer and P+1≤j≤P+Q:
1, it needs before low K each quantization to the first serial capacitor C1With the second serial capacitor C2It carries out initially multiple
Bit manipulation disconnects first switch S by serial Approach by inchmeal logic unit output switch control signal1, third switch S3With the 4th
Switch S4, it is closed second switch S2With the 5th switch S5, thus by the first serial capacitor C1Quantity of electric charge Q1It is precharged to CU×
(VT-VB), the second serial capacitor C2Quantity of electric charge Q2It initializes to 0；
2, it after initialization terminates, needs the first serial capacitor C1With the second serial capacitor C2Total electrical charge carry out again
Distribution disconnects second switch S by serial Approach by inchmeal logic unit output switch control signal2, third switch S3, the 4th open
Close S4With the 5th switch S5, it is closed first switch S1, by the first serial capacitor C1With the second serial capacitor C2Total electrical charge average mark
It is fitted on the first serial capacitor C1With the second serial capacitor C2On；
But in second switch S2With the 5th switch S5It can be respectively to the first serial capacitor C while shutdown1It is serial with second
Capacitor C2Inject a certain amount of channel charge+Qchs2、-Qchs5；In first switch S1When unlatching, and certain quantity of electric charge-can be absorbed
Qchs1,i, therefore the first serial capacitor C after charge share terminates1Quantity of electric charge Q1With the second serial capacitor C2Quantity of electric charge Q2
Respectively as shown in formula (3):
3, it before the electric charge transfer for carrying out following step, needs to answer capacitor Weighting type D/A conversion unit
Bit manipulation, to guarantee the second serial capacitor C2Charge can correctly shift, reset the specific steps are by capacitor Weighting type number
The bottom crown that type matrix intends all quantization capacitors in converting unit connects low reference voltage VB, closed reduction switch is by capacitor weight
The top crown of all quantization capacitors of 302 low section of capacitor array connects low reference voltage V in formula D/A conversion unitB,
The top crown of all quantization capacitors of high section capacitor array connects high reference voltage VT；Step 3 can be same with step 1 and step 2
Shi Jinhang；
4, after above step, if being to carry out j=P+1 quantizations at this time, step 6 is carried out；If being at this time
The quantization for carrying out j > P+1, then carry out step 5；
5, until since jth -1 of composite construction gradually-appoximant analog-digital converter output code until P+1, according to
S numerical value of composite construction gradually-appoximant analog-digital converter output code judges the first serial capacitor C1State to carry out
Multiple charge share, wherein s is positive integer, P+1≤s≤j-1 is first exported according to composite construction gradually-appoximant analog-digital converter
Jth -1 of code judges the first serial capacitor C1State after carry out a charge share, that is, step 2, further according to composite construction by
The secondary jth for approaching analog-digital converter output code -2 judges the first serial capacitor C1State after carry out a charge share, directly
The first serial capacitor C is judged to according to P+1 of composite construction gradually-appoximant analog-digital converter output code1State after carry out
Step 6 is carried out again after charge share, wherein judging the first serial capacitor C1State method particularly includes:
5.1, when being 0 for s of composite construction gradually-appoximant analog-digital converter output code, second switch S is disconnected2, close
Close third switch S3, by the first serial capacitor C1Charge be discharged to 0；When composite construction gradually-appoximant analog-digital converter output code
S be 1 when, disconnect third switch S3, it is closed second switch S2, by the first serial capacitor C1Charge charging to CU×(VT-
VB)；
5.2, step 2 is repeated, i.e., disconnects second by serial 301 output switch control signal of Approach by inchmeal logic unit and opens
Close S2, third switch S3, the 4th switch S4With the 5th switch S5, it is closed first switch S1, by the first serial capacitor C1With the second string
Row capacitor C2Total electrical charge be evenly distributed to the first serial capacitor C1With the second serial capacitor C2On；
6, before electric charge transfer, high section capacitor reset switch S is successively disconnectedH, lowest order quantify capacitor CM+L+1Top crown is opened
Close STWith low section of reset switch SL；Due to channel electrical pumping, low section of capacitor array top crown nod charge is not 0, but high section is electric
Hold reset switch SH, lowest order quantify capacitor CM+L+1Top crown switch STWith low section of reset switch SLThree switches inject the quantity of electric charge
The sum of QS；
7, electric charge transfer is carried out, first switch S is disconnected1With the 5th switch S5, it is closed the 4th switch S4, by the second serial electricity
Hold C2Access capacitor Weighting type D/A conversion unit 302；It at this time can be respectively to the second serial capacitor C2Injection and absorption are certain
Channel charge-the Q of amountchs1,o、+Qchs4.Pole on low section of capacitor array of final capacitor Weighting type D/A conversion unit 302
Shown in plate charge such as formula (4):
8, after electric charge transfer terminates, capacitor Weighting type Approach by inchmeal logic unit is opened according to the generation of high P quantization encoding
The quantization capacitor bottom crown switch for closing control signal control capacitor Weighting type D/A conversion unit 302, obtains capacitor weight
302 output end voltage signal V of formula D/A conversion unitdach, as shown in formula (5):
Wherein CMSB_Tot=2M×CU, CLSB_Tot=(2L-1)×CU。
9, by 302 output end voltage signal V of capacitor Weighting type D/A conversion unitdachWith high reference voltage VTCompare,
Obtain the jth position output code of composite construction gradually-appoximant analog-digital converter.
By formula (5) it can be found that influence of the channel charge of switch MOS to output voltage has been attenuated 2M+L+2L-1
Times.In specific capacitance CU=100fF, high reference voltage VT=1.9V, low reference voltage VBWhen=0.7V, suitable switch is set
And virtual switch size, it can be by channel charge in the second serial capacitor C2The voltage deviation of introducing is controlled in 3 δ≤5mV, i.e. formula
(6):
Therefore gradual approaching A/D converter serial for condenser type, resolution ratio are usually no more than 8.But pass through charge
Transfer techniques can inhibit influence of the channel charge to output voltage significantly.Work as P+Q=14, P=9, M=6, when L=3, channel
The deviation that charge injection generates is that 9.63 μ V of 5mV/519 ≈ is much smaller than 14 1LSB=72.82 μ V.Therefore high section capacitor top crown
Output end voltage VdachFormula (7) can be rewritten as with abbreviation:
The output end voltage V of high at this time section of capacitor top crowndachVariable quantity be equivalent to capacitor Weighting type digital simulation turn
Change unit lowest order quantization capacitor CM+L+1The half of weight, thus by resolution ratio from M+L continuation to M+L+1.
To a kind of composite construction gradually-appoximant analog-digital converter progress matlab emulation proposed by the present invention, the present invention is obtained
Dynamic property (spurious-free dynamic range SFDR, number of significant digit ENOB) Monte Carlo simulation result schematic diagram, static properties it is (micro-
Point non-linear DNL, integral nonlinearity INL) Monte Carlo simulation result schematic diagram and capacitor switch power consumption simulation result schematic diagram,
Respectively as shown in Fig. 5, Fig. 6 and Fig. 7, in emulation setting, unit capacitance values take CU=100uf, specific capacitance mismatch error areMonte Carlo simulation number is 1000 times.
From simulation result as can be seen that the composite construction gradually-appoximant analog-digital converter is in the premise for guaranteeing high area efficiency
Under still have good dynamic property and outstanding Static State Index, spurious-free dynamic range (SFDR), number of significant digit (ENOB),
Differential nonlinearity (DNL), integral nonlinearity (INL) 1000 average value of emulation be respectively 88.5dB, 13.21Bit,
0.994LSB,1.655LSB.Since integral capacitor array has high area efficiency, switching capacity switching power consumption is only
77.8662CV2.Hence it is demonstrated that composite construction gradually-appoximant analog-digital converter proposed by the present invention has outstanding performance indicator.
Capacitor Weighting type digital analog converter in conventional condenser binary weights gradual approaching A/D converter
Principle based on charge conservation, that is to say, that the initial charge of conventional condenser binary weights gradual approaching A/D converter
It is fixed, is also to remain unchanged in quantizing process, if modification will lead to quantization mistake.And individually condenser type is serial
It is almost exactly the structure to fail that successive approximation, which simulates digital quantizer, under current CMOS technology, because of the original of charge injection
Demand because cannot achieve high-speed, high precision completely is just never reused since being suggested this framework in 1978
It crosses.A kind of composite construction gradually-appoximant analog-digital converter and its quantization method proposed by the present invention, due to its digital-to-analogue conversion
Module includes 302 two parts of serial capacitance digital analog-converted unit 301 and capacitor Weighting type D/A conversion unit,
To which entire quantizing process is divided into two-step quantization: the first step is with capacitor Weighting type D/A conversion unit 302 for core
The heart is realized to high P of quantization；Second step is based on serial capacitance digital analog-converted unit 301, by the second serial electricity
Hold C2In the electric charge transfer of storage to capacitor Weighting type D/A conversion unit 302, thus in capacitor Weighting type digital simulation
The output end of converting unit 302 generates smaller plateau voltage to realize to low Q of conversion.Quantizing process combination electric charge transfer
Method, the charge of serial capacitance digital analog-converted unit is rationally transferred to capacitor Weighting type D/A conversion unit
In, the initial charge amount of capacitor Weighting type D/A conversion unit is had modified, and due to charge transfer effect, so that due to opening
It closes the channel charge that opens or closes and introduce to be inhibited well, therefore integrated circuit has very high area efficiency, low
Power consumption and faster conversion speed.Since capacitor Weighting type number can be used in the composite construction gradually-appoximant analog-digital converter
High section capacitor sampling in analog-converted unit 302, so that the input common mode electrical level of comparison module guarantees independently of input signal
Comparison module input imbalance is with input signal unrelated.
It is worth noting that although a kind of composite construction gradually-appoximant analog-digital converter proposed by the present invention and its quantization side
The content of method discloses as above by way of example, and however, it is not intended to limit the invention, if those skilled in the art,
It does not depart from the unsubstantiality that spirit of the invention is done to be altered or modified, all should belong to the model of the claims in the present invention protection
It encloses.
Claims (4)
1. a kind of composite construction gradually-appoximant analog-digital converter, including digital-to-analogue conversion module, comparison module (303) and gradually
Logic module (304) are approached,
It is characterized in that, the digital-to-analogue conversion module includes capacitor Weighting type D/A conversion unit (302) and serial
The low level output end of capacitance digital analog-converted unit (301), the capacitor Weighting type D/A conversion unit (302) connects
The output end of the serial capacitance digital analog-converted unit (301) is connect, high-order output end connects the comparison module
(303) input terminal；
Voltage signal that the comparison module (303) exports the capacitor Weighting type digital analog converter unit (302) with
Reference signal is compared, and obtained comparison result is converted into the composite junction by the Approach by inchmeal logic module (304)
The output code of structure gradually-appoximant analog-digital converter；
The Approach by inchmeal logic module (304) includes capacitor Weighting type Approach by inchmeal logic unit and serial Approach by inchmeal logic
Unit, the capacitor Weighting type Approach by inchmeal logic unit is for controlling the capacitor Weighting type D/A conversion unit
(302) switch in, the serial Approach by inchmeal logic unit is for controlling the serial capacitance digital analog-converted unit
(301) switch in.
2. composite construction gradually-appoximant analog-digital converter according to claim 1, which is characterized in that the serial condenser type
D/A conversion unit (301) includes the first serial capacitor (C1), the second serial capacitor (C2), first switch (S1), second open
Close (S2), third switch (S3), the 4th switch (S4) and the 5th switch (S5), wherein the first serial capacitor (C1) and the second serial electricity
Hold (C2) capacitance it is equal；
First switch (S1) connect in the first serial capacitor (C1) the serial capacitor (C of top crown and second2) top crown between；
Second switch (S2) connect in the first serial capacitor (C1) top crown and high reference voltage (VT) between；
Third switchs (S3) connect in the first serial capacitor (C1) top crown and low reference voltage (VB) between；
4th switch (S4) one end connect the second serial capacitor (C2) top crown, the other end is as the serial condenser type number
Type matrix intends the output end of converting unit (301)；
5th switch (S5) connect in the second serial capacitor (C2) top crown and low reference voltage (VB) between；
First serial capacitor (C1) and the second serial capacitor (C2) bottom crown connect low reference voltage (VB)。
3. composite construction gradually-appoximant analog-digital converter according to claim 1, which is characterized in that the capacitor Weighting type
D/A conversion unit (302) includes high section capacitor array, low section of capacitor array, coupled capacitor (CS) and reset switch；
The high section capacitor array includes multiple capacitors, and the top crown of high all capacitors of section capacitor array is all connected with the electricity
Hold the high-order output end of Weighting type D/A conversion unit (302), bottom crown passes through switch respectively and connects low reference voltage
(VB), high reference voltage (VT) or input voltage (VIN)；
The low section of capacitor array includes multiple capacitors, wherein the top crown of the low section of capacitor array lowest order capacitor is by opening
The top crown of the low section of capacitor array remaining capacitor is connected behind pass and connects the capacitor Weighting type D/A conversion unit
(302) low level output end, bottom crown connect low reference voltage (VB)；The lower pole of remaining capacitor of the low section of capacitor array
Plate connects low reference voltage (V after passing through switch respectivelyB) or high reference voltage (VT)；
Coupled capacitor (CS) connect the capacitor Weighting type D/A conversion unit (302) high-order output end and low level output
Between end；
The reset switch includes high section reset switch (SH) and low section of reset switch (SL), the high section reset switch (SH) connect
In the high-order output end and high reference voltage (V of the capacitor Weighting type D/A conversion unit (302)T) between, it is described low
Section reset switch (SL) connect low level output end and low reference voltage in the capacitor Weighting type D/A conversion unit (302)
(VB) between.
4. a kind of quantization method of composite construction gradually-appoximant analog-digital converter, which is characterized in that the composite construction is gradually forced
Near-lying mode number converter includes digital-to-analogue conversion module, and the digital-to-analogue conversion module includes that capacitor Weighting type digital simulation turns
Change unit (302) and serial capacitance digital analog-converted unit (301)；
The serial capacitance digital analog-converted unit (301) includes the first serial capacitor (C1), the second serial capacitor (C2)、
First switch (S1), second switch (S2), third switch (S3), the 4th switch (S4) and the 5th switch (S5), wherein first is serial
Capacitor (C1) and the second serial capacitor (C2) capacitance it is equal；
First switch (S1) connect in the first serial capacitor (C1) the serial capacitor (C of top crown and second2) top crown between；
Second switch (S2) connect in the first serial capacitor (C1) top crown and high reference voltage (VT) between；
Third switchs (S3) connect in the first serial capacitor (C1) top crown and low reference voltage (VB) between；
4th switch (S4) one end connect the second serial capacitor (C2) top crown, the other end is as the serial condenser type number
Type matrix intends the output end of converting unit (301)；
5th switch (S5) connect in the second serial capacitor (C2) top crown and low reference voltage (VB) between；
First serial capacitor (C1) and the second serial capacitor (C2) bottom crown connect low reference voltage (VB)；
The capacitor Weighting type D/A conversion unit (302) includes high section capacitor array and low section of capacitor array；
The high section capacitor array includes M+1 quantization capacitor, and the top crown of the M+1 quantization capacitor is all connected with the capacitor
The high-order output end of Weighting type D/A conversion unit (302), bottom crown pass through switch respectively and connect low reference voltage
(VB), high reference voltage (VT) or input voltage (VIN)；
The low section of capacitor array includes L quantization capacitor, and the top crown of the low section of capacitor array lowest order quantization capacitor is logical
Cross lowest order quantization capacitor top crown switch (ST) connecting the low section of capacitor array afterwards, remaining quantifies the top crown of capacitor and company
The low level output end of the capacitor Weighting type D/A conversion unit (302) is connect, bottom crown connects low reference voltage (VB)；
The bottom crown of remaining quantization capacitor of the low section of capacitor array connects low reference voltage (V after passing through switch respectivelyB) or high reference
Voltage (VT)；
The reset switch includes high section reset switch (SH) and low section of reset switch (SL), the high section reset switch (SH) connect
In the high-order output end and high reference voltage (V of the capacitor Weighting type D/A conversion unit (302)T) between, it is described low
Section reset switch (SL) connect low level output end and low reference voltage in the capacitor Weighting type D/A conversion unit (302)
(VB) between；
The composite construction gradually-appoximant analog-digital converter carries out P+Q quantization, and P=M+L, Q are positive integer, the process packet of quantization
Include following steps:
A, the 4th switch (S is disconnected4), the digital-to-analogue conversion module only includes the capacitor Weighting type digital-to-analogue conversion list
First (302), are quantified to obtain the composite construction Approach by inchmeal to the capacitor Weighting type D/A conversion unit (302)
High P of analog-digital converter output code；
B, the 4th switch (S of closure4), the digital-to-analogue conversion module includes the capacitor Weighting type D/A conversion unit
(302) and serial capacitance digital analog-converted unit (301) low Q secondary amounts successively, is carried out to the digital-to-analogue conversion module
Change obtains low Q of the composite construction gradually-appoximant analog-digital converter output code, and the specific steps that wherein jth time quantifies are such as
Under, j is positive integer and P+1≤j≤P+Q:
B1, first switch (S is disconnected1), third switch (S3) and the 4th switch (S4), it is closed second switch (S2) and the 5th switch
(S5), by the first serial capacitor (C1) charge be precharged to CU×(VT-VB), the second serial capacitor (C2) charge initialize to
0；
B2, second switch (S is disconnected2), third switch (S3), the 4th switch (S4) and the 5th switch (S5), it is closed first switch
(S1), by the first serial capacitor (C1) and the second serial capacitor (C2) total electrical charge be evenly distributed to the first serial capacitor (C1) and
Second serial capacitor (C2) on；
B3, the bottom crown of all quantization capacitors in the capacitor Weighting type D/A conversion unit (302) is connected into low ginseng
Examine voltage (VB), it is closed the high section reset switch (SH) and low section of reset switch (SL) by the capacitor Weighting type digital simulation
The top crown of all quantization capacitors of low section of capacitor array connects low reference voltage V in converting unit (302)B, by the high section
The top crown of all quantization capacitors of capacitor array connects high reference voltage (VT)；
Step b5 is carried out when progress step b6, j > P+1 when b4, j=P+1；
B5, since jth -1 of the composite construction gradually-appoximant analog-digital converter output code until P+1 until, according to
It is secondary to judge to be to the first serial capacitor according to s numerical value of the composite construction gradually-appoximant analog-digital converter output code
(C1) charge or discharge are carried out, wherein s is positive integer, P+1≤s≤j-1, specific judgment method are as follows:
B51, when s of the composite construction gradually-appoximant analog-digital converter output code being 0, disconnect second switch (S2), it closes
It closes third and switchs (S3), by the first serial capacitor (C1) charge be discharged to 0；When the composite construction Approach by inchmeal analog-to-digital conversion
When s of device output code are 1, disconnect third and switch (S3), it is closed second switch (S2), by the first serial capacitor (C1) electricity
Lotus charges to CU×(VT-VB)；
B52, step b2 is repeated；
B6, the high section reset switch (S is successively disconnectedH), lowest order quantization capacitor top crown switch (ST) and low section of reset switch
(SL)；
B7, first switch (S is disconnected1) and the 5th switch (S5), the 4th switch (S of closure4), by the second serial capacitor (C2) access institute
Capacitor Weighting type D/A conversion unit (302) is stated, it is high to obtain the capacitor Weighting type digital analog converter unit (302)
The output signal of position output end；
B8, by the output signal and reference signal of the high-order output end of the capacitor Weighting type digital analog converter unit (302)
It is compared, obtains the jth position output code of the composite construction gradually-appoximant analog-digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810900483.9A CN109194333B (en) | 2018-08-09 | 2018-08-09 | Composite structure successive approximation analog-to-digital converter and quantization method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810900483.9A CN109194333B (en) | 2018-08-09 | 2018-08-09 | Composite structure successive approximation analog-to-digital converter and quantization method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109194333A true CN109194333A (en) | 2019-01-11 |
| CN109194333B CN109194333B (en) | 2021-06-08 |
Family
ID=64921117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810900483.9A Active CN109194333B (en) | 2018-08-09 | 2018-08-09 | Composite structure successive approximation analog-to-digital converter and quantization method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109194333B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110311675A (en) * | 2019-06-11 | 2019-10-08 | 湖南国科微电子股份有限公司 | Successive approximation modulus conversion circuit and gradual approaching A/D converter |
| CN110504965A (en) * | 2019-07-22 | 2019-11-26 | 电子科技大学 | A kind of new structural two-step monocline analog-digital converter |
| CN111327323A (en) * | 2020-02-17 | 2020-06-23 | 西安交通大学 | Passive noise shaping oversampling successive approximation analog-to-digital converter and control method |
| CN111431535A (en) * | 2020-04-22 | 2020-07-17 | 电子科技大学 | 2b/cycle successive approximation analog-to-digital converter and quantization method thereof |
| CN111900988A (en) * | 2020-07-28 | 2020-11-06 | 电子科技大学 | Combined type third-order noise shaping successive approximation type analog-to-digital converter |
| CN112187273A (en) * | 2020-10-14 | 2021-01-05 | 电子科技大学中山学院 | Low-power-consumption successive approximation type analog-to-digital conversion circuit module |
| CN112968704A (en) * | 2021-02-03 | 2021-06-15 | 电子科技大学 | Successive approximation type analog-to-digital converter based on transient capacitance switching mode and quantization method thereof |
| CN114827505A (en) * | 2022-01-10 | 2022-07-29 | 华中科技大学 | Two-step successive approximation type analog-to-digital converter applied to image sensor |
| CN116455395A (en) * | 2023-04-19 | 2023-07-18 | 北京大学 | Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus |
| CN114827505B (en) * | 2022-01-10 | 2024-05-14 | 华中科技大学 | Two-step successive approximation analog-to-digital converter applied to image sensor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
| CN101263656A (en) * | 2005-08-12 | 2008-09-10 | 模拟装置公司 | Analog-to-digital converter |
| US7978117B2 (en) * | 2008-12-22 | 2011-07-12 | Electronics And Telecommunications Research Institute | Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same |
| US8049654B2 (en) * | 2009-02-23 | 2011-11-01 | Texas Instruments Incorporated | Digital trimming of SAR ADCs |
| CN102324934A (en) * | 2011-07-04 | 2012-01-18 | 电子科技大学 | Resistance-string multiplexing circuit structure of SAR ADC (successive approximation analog to digital converter) |
| CN106992781A (en) * | 2017-03-27 | 2017-07-28 | 电子科技大学 | The prediction quantization method of binary system charge redistribution type gradually-appoximant analog-digital converter |
| CN107888191A (en) * | 2017-12-11 | 2018-04-06 | 电子科技大学 | Gradually-appoximant analog-digital converter and its quantization method based on adaptive prediction section |
-
2018
- 2018-08-09 CN CN201810900483.9A patent/CN109194333B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
| CN101263656A (en) * | 2005-08-12 | 2008-09-10 | 模拟装置公司 | Analog-to-digital converter |
| US7978117B2 (en) * | 2008-12-22 | 2011-07-12 | Electronics And Telecommunications Research Institute | Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same |
| US8049654B2 (en) * | 2009-02-23 | 2011-11-01 | Texas Instruments Incorporated | Digital trimming of SAR ADCs |
| CN102324934A (en) * | 2011-07-04 | 2012-01-18 | 电子科技大学 | Resistance-string multiplexing circuit structure of SAR ADC (successive approximation analog to digital converter) |
| CN106992781A (en) * | 2017-03-27 | 2017-07-28 | 电子科技大学 | The prediction quantization method of binary system charge redistribution type gradually-appoximant analog-digital converter |
| CN107888191A (en) * | 2017-12-11 | 2018-04-06 | 电子科技大学 | Gradually-appoximant analog-digital converter and its quantization method based on adaptive prediction section |
Non-Patent Citations (3)
| Title |
|---|
| LING DU 等: "A 10-bit 100MS/s subrange SAR ADC with time-domain quantization", 《2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS》 * |
| 关允超 等: "一种采用电阻串复用结构的12位SAR ADC", 《微电子学》 * |
| 汪正锋 等: "一种基于电压窗口技术的超低功耗SAR ADC", 《电子学报》 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110311675A (en) * | 2019-06-11 | 2019-10-08 | 湖南国科微电子股份有限公司 | Successive approximation modulus conversion circuit and gradual approaching A/D converter |
| CN110311675B (en) * | 2019-06-11 | 2023-03-24 | 湖南国科微电子股份有限公司 | Successive approximation type analog-to-digital conversion circuit and successive approximation type analog-to-digital converter |
| CN110504965B (en) * | 2019-07-22 | 2022-05-03 | 电子科技大学 | Two-step monoclinic analog-to-digital converter with novel structure |
| CN110504965A (en) * | 2019-07-22 | 2019-11-26 | 电子科技大学 | A kind of new structural two-step monocline analog-digital converter |
| CN111327323A (en) * | 2020-02-17 | 2020-06-23 | 西安交通大学 | Passive noise shaping oversampling successive approximation analog-to-digital converter and control method |
| CN111431535A (en) * | 2020-04-22 | 2020-07-17 | 电子科技大学 | 2b/cycle successive approximation analog-to-digital converter and quantization method thereof |
| CN111431535B (en) * | 2020-04-22 | 2023-05-12 | 电子科技大学 | 2b/cycle successive approximation analog-to-digital converter and quantization method thereof |
| CN111900988A (en) * | 2020-07-28 | 2020-11-06 | 电子科技大学 | Combined type third-order noise shaping successive approximation type analog-to-digital converter |
| CN112187273A (en) * | 2020-10-14 | 2021-01-05 | 电子科技大学中山学院 | Low-power-consumption successive approximation type analog-to-digital conversion circuit module |
| CN112187273B (en) * | 2020-10-14 | 2023-06-02 | 电子科技大学中山学院 | Low-power-consumption successive approximation type analog-to-digital conversion circuit module |
| CN112968704A (en) * | 2021-02-03 | 2021-06-15 | 电子科技大学 | Successive approximation type analog-to-digital converter based on transient capacitance switching mode and quantization method thereof |
| CN114827505A (en) * | 2022-01-10 | 2022-07-29 | 华中科技大学 | Two-step successive approximation type analog-to-digital converter applied to image sensor |
| CN114827505B (en) * | 2022-01-10 | 2024-05-14 | 华中科技大学 | Two-step successive approximation analog-to-digital converter applied to image sensor |
| CN116455395A (en) * | 2023-04-19 | 2023-07-18 | 北京大学 | Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus |
| CN116455395B (en) * | 2023-04-19 | 2024-02-20 | 北京大学 | Successive approximation type analog-to-digital converter circuit, analog-to-digital converter, and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109194333B (en) | 2021-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109194333A (en) | A kind of composite construction gradually-appoximant analog-digital converter and its quantization method | |
| CN103905049B (en) | A kind of high-speed flash adds alternately comparison expression gradually-appoximant analog-digital converter | |
| CN104040898B (en) | Charge scaling digital analog converter | |
| CN106209102A (en) | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter | |
| CN107528594A (en) | Charge type streamline gradual approaching A/D converter and its control method | |
| CN102045067B (en) | Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC | |
| CN105322966B (en) | Improve the capacitors exchange and averaging method of the gradually-appoximant analog-digital converter linearity | |
| CN107493104A (en) | Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof | |
| CN108055037A (en) | A kind of gradual approaching A/D converter and its Switching method | |
| CN105049051B (en) | A kind of successive approximation modulus conversion circuit and the electronic equipment for having the circuit | |
| CN105049049A (en) | Capacitor exchange method for improving DNL (Differential Nonlinearity)/INL (Integral Nonlinearity) of successive approximation analog to digital converter | |
| CN110190854B (en) | Two-step SAR ADC-oriented shared reference voltage realization circuit and method | |
| CN107769784A (en) | A kind of over-sampling formula Pipeline SAR ADC systems | |
| CN207399180U (en) | Reference voltage adaptive circuit structure and related device | |
| CN204376879U (en) | There is the SAR ADC of mixed type DAC capacitor array structure | |
| CN108631778A (en) | Gradually-appoximant analog-digital converter and conversion method | |
| CN112332847B (en) | Two-level switching method applied to successive approximation type analog-to-digital converter | |
| CN106992785A (en) | A kind of delta modulator and its analog-digital converter | |
| CN110535466A (en) | A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus | |
| CN111431534B (en) | Analog-digital converter for quantizing multipath input | |
| CN108039890A (en) | A kind of SAR ADC circuit and D conversion method | |
| CN105375926B (en) | The capacitive gradually-appoximant analog-digital converter of pseudo-differential | |
| CN104868917B (en) | Analog-digital converter | |
| CN107835023B (en) | Successive approximation type digital-to-analog converter | |
| CN106685420A (en) | Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |