CN114827505B - Two-step successive approximation analog-to-digital converter applied to image sensor - Google Patents
Two-step successive approximation analog-to-digital converter applied to image sensor Download PDFInfo
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Abstract
A two-step successive approximation analog-to-digital converter for an image sensor, comprising: the digital-to-analog conversion device comprises a sampling module, an amplifying module, a digital-to-analog conversion module and a switch module; the sampling module is connected with the amplifying module through the switch module, and the amplifying module is connected with the digital-to-analog conversion module; the switch module has a first working state, a second working state and a third working state, and comprises a plurality of switch circuits which are selectively conducted to selectively switch the switch module to be in the first working state, the second working state or the third working state. The invention realizes a two-step analog-to-digital converter by using only a single DAC, obtains the precision of the 2N-bit analog-to-digital converter by using only the N-bit capacitive digital-to-analog converter, and obviously reduces the area and the power consumption of the analog-to-digital converter. The invention has significant advantages, especially for applications where higher accuracy is required while area is severely limited for the image sensor column level readout circuitry.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a two-step successive approximation analog-to-digital converter (SAR ADC, successive Approximation Register Analog-to-Digital Converter) applied to an image sensor.
Background
In a CMOS (Complementary Metal Oxide Semiconductor ) image sensor, the quality of the readout circuit design has a significant impact on the quality of imaging, especially the design of the analog-to-digital conversion circuit module in the readout circuit. The image sensor readout circuit is provided with a huge pixel circuit array, each pixel converts an optical signal into an Analog voltage signal to be output and needs to be subjected to subsequent Analog-to-digital conversion, and based on the compromise of speed and area, the Analog-to-digital conversion in the readout circuit is widely realized by adopting a column parallel architecture, namely each column is provided with an independent ADC (Analog-to-Digital Converter ), and the ADCs of the columns work in parallel, so that the pressure on the conversion speed of a single ADC is effectively reduced. However, under such conditions, the area, and particularly the width, of the ADC is limited by the width of a single pixel, typically from a few micrometers to tens of micrometers, with severe area limitations. In a column parallel architecture readout circuit, a SAR ADC is a widely used ADC type that has characteristics of moderate speed and accuracy, and lower power consumption.
Fig. 1 is a schematic diagram of a conventional SAR ADC. The Digital-to-Analog Converter mainly comprises a DAC (Digital-to-Analog Converter) consisting of a capacitor array, a comparator and a logic module. For this most classical single step SAR ADC, the number of unit capacitances required to achieve N-bit accuracy is 2 N, thus it can be seen that the area of the SAR ADC grows exponentially with increasing accuracy. When the accuracy of an ADC reaches more than 10 bits, the required capacitive array area for the column-parallel architecture is already unacceptable. In order to solve the problem of overlarge area of the capacitor array, a scheme of a two-step SAR ADC also appears.
Fig. 2 is a schematic diagram of a conventional two-step SAR ADC structure. The two-step SAR ADC consists of two DACs, two comparators, two logic modules and a difference amplifier, wherein the number of unit capacitors required for achieving N-bit precision isStill occupy more area and power consumption.
Therefore, in the column parallel readout circuit technology, how to further reduce the area and power consumption of the ADC is a technical problem to be solved.
In view of this, overcoming the shortcomings of the prior art products is a problem to be solved in the art.
Disclosure of Invention
The application mainly solves the technical problem of providing a two-step SAR ADC applied to an image sensor, wherein the two-step ADC is realized by only using a single DAC, and the 2N-bit ADC precision is obtained by only using N-bit CDAC (CAPACITIVE DAC, capacitive digital-to-analog converter), so that the area and the power consumption of the ADC are obviously reduced. The application has significant advantages, especially for applications where higher accuracy is required while area is severely limited for the image sensor column level readout circuitry.
In order to solve the technical problems, the application adopts a technical scheme that: there is provided a two-step SAR ADC for use in an image sensor, the two-step SAR ADC comprising: the digital-to-analog conversion device comprises a sampling module, an amplifying module, a digital-to-analog conversion module and a switch module; the sampling module is connected with the amplifying module through the switch module, and the amplifying module is connected with the digital-to-analog conversion module;
The switch module is provided with a first working state, a second working state and a third working state, and comprises a plurality of switch circuits which are selectively conducted to selectively switch the switch module to be in the first working state, the second working state or the third working state;
When the switch module is in the first working state, the sampling module is used for sending the acquired original signal to the amplifying module, the amplifying module is used for amplifying the original signal to obtain a first amplified signal, and the digital-to-analog conversion module is used for performing first successive approximation conversion on the first amplified signal;
after the first successive approximation conversion is completed, the switch module is switched to the second working state, and the amplifying module is used for carrying out second amplification on the residual difference voltage of the digital-to-analog conversion module to obtain a second amplified signal;
When the switch module is in the third working state, the digital-to-analog conversion module is used for performing successive approximation conversion on the second amplified signal for the second time.
The two-step SAR ADC further comprises a comparator and an SAR control module, wherein the input end of the comparator is connected with the output end of the digital-to-analog conversion module, and the output end of the comparator is connected with the input end of the SAR control module;
In the first successive approximation conversion process, the comparator is used for comparing the signal sizes of two input ends of the digital-to-analog conversion module, and the comparison result is output as high N bits;
In the second successive approximation conversion process, the comparator is used for comparing the signal sizes of the two input ends of the digital-to-analog conversion module, and outputting the comparison result as low N bits, so as to obtain 2N bits of AD conversion data.
The digital-to-analog conversion module comprises a first multi-path selection switch, a second multi-path selection switch, a first capacitor array and a second capacitor array, wherein the first multi-path selection switch is connected with lower polar plates of all capacitors in the first capacitor array, and upper polar plates of all capacitors in the first capacitor array are connected with a positive input end of the comparator;
the second multi-path selection switch is connected with the lower polar plate of each capacitor in the second capacitor array, and the upper polar plate of each capacitor in the second capacitor array is connected with the negative input end of the comparator;
The control end of the first multi-path selection switch and the control end of the second multi-path selection switch are respectively connected with the SAR control module;
The first capacitor array and the second capacitor array each comprise N capacitors, and capacitance values of the capacitors form an equal-ratio array, wherein N is a positive integer.
The digital-to-analog conversion module comprises a sampling module, a digital-to-analog conversion module and a digital-to-analog conversion module, wherein the switching module comprises a first switching circuit, a second switching circuit and a third switching circuit, the output end of the sampling module is connected with the input end of the amplifying module through the first switching circuit, the output end of the amplifying module is connected with the digital-to-analog conversion module through the second switching circuit, and the input end of the amplifying module is connected with the digital-to-analog conversion module through the third switching circuit.
When the first switch circuit is conducted, the second switch circuit is conducted, and the third switch circuit is disconnected, the switch module is in a first working state;
When the first switch circuit is disconnected, the second switch circuit is disconnected and the third switch circuit is conducted, the switch module is in a second working state;
When the first switch circuit is disconnected, the second switch circuit is conducted, and the third switch circuit is disconnected, the switch module is in a third working state.
The first switch circuit comprises a pair of first switches, the amplifying module comprises a differential amplifier, the negative input end of the differential amplifier is connected with one of the first switches, and the positive input end of the differential amplifier is connected with the other first switch.
Wherein the second switching circuit includes a pair of second switches, and the third switching circuit includes a pair of third switches;
The positive output end of the differential amplifier is connected with one of the second switches, and the negative output end of the differential amplifier is connected with the other second switch;
the second switch connected to the positive output end of the differential amplifier is connected with the positive input end of the differential amplifier through one of the third switches;
the second switch connected to the negative output terminal of the differential amplifier is connected to the negative input terminal of the differential amplifier through another third switch.
Wherein, the switch module includes: and the fourth switch circuit comprises a pair of fourth switches, the first end of each fourth switch is connected with the corresponding differential input signal, and the second end of each fourth switch is connected with the upper polar plate of the sampling capacitor and the first end of the corresponding first switch.
Wherein, the switch module still includes: and the fifth switching circuit comprises a pair of fifth switches, wherein one fifth switch is connected across the positive output and the negative input end of the fully-differential amplifier, and the other fifth switch is connected across the negative output and the positive input end of the fully-differential amplifier.
The beneficial effects of the application are as follows:
The invention realizes a two-step ADC by only using single digital-to-analog conversion, obtains the accuracy of the ADC with 2N bits by only using N bits CDAC, and obviously reduces the area and the power consumption of the ADC. The invention has significant advantages, especially for applications where higher accuracy is required while area is severely limited for the image sensor column level readout circuitry.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below. It is evident that the drawings described below are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a conventional SAR ADC;
FIG. 2 is a schematic diagram of a prior art two-step SAR ADC;
Fig. 3 is a schematic structural diagram of a two-step SAR ADC according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram of another two-step SAR ADC according to an embodiment of the present invention;
FIG. 5 is a timing diagram of the operation of a two-step SAR ADC according to an embodiment of the present invention;
FIG. 6 is a simulated waveform diagram I of a two-step SAR ADC according to an embodiment of the present invention;
fig. 7 is a simulation waveform diagram two of a two-step SAR ADC according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
It should be noted that, because the method of the embodiment of the present application is executed in the electronic device, the processing objects of each electronic device exist in the form of data or information, for example, time, which is substantially time information, it can be understood that in the subsequent embodiment, if the size, the number, the position, etc. are all corresponding data, so that the electronic device can process the data, which is not described herein in detail.
Example 1:
In order to solve the foregoing problems, referring to fig. 3, the present embodiment provides a two-step SAR ADC for an image sensor, which includes: the digital-to-analog conversion device comprises a sampling module 1, an amplifying module 2, a digital-to-analog conversion module 3 and a switch module; the sampling module 1 is connected with the amplifying module 2 through the switch module, and the amplifying module 2 is connected with the digital-to-analog conversion module 3.
In this embodiment, the switch module has a first working state, a second working state and a third working state, and the switch module includes a plurality of switch circuits, and the switch circuits are selectively turned on to selectively switch the switch module to be in the first working state, the second working state or the third working state; when the switch module is in a first working state, the sampling module 1 is used for sending the acquired original signal to the amplifying module 2, the amplifying module 2 is used for amplifying the original signal to obtain a first amplified signal, and the digital-to-analog conversion module 3 is used for performing first successive approximation conversion on the first amplified signal.
After the first successive approximation conversion is completed, the switch module is switched to a second working state, and the amplifying module 2 is used for carrying out second amplification on the residual difference voltage of the digital-to-analog conversion module 3 to obtain a second amplified signal; when the switch module is in the third working state, the digital-to-analog conversion module 3 is used for performing successive approximation conversion on the second amplified signal for the second time.
Further, the two-step successive approximation type analog-to-digital converter further comprises a comparator 5 and an SAR control module 6, wherein the input end of the comparator 5 is connected with the output end of the digital-to-analog conversion module 3, and the output end of the comparator 5 is connected with the input end of the SAR control module 6; the SAR control module 6 controls the conversion of the digital-to-analog conversion module 3 according to the comparison result of the comparator 5, thereby realizing a successive approximation conversion function.
In the first successive approximation conversion process, the comparator 5 is used for comparing the signal sizes of the two input ends of the digital-to-analog conversion module 3, and the comparison result is output as high N bits; in the second successive approximation conversion process, the comparator 5 is configured to compare the signal sizes at two ends of the digital-to-analog conversion module 3, and output the comparison result as a low N bit, thereby obtaining 2N bit AD conversion data.
In this embodiment, only N-bit CDAC is used to obtain 2N-bit ADC accuracy, which significantly reduces the area and power consumption of the ADC. Particularly for applications requiring higher accuracy and having strictly limited area for the image sensor column level readout circuitry.
Specifically, referring to fig. 4, the digital-to-analog conversion module 3 includes a first multiplexing switch 31, a second multiplexing switch 32, a first capacitor array and a second circuit array, where the first multiplexing switch 31 is connected to a lower plate of each capacitor in the first capacitor array, and an upper plate of each capacitor in the first capacitor array is connected to a positive input end of the comparator 5; the second multi-path selection switch 32 is connected with the lower polar plate of each capacitor in the second capacitor array, and the upper polar plate of each capacitor in the first capacitor array is connected with the negative input end of the comparator 5; the control end of the first multiplexing switch 31 and the control end of the second multiplexing switch 32 are connected with the SAR control module 6, respectively.
The first capacitor array and the second capacitor array each comprise N capacitors, the N capacitors form an equal ratio array, and N is a positive integer.
In an alternative embodiment, the size of each capacitor Ci-1 is 2 i-1 ×cu, where N is a positive integer, i is a positive integer between [1, N ], and Cu is a unit capacitor.
In an actual application scenario, a capacitor C0 is reserved in the first capacitor array and the second capacitor array for standby.
In an alternative embodiment, the switching module includes a first switching circuit 41, a second switching circuit 42 and a third switching circuit 43, the output end of the sampling module 1 is connected with the input end of the amplifying module 2 through the first switching circuit 41, the output end of the amplifying module 2 is connected with the digital-to-analog conversion module 3 through the second switching circuit 42, and the input end of the amplifying module 2 is also connected with the digital-to-analog conversion module 3 through the third switching circuit 43.
In connection with the foregoing description, the switch module is in the first operating state when the first switch circuit 41 is on, the second switch circuit 42 is on, and the third switch circuit 43 is off; when the first switch circuit 41 is turned off, the second switch circuit 42 is turned off, and the third switch circuit 43 is turned on, the switch module is in the second working state; when the first switching circuit 41 is turned off, the second switching circuit 42 is turned on, and the third switching circuit 43 is turned off, the switching module is in the third operating state.
In an alternative embodiment, referring to fig. 4, the first switch circuit 41 includes a pair of first switches S1, and the amplifying module 2 includes a differential amplifier, a negative input terminal of the differential amplifier is connected to one of the first switches S1, and a positive input terminal of the differential amplifier is connected to the other first switch S1.
The second switch circuit 42 includes a pair of second switches Ssmp, and the third switch circuit 43 includes a pair of third switches S3; the positive output end of the differential amplifier is connected with one of the second switches Ssmp, and the negative output end of the differential amplifier is connected with the other second switch Ssmp; the second switch Ssmp connected to the positive output end of the differential amplifier is connected with the positive input end of the differential amplifier through one of the third switches S3; the second switch Ssmp connected to the negative output of the differential amplifier is connected to the negative input of the differential amplifier through a further third switch S3.
Further, the switch module includes: the fourth switch circuit 44, the fourth switch circuit 44 includes a pair of fourth switches S4, and a first end of each fourth switch S4 is connected to the corresponding differential input signal, and a second end is connected to the upper plate of the sampling capacitor Csig and the first end of the corresponding first switch S1.
The switch module further includes: the fifth switch circuit 45, the fifth switch circuit 45 includes a pair of fifth switches Srst, wherein one of the fifth switches Srst is connected across the positive output and the negative input of the fully differential amplifier, and the other of the fifth switches Srst is connected across the negative output and the positive input of the fully differential amplifier.
In the embodiment, a single digital-to-analog conversion module, a single amplifier and a single SAR control module are used for realizing a two-step ADC, the number of devices is reduced, and the accuracy of the 2N-bit ADC is obtained by using only N-bit CDAC, so that the area and the power consumption of the ADC are obviously reduced. Particularly for applications requiring higher accuracy and having strictly limited area for the image sensor column level readout circuitry.
For the function of each module, please refer to the following description for the operation of the two-step SAR ADC.
Example 2:
Referring to fig. 4, the following details of each functional module are described in order from left to right in conjunction with the flow direction of signals:
The fourth switching circuit 44 mainly includes five ports, specifically a pair of differential input ports, a pair of differential output ports, and a control port PH1; the differential input ports are used for receiving original signals in a differential mode, the differential output ports are used for inputting the original signals to the sampling module 1, and the on-off of the fourth switches S4 are controlled through the control signals PH1 so as to switch the working states of the switching module.
The sampling module 1 is mainly used for sampling and holding an original differential signal needing analog-to-digital conversion, and the module is provided with four main ports, wherein a pair of differential input ports are used for inputting the original signal; a pair of differential output ports is connected to a subsequent amplification module 2. The switching module comprises a pair of sampling capacitors by means of which the original signal is held in the sampling module 1.
The first switch circuit 41 mainly includes five ports, specifically a pair of differential input ports, a pair of differential output ports, and a control port PH2; the differential input ports are used for receiving original signals in a differential mode, the differential output ports are used for inputting the original signals to the amplifying module 2, and the on-off of the first switches S1 are controlled through the control signals PH2 so as to switch the working states of the switching module.
The first end of the fourth switch S4 is connected with the differential input signal, the second end of the fourth switch S4 is connected with the upper pole plate of the sampling capacitor Csig and the first end of the first switch S1, the first end of the first switch S1 is connected with the second end of the fourth switch S4 and the upper pole plate of the sampling capacitor Csig, and the upper pole plate of the sampling capacitor Csig is connected with the second end of the fourth switch S4 and the first end of the first switch S1. PH1 controls the break-make of fourth switch S4, PH2 controls the break-make of first switch S1, when fourth switch S4 switches on, sample and keep the input signal at sampling capacitor, when first switch S1 switches on, input the signal that sampling capacitor kept to amplifying module 2.
The amplifying module 2 is provided with four main ports, wherein two differential input ports are connected with differential output ports of the front-stage sampling module 1; the two differential output ports are connected with the input port of the post-stage digital-to-analog conversion module 3; the amplifying module 2 comprises a fully differential operational amplifier and a set of two capacitors Cf. The differential input end of the amplifier is the input end of the module, and the differential output end is connected with the first end of the second switch Ssmp and the pair of capacitors Cf.
The fifth switch circuit 45 includes a pair of fifth switches Srst, each of which is connected across the positive output and the negative input and the negative output and the positive input of the fully differential amplifier.
The amplifying module 2 is configured to amplify the original signal to obtain a first amplified signal, and further configured to amplify the residual difference voltage of the digital-to-analog conversion module 3 for a second time to obtain a second amplified signal.
The second switch circuit 42 mainly includes five ports, specifically a pair of differential input ports, a pair of differential output ports, and a control port SMP; the pair of differential input ports are used for receiving original signals, the pair of differential output ports are used for inputting the original signals to the amplifying module 2, and the on-off of the pair of second switches Ssmp is controlled through the control signal SMP so as to switch the working state of the switching module.
The third switch circuit 43 mainly includes five ports, specifically a pair of differential input ports, a pair of differential output ports, and a control port PH3; the pair of differential input ports are used for receiving residual difference voltage of the digital-to-analog conversion module 3, the pair of differential output ports are used for inputting the residual difference voltage to the amplifying module 2, and the on-off of the pair of third switches S3 is controlled through the control signal PH3 so as to switch the working state of the switch module.
The digital-to-analog conversion module 3 realizes the successive approximation conversion function based on the charge redistribution principle, and in the ADC of the present invention, this digital-to-analog conversion can multiplex coarse conversion (i.e., first successive approximation conversion) and fine conversion (i.e., second successive approximation conversion) respectively, thereby realizing multi-bit conversion using a less-bit DAC. The main port comprises two differential input ports which are connected with the front-stage amplifying circuit; the two differential output ports are connected with the comparator 5; the three voltage input ports VCM, VP and VN are selectively connected with the capacitance lower plate through a multi-way selection switch, wherein VCM is a common mode voltage, VP is larger than VCM, and VN is smaller than VCM; the two multiplexing control ports are connected with the post-stage SAR control module 6. The module mainly comprises a differential N-bit CDAC binary capacitor array, wherein the sizes of C0-CN-1 and C0 are unit capacitors Cu, C1 is 2 1 times Cu, and the size of CN-1 is 2 N-1 times Cu, the upper polar plate of the capacitor is directly connected with the input port and the output port of the DAC, and the lower polar plate is connected with a multi-way selection switch; the output ends of the multiple-way selector switch are respectively connected to the lower polar plates of the capacitors on the positive side and the negative side, and the input ends are connected with the voltage input ports VCM, VP and VN.
The comparator 5 mainly compares the differential inputs and outputs a comparison result, and outputs 1 when the input positive terminal voltage is greater than the input negative terminal voltage, and otherwise outputs 0. The main ports are a pair of differential input ports and an output port. The differential input port is connected with the front-stage DAC, and the output port is connected with SAR control logic.
The SAR control module 6 realizes a successive approximation function by timing control, and outputs converted data DOUT. The main port comprises an input port connected with the output of the comparator 5; an output port DOUT for outputting data; the two multiplexing control ports are connected with multiplexing switches in the digital-to-analog conversion module 3.
Fig. 5 shows a timing control method according to an embodiment of the present invention, by which the conversion function of the ADC can be implemented. Fig. 4 shows a complete two-step ADC conversion cycle, which is mainly divided into four phases, namely an input sampling phase, a coarse conversion phase, a difference sampling phase and a fine conversion phase.
In the input sampling phase, the control signals PH1 and RST are first set high, the rest signals are set low, and when the signals are set high, the corresponding switches are turned on, and otherwise, the corresponding switches are turned off. At the moment, an external input signal is sampled into a sampling capacitor in the sampling module 1, and meanwhile, the input and output short circuits of the amplifier are used for resetting; secondly PH1 and RST are low, PH2 and SMP are high, at the moment, the signal in Csig is amplified by the amplifier, the amplification factor is Csig/Cf, and Csig and Cf are equal to unit capacitance Cu, namely, at the moment, the amplifier plays a role of unit gain buffering. The amplified signal is sampled by a capacitor array in the DAC.
The coarse transition phase follows, where PH2 and SMP are set low, RST is set high, DAC sampling is complete, and the amplifier is reset again. At this point the input signal is already stored in the capacitive array of the DAC and the system begins the successive comparison operation. Firstly, the comparator 5 compares the signal sizes at two ends of the DAC, the result is positive output 1, the result is negative output 0, meanwhile, the SAR control module 6 stores the output of the current bit and controls the multi-path selection switch array, and the voltage of the lower polar plate of the DAC capacitor is selectively changed, so that the voltage of the upper polar plate of the DAC is influenced to realize binary successive approximation. And next comparison is carried out, the output of the high N bits is obtained and stored after the N times of circulation are completed, and the voltage of the upper polar plate of the DAC capacitor is the residual difference voltage after the N times of successive approximation.
Then, a difference sampling stage is performed, in which RST is first set low and PH3 is set high, at which time the difference voltage in the DAC is amplified by (c0+c0+c1+ … +cn-1)/Cf, and c0=cu, CN-1= N-1 ×cu, so c0+c0+c1+ … +cn-1= N ×cu, cf=cu, and the amplification factor is 2 N, so that the difference can be amplified to 2 N times. Then PH3 is set low, SMP is set high, and the amplified result is resampled to the capacitive array.
And finally, in the fine switching stage, RST is set high, SMP is set low, DAC sampling is finished, and the amplifier is reset again. The next working condition is similar to the coarse conversion, successive approximation comparison is also carried out for the same time, and the output of the low N bits is obtained and stored after N times of circulation. At this time, 2N-bit AD conversion data has been obtained.
Fig. 6 and 7 show the waveforms of the results of the simulation performed based on this embodiment. Taking N as 6, other specific parameters are power supply voltage 1.8V, common mode voltage 0.9V and reference voltage 1V. The waveforms of the control signals PH1, PH2, RST, SMP, PH in fig. 6 correspond to fig. 5. Waveforms VP and VN are voltages on the upper plates of the DAC capacitors, and in the conversion phase, VP and VN voltage changes conform to a successive approximation comparison process, corresponding to the thickness conversion phase in fig. 5. Fig. 7 shows binary data output during conversion, and it can be seen that 12-bit conversion accuracy is achieved by twice conversion of the thickness.
In general, the invention realizes a two-step ADC with only a single DAC, and only N bits of CDAC are used to obtain 2N bits of ADC precision, thereby remarkably reducing the area and power consumption of the ADC. The invention has significant advantages, especially for applications where higher accuracy is required while area is severely limited for the image sensor column level readout circuitry.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (10)
1. A two-step successive approximation analog-to-digital converter for an image sensor, comprising: the digital-to-analog conversion device comprises a sampling module, an amplifying module, a digital-to-analog conversion module and a switch module;
The sampling module is connected with the amplifying module through the switch module, and the amplifying module is connected with the digital-to-analog conversion module;
The switch module is provided with a first working state, a second working state and a third working state, and comprises a plurality of switch circuits which are selectively conducted to selectively switch the switch module to be in the first working state, the second working state or the third working state;
When the switch module is in the first working state, the sampling module is used for sending the acquired original signal to the amplifying module, the amplifying module is used for amplifying the original signal to obtain a first amplified signal, and the digital-to-analog conversion module is used for performing first successive approximation conversion on the first amplified signal;
after the first successive approximation conversion is completed, the switch module is switched to the second working state, and the amplifying module is used for carrying out second amplification on the residual difference voltage of the digital-to-analog conversion module to obtain a second amplified signal;
When the switch module is in the third working state, the digital-to-analog conversion module is used for performing successive approximation conversion on the second amplified signal for the second time.
2. The two-step successive approximation analog-to-digital converter according to claim 1, further comprising a comparator and a successive approximation control module, wherein an input of the comparator is connected to an output of the digital-to-analog conversion module, and an output of the comparator is connected to an input of the successive approximation control module;
In the first successive approximation conversion process, the comparator is used for comparing the signal sizes of two input ends of the digital-to-analog conversion module, and the comparison result is output as high N bits;
in the second successive approximation conversion process, the comparator is used for comparing the signal sizes of two input ends of the digital-to-analog conversion module, and outputting the comparison result as low N bits so as to obtain 2N bits of AD conversion data; wherein N is a positive integer.
3. The two-step successive approximation analog-to-digital converter of claim 2, wherein the digital-to-analog conversion module comprises a first multiplexing switch, a second multiplexing switch, a first capacitor array and a second capacitor array, wherein the first multiplexing switch is connected with a lower plate of each capacitor in the first capacitor array, and an upper plate of each capacitor in the first capacitor array is connected with a positive input terminal of the comparator;
the second multi-path selection switch is connected with the lower polar plate of each capacitor in the second capacitor array, and the upper polar plate of each capacitor in the first capacitor array is connected with the negative input end of the comparator;
the control end of the first multi-path selection switch and the control end of the second multi-path selection switch are respectively connected with the successive approximation type control module.
4. The two-step successive approximation analog-to-digital converter according to claim 3, wherein the first capacitor array and the second capacitor array each comprise N capacitors, the capacitance values of each capacitor forming an equal-ratio array, wherein N is a positive integer.
5. The two-step successive approximation analog-to-digital converter according to any one of claims 1to 4, wherein the switching module comprises a first switching circuit, a second switching circuit and a third switching circuit, the output end of the sampling module is connected with the input end of the amplifying module through the first switching circuit, the output end of the amplifying module is connected with the digital-to-analog conversion module through the second switching circuit, and the input end of the amplifying module is further connected with the digital-to-analog conversion module through the third switching circuit.
6. The two-step successive approximation analog-to-digital converter of claim 5, wherein the switch module is in a first operating state when the first switch circuit is on, the second switch circuit is on, and the third switch circuit is off;
When the first switch circuit is disconnected, the second switch circuit is disconnected and the third switch circuit is conducted, the switch module is in a second working state;
When the first switch circuit is disconnected, the second switch circuit is conducted, and the third switch circuit is disconnected, the switch module is in a third working state.
7. The two-step successive approximation analog-to-digital converter according to claim 6, wherein the first switching circuit comprises a pair of first switches, the amplifying module comprises a differential amplifier, a negative input of the differential amplifier is connected to one of the first switches, and a positive input of the differential amplifier is connected to the other first switch.
8. The two-step successive approximation analog-to-digital converter according to claim 7, wherein the second switching circuit comprises a pair of second switches, and the third switching circuit comprises a pair of third switches;
The positive output end of the differential amplifier is connected with one of the second switches, and the negative output end of the differential amplifier is connected with the other second switch;
the second switch connected to the positive output end of the differential amplifier is connected with the positive input end of the differential amplifier through one of the third switches;
the second switch connected to the negative output terminal of the differential amplifier is connected to the negative input terminal of the differential amplifier through another third switch.
9. The two-step successive approximation analog-to-digital converter according to claim 6, wherein the switching module comprises: and the fourth switch circuit comprises a pair of fourth switches, the first end of each fourth switch is connected with the corresponding differential input signal, and the second end of each fourth switch is connected with the upper polar plate of the sampling capacitor and the first end of the corresponding first switch.
10. The two-step successive approximation analog-to-digital converter according to claim 7, wherein the switching module further comprises: and the fifth switching circuit comprises a pair of fifth switches, wherein one fifth switch is connected across the positive output and the negative input end of the differential amplifier, and the other fifth switch is connected across the negative output and the positive input end of the differential amplifier.
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