KR20130064971A - Analog-digital converter for high resolution image sensor - Google Patents

Abstract

PURPOSE: A high definition image sensor using an analog to digital converter is provided to implement a normal mode of reading a signal sequentially from each column from pixels of the image sensor and a binning mode of reading signals for a number of adjacent pixels of two columns through a charge averaging method. CONSTITUTION: A column driver includes more than one column analog to digital converters(ADC)(200) receiving a signal from two column lines included in a pixel array. The column ADC includes a sigma-delta ADC(201) and a successive approximation register ADC(202). The sigma-delta ADC receives an output voltage of the pixel from at least two column lines of the pixel array, and then performs analog to digital conversion of the output voltage. The successive approximation register ADC receives an output value of the sigma-delta ADC, and then performs the analog to digital conversion of the output value.

Description

Analog-Digital Converter for High Resolution Image Sensor

The present invention relates to an analog-to-digital converter for a high-resolution image sensor, and more particularly, to provide an analog-to-digital converter for deriving a high-resolution image image by using a low power high resolution function.

Conventional film-type analog image detection apparatus has generally taken the image manually using an optical system technology such as a lens or film.

Technology for image detection devices has been gradually developed, such as a charge coupled device (CCD) or a CMOS image sensor (CIS) has emerged a digital image detection device that can be easily converted to digital data and stored in a storage device. The digital image detection device can store a large amount of video and video and transmit it to another device, and it is possible to process the captured image using digital signal processing to a high level of informational data.

Furthermore, image sensors used in image detection devices are widely used in medical and scientific fields such as advanced image detection devices such as digital single lens reflex (DSLR) or broadcast cameras, and X-ray detectors. Accordingly, there is a demand for an image sensor capable of outputting high resolution image data of 14-bit or more while satisfying a high resolution of about Mega pixels.

Therefore, by using a high-resolution high-resolution image sensor, charge averaged signals for a plurality of neighboring pixels of a plurality of columns constituting an image while capturing a video at 30 frames per second to obtain high resolution image data. Research on analog-to-digital converters (ADCs) that support a binning mode that reads on an average basis is continuing.

Currently used ADCs serve a purpose and function depending on their type.

Single-slope ADCs are mainly used in image sensors because of their excellent monotonicity, but they require high-speed clocks to operate with 14-bit or higher resolution ADCs. Inappropriate.

Cyclic ADCs and Successive Approximation ADCs (SAR ADCs) require as many bits of clock cycles as high resolution ADCs, making them suitable for high-resolution, high-resolution image sensors.

However, the Cyclic ADC requires an amplifier having a high voltage gain to reduce the error due to the finite voltage gain and a large capacitor to reduce the sampling error. Therefore, the power consumption increases rapidly as the resolution is increased. In addition, although the SAR ADC consumes very little power, the size of the capacitor constituting the digital-to-analog converter (DAC) in the ADC increases, so that the overall area increases rapidly as the resolution of the ADC increases.

As another ADC, the Sigma-delta ADC can reduce the size of the sampling capacitor and the voltage gain of the op amp by the oversampling effect. However, as the resolution of the ADC increases, the bandwidth increases, making it difficult to reduce power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to charge signals for a normal mode and a plurality of neighboring pixels, which sequentially read signals from each pixel from pixels of an image sensor. This paper proposes an ADC that supports binning mode that reads in an averaged manner and removes noise generated when a signal is read.

Another object of the present invention is to propose a structure and a driving method of an ADC to which the digital correlated double sample (CDS) technology, which does not increase the speed of the ADC even in the binning mode, is applicable.

It is still another object of the present invention to propose a structure and a driving method of an ADC which reduces the size of a sampling capacitor and enables low power in a high resolution ADC.

An analog to digital converter for a high-resolution image sensor according to an embodiment of the present invention for solving the above problems is to select a pixel array including a plurality of pixels formed in the form of a two-dimensional array, the row line constituting the pixel array An image sensor comprising a scan driver and a column driver that reads a photoelectric conversion signal from pixels of a row line selected by the scan driver, wherein the column driver is configured to output a signal from at least two column lines included in the pixel array. And one or more column-to-analog analog-to-digital converters (ADCs) receiving the inputs, wherein the column ADCs perform S / Ama-A to receive output voltages of pixels from at least two column lines of the pixel array. Input the output values of the delta ADC and the Sigma-delta ADC as input signals Oh and a SAR ADC (Successive Approximation ADC) for performing A / D conversion.

The pixel array according to an embodiment of the present invention may be arranged such that pixels of an odd row line and pixels of an even row line have different column lines.

The column driver according to an embodiment of the present invention includes a column ADC array including one or more of the column ADCs and converting an output voltage of a pixel into a digital signal and outputting the digital signal; A column digital processing unit for correcting an output result generated by the column ADC in the column ADC array; And an SRAM array storing an output result generated by the column ADC array.

An input terminal of the column ADC may be connected to at least two column output lines for outputting photoelectric conversion signals corresponding to pixels of an odd row line and an even row line for each column of the pixel array.

The column ADC may include a circuit including at least two current sources, at least two sampling capacitors, and a plurality of switches for each channel unit of the column driver, and sequentially receive signals from the two column output lines through the circuit. Can be input.

Meanwhile, the input terminal of the column ADC includes a switch connected between the two column output lines, and the switch may be turned on in a normal mode and turned off in a binning mode. In this case, the column ADC may simultaneously receive an output signal from four adjacent pixels among the plurality of pixels constituting the pixel array using the switch and the adjacent channel ADC.

The Sigma-delta ADC according to an embodiment of the present invention may include a feedback capacitor, a plurality of sampling capacitors, a circuit including a plurality of switches and integrators connected between the capacitors.

In this case, the Sigma-delta ADC is to repeat the process of sampling and holding the signal input to the first clock, A / D conversion of the signal input from the second clock to output as a digital signal, the last clock The output voltage may be sampled and output as a digital signal such that the output voltage of the integrator is half of the input voltage range input to the SAR ADC.

The integrator according to an embodiment of the present invention includes a two-stage amplifier of a first amplifier stage and a second amplifier stage, and applies current only to the first amplifier stage while initializing all voltage nodes of the integrator to the same voltage. The current path of the two amplifier stages can be shorted.

Meanwhile, the Sigma-delta ADC reduces the power consumption of the integrator to a predetermined level while the pixel signal voltage is input from the pixel array, and A / D converts the pixel signal voltage to a point where the pixel reset voltage is input. The integrator may store and maintain the integrator and perform A / D conversion by connecting opposite ends of the sampling capacitor with respect to the input pixel reset voltage.

In addition, the Sigma-delta ADC sets the feedback capacitor to twice the size of the sampling capacitor to perform A / D conversion on the pixel signal voltage, and outputs the integrator to the SAR ADC. The output voltage may be sampled to be half of the input voltage range and output as a digital signal.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the present invention by those skilled in the art. And can be understood and understood.

According to the present invention, a normal mode in which signals are sequentially read in each column from pixels of an image sensor, and a binning mode in which signals for a plurality of neighboring pixels of two columns are read in a charge average method. Can be implemented.

In addition, according to the present invention, KT / C noise may be reduced while reducing the size of the sampling capacitor while implementing an ADC that generates a high resolution image.

In addition, according to the present invention, by implementing the column ADC of the column driver by connecting the Sigma-delta ADC and the SAR ADC, it is possible to use a partially switched operational amplifier technology, thereby minimizing power consumption.

In addition, according to the present invention, it is possible to remove the noise of the pixel signal by the analog CDS method using only the ADC circuit, without using the analog CDS amplifier, and can also be used as the digital CDS method by adding a digital processing block.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
1 is an overall configuration diagram showing an example of an image sensor according to an embodiment of the present invention.
2 is a block diagram illustrating an example of a configuration of a column driver of an image sensor according to an exemplary embodiment.
3 is a diagram illustrating an example of a connection state between a column ADC array and a pixel array of a column driver according to an exemplary embodiment of the present invention.
4 is a diagram illustrating an example of a unit channel of a column driver according to an embodiment of the present invention.
5 is a diagram illustrating an example of a circuit diagram of a Sigma-delta ADC according to an embodiment of the present invention.
6 is a diagram illustrating an example of an operating state of a circuit according to time of a Sigma-delta ADC according to an embodiment of the present invention.
7 is a diagram illustrating an example of a circuit diagram of a SAR ADC according to an embodiment of the present invention.
8 is a diagram illustrating an example of a block diagram of a column ADC input terminal according to an embodiment of the present invention.
9 is a flowchart illustrating an example of a process of driving the pixel array and the ADC according to an embodiment of the present invention over time.
10 is a flowchart illustrating another example of a process in which a pixel array and an ADC are driven over time according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating an example of an integrator circuit diagram in which an associative amplifier of a switch is applied to reduce power consumption in a Sigma-delta ADC according to an embodiment of the present invention.
12 is a diagram illustrating an example of an output result for each gray level of sub-ADCs constituting a column ADC according to an exemplary embodiment of the present invention.
FIG. 13 is a diagram illustrating an example of a technique for correcting a comparator offset in a Sigma-delta ADC according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Terms such as 'first' and 'second' may be used to describe various components, but the components are not limited by the terms, and the terms are only used to distinguish one component from another component. Used.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description, together with the accompanying drawings, is intended to illustrate exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced. The following detailed description includes specific details in order to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without these specific details.

The present invention relates to an analog-to-digital converter for a high-resolution image sensor, and more particularly, to provide an analog-to-digital converter for deriving a high-resolution image image by using a low power high resolution function.

1 is an overall configuration diagram showing an example of an image sensor according to an embodiment of the present invention.

Referring to FIG. 1, the image sensor 100 includes a pixel array 110, a scan driver 120, and a column driver 130.

Photoelectric conversion pixels are formed in the pixel array 110 in the form of a two-dimensional array, and the scan driver 120 and the column driver 130 operate as driving circuits for reading the photoelectric conversion signals detected by the pixel array 110. do.

The scan driver 120 sequentially selects row lines in a row direction to activate pixels formed in the selected row line to sense light incident from the outside.

The column driver 130 reads the photoelectric conversion signal in each column from the pixels of the corresponding row line selected by the scan driver 120. Here, each pixel of the pixel array 110 outputting the photoelectric conversion signal may be photoelectrically converted to incident light to generate an electrical signal corresponding to the incident light.

In particular, the scan driver 120 and the column driver 130 operate slightly differently according to a normal mode or a binning mode.

For example, in the normal mode, as the scan driver 120 sequentially selects the row lines one by one, the odd CDS circuit of the odd column and the even CDS circuit of the even column are each of the corresponding column. The photoelectric conversion signals from the pixels of the low line can be sequentially output. On the other hand, in the binning mode, as the scan driver 120 sequentially selects a plurality of row lines (for example, two row lines), the even CDS circuit stops operation, and the odd CDS circuit of the odd CDS circuit is selected. Photoelectric conversion signals corresponding to the pixels of the plurality of row lines (for example, two row lines) and the plurality of row lines of the adjacent even columns (for example, through a multiplexer on the even column side). For example, the photoelectric conversion signals corresponding to the pixels of the 2 row lines may be summed by the charge sum method and sequentially output.

2 is a block diagram illustrating an example of a configuration of a column driver of an image sensor according to an exemplary embodiment.

Referring to FIG. 2, the column driver 130 may include a column ADC array 131, a column digital processing unit 132, and a static random access memory (SRAM) array 133. Can be.

The column ADC array 131 includes an ADC for each column from pixels of the row line selected by the scan driver 120 described above with reference to FIG. 1 to convert the output voltage of each pixel into digital data.

The column digital processing unit 132 performs the function of correcting the offset of each channel ADC when the analog CDS method is used in the ADC, and calculates the difference in the output result of the ADC when the digital CDS method is used in the ADC. .

The SRAM array 133 performs a memory function. Specifically, the SRAM array 133 stores the corrected digital data output value of the ADC through interworking of the column ADC array 131 and the column digital processing unit 133.

3 is a diagram illustrating an example of a connection state between a column ADC array and a pixel array of a column driver according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the pixel array 110 includes k odd columns and k even columns, and the column ADC array 131 also includes k column ADCs. In order to support the binning mode, pixels of the pixel array 110 are connected to column lines having odd and even row lines different from each other. The total column lines of the pixel array 110 are connected in pairs to each column ADC constituting the column ADC array 131.

4 is a diagram illustrating an example of a unit channel of a column driver according to an embodiment of the present invention. Specifically, FIG. 3 illustrates a unit channel of the column driver connected to the j-th column line of the pixel array 110 according to the exemplary embodiment of the present invention.

Referring to FIG. 4, a unit channel of a column driver according to an exemplary embodiment of the present invention includes a unit column ADC 200, a column digital processing unit 210, and an SRAM 220. As an example of the column ADC 200, the (m + n-1) -bit column ADC 200 may be configured as an m-bit primary Sigma-delta ADC 201 and an n-bit SAR ADC 202.

The use of a Sigma-delta ADC enables the analog CDS function without the use of a separate CDS amplifier, which reduces the area and power consumption. In addition, in order to obtain high resolution of 14-bit or more with respect to the actual output signal of the pixel, the size of the sampling capacitor requires a few picofarads (pF) or more considering the KT / C noise. Since the driving capability must be improved, power consumption is increased and the required area of the capacitor is also increased. In addition, the use of a Sigma-delta ADC to sample the pixel output reduces the size of the sampling capacitor.

When the SAR ADC is used together with the Sigma delta ADC, the over-sampling rate that is increased by using the second or more Sigma-delta ADC to have a resolution of 14-bit or more when using only the Sigma-delta ADC alone. sampling rate) and power consumption can be prevented. That is, in the present invention, as shown in FIG. 4, the output value of the primary Sigma-delta ADC 201 is input to the SAR ADC 202 so that the lower bit is decomposed, thereby minimizing power consumption.

The signal input to the input terminal of the Sigma-delta ADC 201 modulator is transmitted from a column line connected to one or more pixels located nearby, and may be simultaneously or sequentially input.

For example, when the odd and even row lines of the pixel array of the image sensor are connected to the m-bit Sigma-delta ADC 201 in the column ADC 200, the m-bit Sigma-delta ADC 201 is a pixel. The output voltages of pixels positioned in odd row lines and even row lines of the j th column may be simultaneously input from two column lines of the array. After the A / D conversion of the output voltage of the pixel input from the Sigma-delta ADC 201 is completed, the final output voltage MOD_AOUT of the modulator in the Sigma-delta ADC 201 is n-bit SAR ADC ( 202). The digital m-bit converted by the m-bit Sigma-delta ADC 201 is transferred to the column digital processing unit 210.

At this time, the input range of the SAR ADC 202 is Sigma-delta ADC 201 in order to correct the error of the ADC caused by the offset of the modulator of the Sigma-delta ADC 201 and the comparator in the SAR ADC 202 The column ADC 200 may be implemented to be twice the output range of.

Next, the n-bit SAR ADC 202 receives the output voltage of the modulator in the m-bit Sigma-delta ADC 201 as an input signal, performs n-bit A / D conversion, and converts the converted digital n-bit. Is passed to the column digital processing unit 210.

The column digital processing unit 210 receives the output of the A / D conversion from the Sigma-delta ADC 201 and the SAR ADC 202, and outputs the final ADC based on the output of the two ADCs (m + n-1). The bit is output and stored in the SRAM 220.

If the Sigma-delta ADC 201 and the SAR ADC 202 are used together to convert the lower bits as in the present invention, the pixel output voltage can be set during the operation of the SAR ADC 202. Therefore, when only the existing Sigma-delta ADC is used, the A / D conversion time can be increased compared to the method of using the A / D conversion time for the remaining time except the settling time of the pixel's output voltage.

In addition, the A / D conversion method using the Sigma-delta ADC 201 and the SAR ADC 202 together reduces the operation speed of the sub-ADCs (here, Sigma-delta ADC and SAR ADC) constituting the column ADC. Therefore, the amount of power consumption can also be reduced. In addition, by partially reducing the power consumption of the integrator in the Sigma-delta ADC 201 modulator while the SAR ADC 202 is operating, the power consumption can be reduced using a partially switched op-amp technique. Can be further reduced.

Meanwhile, the unit channel of the column driver illustrated in FIG. 4 is an example for describing a method of using a Sigma-delta ADC and a SAR ADC together, but is not necessarily limited thereto. An analog CDS or digital CDS scheme may be applied through a modification of the unit column ADC configuration of the column driver illustrated in FIG. 4.

For example, a method of accumulating the pixel reset output voltage value and the signal output voltage value to the modulator of the Sigma-delta ADC 201 and transferring the value finally outputted from the modulator to the input value of the SAR ADC 202. By using this, an analog CDS scheme can be implemented. The analog CDS scheme according to the present invention can reduce the power consumption because the function of the CDS amplifier is included in the modulation unit of the Sigma-delta ADC 201.

As another example, the digital CDS scheme may be implemented by adding a digital processing block that decomposes the pixel reset output voltage and the signal output voltage using an ADC and calculates the difference between the result values in the column driver unit channel shown in FIG. 4. . In this case, the final output value of the ADC is expressed as (m + n) -bit so that even if the digital code is out of the (m + n-1) -bit range, digital processing can be used for easier error correction.

5 is a view showing an example of a circuit diagram of a Sigma-delta ADC according to an embodiment of the present invention, Figure 6 is a view of the operating state of the circuit over time of the Sigma-delta ADC according to an embodiment of the present invention It is a figure which shows an example.

The 3-bit Sigma-delta ADC shown in FIG. 5 is implemented as a primary Sigma-delta ADC circuit. For example, when the 2 * 2 binning mode is implemented, four pixel outputs may be simultaneously sampled by an addition of a basic sampling capacitor Cs 301 and an input sampling capacitor C _S1 , C _S2 , C _S3 302. Operation of the Sigma-delta ADC circuit shown in FIG. 5 for each sampling period shown in FIG. 6 is as follows.

P1: Integrator initialization section

Referring to FIG. 5, the ph1p switch 304, the ph2p switch 305, and the ph_rst switch 306 are turned on to be stored in the feedback capacitor C _F 303 while partially reducing power consumption of the integrator 311. The charged charge is initialized.

-P2: input voltage sampling and comparison section

After sampling the input voltage to the basic sampling capacitor (Cs) 301 using the ph1_IN switch 307 and the ph1p switch 304, the ph2_REFP switch 309 and the ph2p switch 305 are turned on so that the basic sampling capacitor (Cs) is turned on. The voltage at 301 is transferred to the feedback capacitor C _F 303. In this case, the voltage transferred to the feedback capacitor C _F 303 may be compared with the V _CM voltage (the middle value of the input voltage range) by the comparator 312 to obtain the first digital conversion data.

P3: digitally converted data acquisition interval

Sampling the input voltage to the basic sampling capacitor (C _S ; 301) using the ph1_IN switch 307 and ph1p switch 304, and then the ph2_REFP switch 309 and ph2_REFN switch using the digital data compared by the comparator in the interval P2 Select (310) to _connect the V _REFP (maximum value of the input voltage range) or V _REFN (minimum value of the input voltage range) voltage to the bottom plate of the basic sampling capacitor (C _S ; 301). In addition, the comparator 312 may obtain seven additional digital data from the second to the eighth in comparison with the output voltage of the integrator 311 and the V _CM voltage.

-P4: Integrator output adjustment section and last digital data acquisition section

After sampling the V _CM voltage through the ph1_CM switch 308 and the ph1p switch 304, the ph2_REFP switch 309 and the ph2_REFN switch 310 are selected using the digital data compared in the P2 interval to select V _REFP or V _REFN. Connect the voltage to the bottom plate of the basic sampling capacitor (C _S ; 301). In the P4 section, the final ninth digital data may be obtained from the comparator 312 using the integrator output voltage. The eighth through the second to ninth digital data output the 3-bit digital data through the decimation filter 313.

-P5: integrator output transfer section

The output voltage output from the integrator 311 is stored in the sampling capacitor of the SAR ADC of the later stage.

Next, FIG. 7 is a diagram illustrating an example of a circuit diagram of a SAR ADC according to an embodiment of the present invention.

Referring to FIG. 7, a SAR ADC according to an embodiment of the present invention may be implemented in a 12-bit double array structure. Since the SAR ADC according to the present invention should have a sampling function, the DAC in the SAR ADC is configured as a capacitor array as shown in FIG. 7. Alternatively, unlike the example shown in FIG. 7, an additional sample and fold circuit and another DAC may be used to implement a SAR ADC having a sampling function.

In this case, the SAR ADC samples the MOD_AOUT transferred from the Sigma-delta ADC using the ph_sample switch 401 and the ph_samplep switch 402 in the P5 (integrator output transfer period) section of the sampling period shown in FIG. 6. In binning mode, connect V _REFP to the positive input terminal to ensure that the output of the integrator does not exceed the allowable range.

8 is a diagram illustrating an example of a block diagram of a column ADC input terminal according to an embodiment of the present invention.

Referring to FIG. 8, a circuit stage consisting of switch blocks 1 to 4 (501 to 504), switches SD_SW1 to SD_SW4 (505 to 508), and sampling capacitors C _S1 to C _S4 (509 to 512) connected to each column line. Corresponds to the input of the Sigma-delta ADC. In order to implement the 2 * 2 binning mode, the input terminal of the two column ADC is connected to each pixel column line. As shown in FIG. 8, the n and n + 1 column lines of the pixel array are n and n + 1, respectively. Connect to each column ADC.

Accordingly, n odd column lines, n even column lines, n + 1 odd column lines, and n + 1 even column lines are connected to current sources ISRC1 to ISRC4 515 to 518, respectively, and output from each pixel. The output voltage is connected to analog buffers BUF1 to BUF4 519 to 522. At this time, the analog buffer may or may not be used by the RC load of the column line.

In the normal mode, the BIN_SW switch 523 is always turned off, and pixels connected to odd and even row lines sequentially by the scan driver are connected to each column line, and each switch block 501 to 504. And are alternately input to the column ADC through the switches 505 to 508.

On the other hand, in the binning mode, the BIN_SW switch 523 is always turned on and the pixels connected to the odd row lines and the even row lines by the scan driver are simultaneously connected through the sampling capacitor. At this time, the SD_SW6 switch 514 is always turned off so that the ADC [n + 1] 525 does not operate. Thus, four pixel voltages are simultaneously input to ADC [n] 524 using the charge averaging method.

9 is a flowchart illustrating an example of a process of driving the pixel array and the ADC according to an embodiment of the present invention over time. Specifically, in FIG. 9, the pixel array includes 3-Tr. Explain using structure.

Referring to FIG. 9, after the value of the pixel signal voltage V _SIG on the nth line is set through the column line (S601), A / D conversion is performed using the Sigma-delta ADC (S602). In this case, the integrator power consumption of the Sigma-delta ADC is partially reduced while the pixel signal voltage is settling. The partial power consumption reduction in the integrator will be described later.

Thereafter, the pixel reset voltage V _RST is transferred to the column line (S603), and at the same time, the Sigma-delta ADC maintains the voltage stored in the feedback capacitor C _F (S604). When the V _RST voltage transmitted to the column line is set (S603), Sigma-delta A / D conversion is performed using the V _RST voltage (S605). At this time, the V _RST voltage is sampled as opposed to the case of sampling the V _SIG voltage to obtain the result of A / D conversion of the difference between the two voltages. This can be easily achieved by changing the position across the sampling capacitor using a switch.

When the Sigma-delta A / D conversion is completed, the MOD_AOUT voltage is transferred to the sampling capacitor of the SAR ADC (S606).

The SAR ADC A / D converts the transferred MOD_AOUT voltage (S607), and performs Sigma-delta A / D conversion of the pixel located at line n + 1 during SAR A / D conversion time. Since the process corresponds to S601 to S606, the same description is omitted.

As described above, the A / D conversion method using the Sigma-delta ADC and the SAR ADC together according to the present invention can reduce the power consumption according to the operation by reducing the operation speed of the sub-ADCs constituting the ADC according to the present invention. have.

10 is a flowchart illustrating another example of a process in which a pixel array and an ADC are driven over time according to an embodiment of the present invention. Specifically, in FIG. 10, the pixel array includes 3-Tr. Explain using structure.

Referring to Figure 10, 3-Tr of the digital CDS scheme. The structure also uses the A / D conversion using the Sigma-delta ADC and SAR ADC scheme according to the present invention.

However, as shown in FIG. 10, after the value of the pixel signal voltage V _SIG on the nth low line is set through the column line (S701), A for the pixel voltage V _SIG using the Sigma-delta ADC is used. / D conversion is performed (S702). When the converted voltage V _SIG is transferred to the sampling capacitor of the SAR ADC (S703), the SAR ADC A / D converts the transferred pixel voltage V _SIG (S704).

While the pixel voltage V _SIG is A / D converted in the SAR ADC, the pixel reset voltage V _RST on the nth low line is settled through the column line (S705), and the pixel reset voltage V _RST using the Sigma-delta ADC. An A / D conversion is performed on (S706). When the converted pixel reset voltage V _RST is transferred to the sampling capacitor of the SAR ADC (S707), the SAR ADC performs A / D conversion on the pixel reset voltage V _RST (S708).

Subsequently, it is driven in such a manner as to derive the difference between the digitally converted voltage V _SIG and the voltage V _RST transmitted in steps S703 and S707. The digital conversion of the pixel voltage and the pixel reset voltage is performed respectively and the digitally converted positive voltage. It is distinguished from the analog CDS scheme described above with reference to FIG.

FIG. 11 is a diagram illustrating an example of an integrator circuit diagram in which an associative amplifier of a switch is applied to reduce power consumption in a Sigma-delta ADC according to an embodiment of the present invention.

Referring to FIG. 11, the integrator is composed of a two stage amplifier, and the MP1 transistor 800, the MP2 transistor 801, the MN1 transistor 804, the MN2 transistor 805, the MN5 transistor 806, and the MN3 transistor 807. Constitutes a first amplifier stage. The MP3 transistor 802, the MP4 transistor 803, the MN6 transistor 808, and the MN4 transistor 809 constitute a second amplifier stage.

When the output voltage of the pixel is set on the column line, the ph1p switch 810, ph2p switch 811, and ph_rst switch 812 are turned on, and the pwdnb_bin signal and the pwdnb signal are logic high and low, respectively, to form the MN5 transistor ( 806 is turned on while MP4 transistor 803 and MN6 transistor 808 are turned off. As a result, a power-down phenomenon occurs in which the current path of the line to which the MP3 transistor 802 and the MN6 transistor 808 constituting the second amplifier are connected is cut off, and current flows only in the first amplifier.

In an integrator in power-down mode, both ends of the frequency compensation capacitor will always form the same voltage. This initializes all voltage nodes in advance so that the integrator is turned on so that they are not affected by the initial node voltage during operation.

Therefore, the ADC according to the embodiment of the present invention may exhibit a partial power consumption reduction effect through partial power down in an integrator in which power consumption is generally maximized in a sigma-delta ADC. The power down process is also partially shown in FIG.

12 is a diagram illustrating an example of an output result for each gray level of sub-ADCs constituting a column ADC according to an exemplary embodiment of the present invention.

Specifically, in the circuit diagram shown in FIG. 12, the voltage V _REFP is inputted as 2V, the voltage V _REFN is inputted as 1V, and the input signal input range of the ADC is 1V. It shows the simulation result by macro-modeling the ADC circuit of -bit.

The Sigma-delta ADCs used in the simulation are designed to resolve 3-bits and the SAR ADCs are designed to resolve 12-bits. The final output of the integrator to the SAR ADC increases monotonically with increasing input voltage. However, after transitioning from the (3V _REFP + V _REFN ) / 4 voltage position to the point of (V _REFP + 3V _REFN ) / 4 voltage, it increases again, and this transition occurs 2 ^m times in the m-bit Sigma-delta ADC. do. At the point of transition, the output data of the Sigma-delta ADC is increased by 1 bit. The final output range of the integrator in the Sigma-delta ADC has half the signal input range of the Sigma-delta ADC and the SAR ADC. This can be achieved by designing the size of the feedback capacitor C _F to be twice the size of the sampling capacitor C _S on the column ADC circuit. Adjustment of the signal input range is made through error correction generated by offset voltages of comparators in the Sigma-delta ADC and the SAR ADC. The principle of error correction will be described later.

Since the integrator final output value has a pattern that repeats periodically with the input voltage, the output digital data of the SAR ADC also repeats periodically. As a result of digital processing the output of the sub-ADC, the final input / output characteristics of the ADC have the same slope with an ideal 14-bit ADC and a constant offset digital code. The offset digital code can be corrected by using the same output voltage after inputting the same analog voltage for each channel in the ADC using the analog CDS, and automatically removed from the ADC using the digital CDS.

FIG. 13 is a diagram illustrating an example of a technique for correcting a comparator offset in a Sigma-delta ADC according to an embodiment of the present invention.

Referring to FIG. 13, if the integrator output range in the Sigma-delta ADC is designed to be equal to the input range of the SAR ADC, missing codes 801 and 802 are generated according to the offset of the comparator or the error of the comparison voltage. If the integrator output range in the Sigma-delta ADC is designed to be half of the SAR ADC input range, error compensation can be performed if the comparator offset or comparison voltage is less than half the input range. Comparator errors in the SAR ADC can also be calibrated using the same method.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments described in the present invention are not intended to limit the technical idea of the present invention but to explain, and the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

Claims (12)

A pixel array including a plurality of pixels formed in the form of a two-dimensional array, a scan driver for selecting a row line constituting the pixel array, and a column driver for reading a photoelectric conversion signal from the pixels of the row line selected by the scan driver. In the image sensor comprising:
The column driver,
At least one column to analog converter (Analog to Digital Converter) for receiving a signal input from at least two column lines included in the pixel array,
The column ADC,
Sigma-delta ADC that receives A / D output voltages of pixels from at least two column lines of the pixel array and SAR ADC that performs A / D conversion by receiving output values of the Sigma-delta ADCs as input signals (Successive Approximation ADC), characterized in that the analog to digital converter for high resolution image sensor. The method of claim 1,
The pixel array,
An analog-to-digital converter for a high resolution image sensor, wherein the pixels of the odd row line and the pixels of the even row line are arranged to have different column lines. The method of claim 1,
The column driver,
A column ADC array including at least one column ADC and converting an output voltage of a pixel into a digital signal and outputting the digital signal;
A column digital processing unit for correcting an output result generated by the column ADC in the column ADC array; And
And an SRAM array for storing output results generated in said column ADC array. The method of claim 1,
The input terminal of the column ADC,
Each column constituting the pixel array is connected to at least two column output lines for outputting photoelectric conversion signals corresponding to the pixels of the odd row line and even row line, respectively, analog for high-resolution image sensor Digital converter. 5. The method of claim 4,
The column ADC,
Comprising a circuit including at least two current sources, at least two sampling capacitors and a plurality of switches for each channel unit of the column driver,
And sequentially receiving signals from the two column output lines through the circuit. 5. The method of claim 4,
The input terminal of the column ADC,
A switch connected between the two column output lines,
The switch is turned on in normal mode and turned off in binning mode. The method according to claim 6,
The column ADC,
And an output signal is simultaneously input from four adjacent pixels among the plurality of pixels constituting the pixel array by using the switch and the adjacent channel ADC. The method of claim 1,
The Sigma-delta ADC,
And a circuit comprising a feedback capacitor, a plurality of sampling capacitors, a plurality of switches and an integrator connected between the capacitors. 9. The method of claim 8,
The Sigma-delta ADC,
Sampling and holding the signal input to the first clock, and repeats the process of outputting the signal input from the second clock A / D to a digital signal, at the last clock output voltage of the integrator to the SAR ADC And outputting the output voltage as a digital signal by sampling the output voltage so as to be half of an input voltage range input thereto. 10. The method of claim 9,
The integrator is composed of two stage amplifiers of the first amplifier stage and the second amplifier stage,
While initializing all voltage nodes of the integrator to the same voltage, applying current only to the first amplifier stage and shorting the current paths of the second amplifier stages. 9. The method of claim 8,
The Sigma-delta ADC,
While the pixel signal voltage is inputted from the pixel array, while reducing the power consumption of the integrator to a predetermined level, the pixel signal voltage is A / D converted and stored and maintained in the integrator until the pixel reset voltage is inputted. And an A / D conversion by connecting opposite ends of the sampling capacitor with respect to the pixel reset voltage. 9. The method of claim 8,
The Sigma-delta ADC,
The A / D conversion is performed on the pixel signal voltage by setting the size of the feedback capacitor to twice the size of the sampling capacitor, and outputting the output voltage of the integrator to be half of the input voltage range applied to the SAR ADC. An analog-to-digital converter for a high resolution image sensor, characterized in that the voltage is sampled and output as a digital signal.

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