CN112398472B

CN112398472B - Error quantization 10-bit monoclinic ADC for image sensor

Info

Publication number: CN112398472B
Application number: CN201910750809.9A
Authority: CN
Inventors: 徐江涛; 史晓琳
Original assignee: Tianjin University Marine Technology Research Institute
Current assignee: Tianjin University Marine Technology Research Institute
Priority date: 2019-08-14
Filing date: 2019-08-14
Publication date: 2023-04-18
Anticipated expiration: 2039-08-14
Also published as: CN112398472A

Abstract

An error quantization 10-bit single-slope ADC for an image sensor comprises a two-stage comparator and a counter; in the ADC, a single ramp is adopted in the DDS process to improve the operation speed of the ADC, and more importantly, the ADC can quantize non-ideal factors existing in a reading circuit and complete DDS operation. Therefore, the number of clocks used by the counter during DDS and power consumption can be reduced. Meanwhile, the proposed monoclinic ADC uses two identical differential input pairs to ensure uniformity in the whole quantization process.

Description

Error quantization 10-bit monoclinic ADC for image sensor

Technical Field

The invention belongs to the field of analog integrated circuit design of microelectronics, and particularly relates to an error quantization 10-bit monoclinic ADC (analog to digital converter) for an image sensor.

Background

CMOS image sensors are widely used in various fields due to their low power and fast imaging speed. A conventional image sensor is shown in fig. 1, and includes a pixel, a Source Follower (SF), an Analog-to-Digital converter (ADC), and some Digital processing modules. Among these modules, the ADC is an important module that converts an analog pixel voltage value into a digital value. The core module of the readout circuit is the ADC. Various types of ADCs, such as cyclic ADCs, successive approximation ADCs, monoclinic ADCs, and oversampling ADCs, may be integrated in a CMOS image sensor. However, an amplifier with accurate gain is required in the successive approximation ADC, and a well-matched Digital-to-Analog converter (DAC) is required. The requirement of precision gain amplifiers not only increases the design difficulty, but also leads to significant layout complexity and column uniformity problems when placing the cyclic/successive approximation ADC into a small pitch column parallel readout circuit. Reading out the entire pixel array with a single on-chip ADC avoids the above-mentioned problems, but the frame rate of the image sensor is limited by the speed of the ADC. For the column parallel single-slope ADC, a common slope signal is connected to all column parallel read-out arrays, so that the layout area of the column parallel single-slope ADC can be effectively reduced, and the column parallel single-slope ADC is suitable for a small-pitch circuit. The two-stage monoclinic ADC can meet the requirement of a high-frame-frequency CMOS image sensor on the reading speed of a circuit, and make up for the defect of the reading speed of the monoclinic ADC. More importantly, a Correlated Double Sampling (CDS) operation may be performed in the single-slope ADC to ensure uniformity between readout columns, so that Fixed Pattern Noise (FPN) may be reduced. In general, analog CDS and Digital CDS (DDS) operation are common in a single-ramp ADC. Although an analog CDS circuit using capacitors and switches is easy to design, it is difficult to improve accuracy due to clock feedthrough errors and mismatch errors. In contrast, the DDS can effectively subtract the pixel reset signal and the pixel exposure signal in the digital domain, which can eliminate the non-uniformity caused by reset kT/C noise, clock feedthrough, and ramp delay present in the column readout circuit. Fig. 2 shows a process of performing DDS operation to quantize non-ideal factors in a conventional single-slope ADC. The counter starts counting down when the ramp starts to fall and stops counting when the comparator state is low, thereby obtaining a clock count of non-idealities. In this case, the counter quantifies the number of clocks of the difference between DACRST and Vrefh together with the non-ideal factor. However, conventional single-slope ADCs that operate with DDS have two obstacles. On the one hand, two ramps are required to complete the DDS operation, which reduces the conversion speed of the single-ramp ADC. On the other hand, to eliminate the effects of non-idealities, the additional voltage signal is typically digitized during the first DDS stage, and the digital code is used to subtract from the pixel signal. This means that the column digital counter consumes more power than the analog CDS, especially in a high speed single-slope ADC which requires a high speed count clock.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an Error Quantization (EQ) 10-bit monoclinic ADC for an image sensor; in the ADC, a single slope is adopted in the DDS process to improve the operation speed of the ADC, and more importantly, the ADC can quantize the existence of non-ideal factors in a reading circuit and complete DDS operation. Therefore, the number of clocks used by the counter during DDS and power consumption can be reduced. At the same time, the proposed single-slope ADC uses two identical differential input pairs to ensure uniformity throughout the quantization process.

An error quantization 10-bit single-slope ADC for an image sensor has a structure shown in fig. 3, and the ADC is composed of a two-stage comparator and a counter, and the specific connection relationship is as follows: the PIXEL output PIXEL is connected to a left electrode plate of a capacitor C1, a right electrode plate of the capacitor C1 is connected to a positive input end of a first-stage comparator, a positive input end of the first-stage comparator is connected with a negative output end of the first-stage comparator through a switch S1, a RAMP signal RAMP is connected to a left electrode plate of a capacitor C2, a right electrode plate of the capacitor C2 is connected to a negative input end of the first-stage comparator, a negative input end of the first-stage comparator is connected with a positive output end of the first-stage comparator through a switch S2, a negative output end of the first-stage comparator is connected with a left electrode plate of a capacitor C3, a right electrode plate of the capacitor C3 is connected with a negative input end of a second-stage comparator, a negative input end of the second-stage comparator is connected with an output end VO of the second-stage comparator through a switch S3, a common mode voltage VCM is connected to a positive input end of the second-stage comparator, and an output of the comparator is connected to a 10-bit counter.

An error quantization 10-bit single-slope ADC for an image sensor is disclosed, the working time sequence is shown in FIG. 4, firstly, in the stage A, the first reset operation of a comparator is completed through switches S1, S2 and S3; AZ and BZ respectively carry out reset operation on the first-stage comparator and the second-stage comparator; meanwhile, the pixel outputs its reset voltage VRST, and the ramp generator outputs a fixed voltage value DACRST; during this phase, the left plates of the capacitors C1 and C2 are connected to VRST and DACRST, respectively, while the right plate voltages of C1 and C2 are a common-mode voltage VCM defined by the first-stage comparator when the reset signal AZ is on; therefore, the voltage value VRST-VCM and the non-ideal factor are stored across the capacitor C1; similarly, the voltage value DACRST-VCM and non-idealities are stored across capacitor C2; at the end of the first reset phase, S3 is turned off later than S1 to reduce the non-idealities introduced by the clock and charge injection.

The quantification of the non-idealities is done in the B-phase: firstly, adjusting the RAMP to the maximum voltage Vrefh thereof, so as to generate voltage jump at a C2 left plate and a VCN node; then, the VCN will follow the ramp down, flipping at the comparator output when VCN crosses VCM; meanwhile, the counter in the proposed single-slope ADC starts counting down when the ramp falls to DACRST, and stops counting when the comparator state is low; in this way, the value recorded by the counter represents only all non-ideal factors, thus saving power consumption.

The reset operation of the second-stage comparator is completed in the stage C, and the process is similar to the reset process of the first-stage comparator; the only difference is that DACMID-VCM is stored across capacitor C2; where DACMID is the RAMP voltage after the resets S1 and S2 of the second stage comparators are turned off, and the output of the pixel changes from the reset voltage VRST to its exposure voltage Vsig; in this phase, the counter stops counting, keeping its current value.

In the D phase, the counter starts counting up and VCN will follow the RAMP down. When VCN crosses VCM, the comparator flips and the counter stops counting. Finally, the counter digitally counts the difference voltage between VRST and Vsig and eliminates non-ideal factors.

A10-bit monoclinic ADC for error quantization of an image sensor is provided with a single slope, can effectively reduce redundant counting and power consumption in a sampling quantization process, effectively reduces chip power consumption and improves quantization speed. And the requirements of high precision and low power consumption of the image sensor are further met, and the application range of the image sensor is expanded.

Drawings

FIG. 1 is a schematic diagram of a graphical sensor configuration;

FIG. 2 is a conventional monoclinic ADC operating timing sequence;

FIG. 3 is a schematic diagram of the proposed single-slope ADC;

fig. 4 is a proposed monoclinic ADC operation timing.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, a detailed description of embodiments of the present invention will be given below with reference to examples. As shown in the left dashed box of fig. 2, in this example, both comparators are implemented with a conventional 5-tube operational amplifier, the ac gain of the single comparator is about 48dB, and the total gain and power consumption of the comparator are 97dB and 6.6 μ W, respectively. The capacitor is realized by using a MOS capacitor, wherein the size of C1 is W =33 μm, and L =2 μm. The size of C2 is W =33 μm, L =2 μm. C1 and C2 can satisfy the matching requirement of 10-bit precision. C3 and C1 or C2 do not need to be matched, the matching of C3 in the columns has little influence on the result, and the size of C3 is only W =9um, l =2um. The 10-bit counter circuit structure is shown in a dashed box on the right side of fig. 2 and is implemented by a string of cascaded D flip-flops. The counter is clocked at 80MHz. The proposed monoclinic ADC was realized and simulated by a 130nm process. The readout circuit achieves column FPN of 0LSB and 9.8LSB under dark (pixel output of 0.1V) and bright (pixel output of 1.2V) conditions, the counter saving power consumption of 58.7% and 23.6% respectively.

Claims

1. An error-quantized 10-bit monoclinic ADC for an image sensor, characterized by: the device consists of a two-stage comparator and a counter; the PIXEL output PIXEL is connected to a left pole plate of a capacitor C1, a right pole plate of the capacitor C1 is connected to a positive input end of a first-stage comparator, the positive input end of the first-stage comparator is connected with a negative output end of the first-stage comparator through a switch S1, a RAMP signal RAMP is connected to a left pole plate of a capacitor C2, a right pole plate of the capacitor C2 is connected to a negative input end of the first-stage comparator, the negative input end of the first-stage comparator is connected with a positive output end of the first-stage comparator through a switch S2, the negative output end of the first-stage comparator is connected with a left pole plate of a capacitor C3, a right pole plate of the capacitor C3 is connected with a negative input end of a second-stage comparator, the negative input end of the second-stage comparator is connected with an output end VO of the second-stage comparator through a switch S3, a common mode voltage VCM is connected to the positive input end of the second-stage comparator, and the output of the comparator is connected to a 10-bit counter;

firstly, in the phase A, the first reset operation of the comparator is completed through the switches S1, S2 and S3; AZ and BZ respectively carry out reset operation on the first-stage comparator and the second-stage comparator; meanwhile, the pixel outputs its reset voltage VRST, and the ramp generator outputs a fixed voltage value DACRST; during this phase, the left plates of the capacitors C1 and C2 are connected to VRST and DACRST, respectively, while the right plate voltages of C1 and C2 are a common-mode voltage VCM defined by the first-stage comparator when the reset signal AZ is on; therefore, the voltage value VRST-VCM and the non-ideal factor are stored across the capacitor C1; the voltage value DACRST-VCM and the non-ideal factor are stored at two ends of the capacitor C2; at the end of the first reset phase, S3 is turned off later than S1 to reduce the non-idealities introduced by the clock and charge injection;

the quantification of the non-idealities is done in the B-phase: RAMP is adjusted to its maximum voltage Vrefh, thereby generating a voltage jump at the C2 left plate and the VCN node; then, the VCN will follow the ramp down, flipping at the comparator output when VCN crosses VCM; meanwhile, the counter in the proposed single-slope ADC starts counting down when the ramp falls to DACRST, and stops counting when the comparator state is low;

the reset operation of the second-stage comparator is completed in the stage C, which is similar to the reset process of the first-stage comparator; the only difference is that DACMID-VCM is stored across capacitor C2; where DACMID is the RAMP voltage after the resets S1 and S2 of the second stage comparators are turned off, and the output of the pixel changes from the reset voltage VRST to its exposure voltage Vsig; in this phase, the counter stops counting, keeping its current value;

in phase D, the counter starts counting up, VCN will follow RAMP down; when VCN crosses VCM, the comparator is turned over, and the counter stops counting; finally, the counter digitally counts the difference voltage between VRST and Vsig and eliminates non-ideal factors.