CN111182246B

CN111182246B - CMS-based CMOS image sensor reading circuit

Info

Publication number: CN111182246B
Application number: CN202010030179.0A
Authority: CN
Inventors: 殷景志; 刘芳园; 常玉春
Original assignee: Jilin University
Current assignee: Changguang Cangzhou Raster Sensing Technology Co ltd
Priority date: 2020-01-13
Filing date: 2020-01-13
Publication date: 2021-08-03
Anticipated expiration: 2040-01-13
Also published as: CN111182246A

Abstract

The invention discloses a CMS (CMS) technology-based low-noise image sensor reading circuit architecture, which belongs to the technical field of semiconductor image sensing. CMS technology is applied to both analog and digital parts in the same reading circuit, noise of the reading circuit is effectively reduced, the standard of an ultra-low noise image sensor can be achieved, circuit advantages can be achieved according to specific application, and the CMS technology has high compatibility. Meanwhile, the circuit greatly reduces the layout area and complexity, and the utilization rate of the chip area is higher.

Description

CMS-based CMOS image sensor reading circuit

Technical Field

The invention belongs to the technical field of semiconductor image sensing, and particularly relates to a readout circuit of a CMOS (complementary metal oxide semiconductor) image sensor based on CMS (correlated multiple sampling) technology.

Background

CMOS image sensors are widely used in people's work and life due to their high integration and low cost, and their technology and performance have been dramatically advanced over the years, and they have not only been limited to low-end consumer and monitoring applications, but also to high-end scientific, bio-imaging, industrial, aerospace, and other applications. Most high-end applications require CMOS sensors to have characteristics such as high dynamic range, high speed, low noise, low dark current, global shutter, etc.

Noise is one of the important indicators for measuring the quality of the image sensor, and therefore, analog readout circuit noise research of the image sensor is also a hot spot. The commonly applied related double sampling method can greatly weaken the noise of the sensor, thereby increasing the signal-to-noise ratio and enhancing the imaging quality, and therefore, the method has important significance for the research of a reading circuit. The application of related multiple sampling in the ultra-low noise image sensor is necessary, and the noise reduction efficiency of the ultra-low noise image sensor is greatly improved, so that the image quality is greatly improved.

In the design of the current image sensor readout circuit, due to the limitation of chip size and pixel size, the readout chain often has difficulty in using complex circuits to achieve ultra-low noise performance. A well-known method of noise reduction is to limit the bandwidth and correlated double sampling. The method of limiting the bandwidth is easier to implement, but the noise reduction effect cannot achieve a better effect due to the limitation of the amplifier establishing time. The correlated double sampling technology can greatly reduce the thermal noise and 1/f noise of a source follower in a pixel and reduce the noise of a PGA, but the sampling has randomness, so that a large amount of noise is still left unprocessed.

Disclosure of Invention

In order to solve the technical problem, the invention provides an ultra-low noise image sensor reading circuit based on CMS, which adopts analog and digital modules to simultaneously apply CMS technology and can realize the ultra-low noise reading circuit.

The invention is realized by the following technical scheme:

a CMS-based ultra-low noise image sensor reading circuit comprises active pixels, column bus current sources, a gain programmable amplifier, a sample-and-hold circuit with a CMS function and a ramp-mode ADC (Analog-to-digital converter) with the CMS function; light from a scene is focused on each pixel through an optical system, light intensity information is converted into a voltage signal through an active pixel, the voltage signal is transmitted to the input end of a gain programmable amplifier through a column bus, a column bus current source provides bias current for a source follower in the active pixel, pull-down current is provided for the column bus, the voltage signal is zoomed through the gain programmable amplifier, the zoomed voltage amplitude is in a voltage range which can be processed by a subsequent circuit, and then, a sampling and holding circuit is used for sampling and storing reference voltage and signal voltage for multiple times; and finally, performing digital conversion on the two groups of voltage values stored in the sampling and holding circuit for many times by using a low-power-consumption slope ADC with a CMS function, and subsequently performing data processing and reading.

Further, the sample-and-hold circuit with the CMS function includes 4 sampling capacitors (C1, C2, C3, C4), 4 sampling control switches (S1, S2, S3, S4), and 1 readout capacitor (C4)_OUT) And 2 readout switches (S5, S6); the input ends of the two switches S1 and S3 are connected with the output signal of the pre-gain programmable amplifier, the output ends are respectively connected with the positive plates of the sampling capacitors C1 and C3, and the negative plates of the sampling capacitors C1 and C3 are grounded. The input ends of the switches S2 and S4 are respectively connected with the positive plates of C1 and C3, the output ends of the switches S2 and S4 are respectively connected with the positive plates of the sampling capacitors C2 and C4, and the negative plates of the C2 and C4 are grounded. Two input ends of the readout switches S5 and S6 are respectively connected to positive plates of the sampling capacitors C2 and C4, and the other two output ends are connected to a positive plate of the readout capacitor COUT, wherein the negative plate of the COUT is grounded.

As shown in fig. 2, the switch S1, the capacitor C1, the switch S2 and the capacitor C2 on the left side are used for time-sharing sampling of the reset voltage, and as shown in fig. 3, the switch S2 is opened at a time T2 from a time T1, and then the VR1 voltage is stored in the C2, that is, the first sampling is completed; the switch S1 is opened again at the time T3, and the VR2 voltage is stored in the C1, namely the second sampling is completed; then the charges in the C1 and the C2 are shared by closing S2 and S5 and then transferred to COUT, namely, two times of sampling of the reset voltage is completed, and infinite times of sampling of the reset voltage can be realized in the same sampling and storage mode; the right side S3, C3, S4 and C4 are used for time-sharing sampling of the signal voltage, starting from the time T3, the switch S4 is opened at the time T4, and then the VS1 voltage is stored in the C4, namely the first sampling is completed; the switch S1 is opened again at the time of T5, and the VS2 voltage is stored in the C3, namely the second sampling is completed; then the charges in C3 and C4 are shared by closing S4 and S6 and transferred to COUT, i.e. two samples of the signal voltage are completed, and infinite samples of the signal voltage can be obtained in the same sampling and storing manner.

Further, the ramp type ADC with CMS function includes a main comparator, wherein the positive phase input signal is the output signal (STORAGE _ OUT) of the previous stage sample-and-hold circuit, the negative phase input terminal is the shaped ramp signal, and the output comparison result is the result of a set of correlated double sampling (CDS _ OUT), which is also the count signal of the next stage counter; wherein the shaped ramp signal is generated by a ramp signal generator with a shaping function, which consists of four comparators, a DAC (digital-to-analog converter), and an analog driver that pulls down the ramp signal to a reset signal; the four comparators are the same 5-tube comparators, the positive phase input ends of the four comparators are reference voltages (VREF _ S0, VREF _ S1, VREF _ S2 and VREF _ S3) with different voltage values, and the negative phase input ends of the four comparators are connected with the output signal of the preceding stage sample and hold circuit in common; the four comparators output a group of binary digital codes which are used as four input signals of the DAC, the DAC converts the group of 4-bit digital codes into an analog voltage (VREF _ SIG), and the calibration of the voltage range of the VSIG is completed in the process; the analog voltage is used as a reset voltage value of the large RAMP signal, and the reset voltage is connected with a positive input end of the analog driver to reset the RAMP signal to the voltage value, so that the function of adjusting the reset voltage of the RAMP signal according to the size of the input signal is realized, and the shaping function of the RAMP is realized.

The principle of the CMS-based ultra-low noise image sensor readout circuit of the invention is as follows:

firstly, resetting and exposing pixels, converting optical signals into electric signals, carrying out voltage amplification through a source follower in the active pixels, adjusting the voltage amplitude of the electric signals to a range matched with a subsequent circuit, and respectively carrying out multiple sampling on the two signals through a sampling and holding circuit consisting of a switch and a sampling capacitor by a group of VRST (voltage of reset) and VSIG (voltage of signal) amplified by PGA. The design can realize N times of sampling in the least time, so that the circuit structure can be flexibly applied to balance the relation between line frequency and noise, and the VRST and the VSIG are read out after sampling; finally, the ramp ADC with CMS function is applied, the proposed ADC has the function of automatically adjusting the ramp size according to the input range, so that the conversion time and power consumption of the ADC can be greatly reduced, and the signal can be quantized through a plurality of same ramps, the function of reducing noise is realized again, and the electric signal is read out.

Compared with the prior art, the invention has the following advantages:

1. the novel sample-and-hold circuit with the related multi-sampling function can realize the multi-sampling function, saves the sampling capacitance compared with the traditional related multi-sampling circuit, can select the sampling times by self, is not limited, and can balance the sampling times and time according to line time in the application process;

2. compared with the traditional CMS ramp ADC, the ramp ADC with the CMS function has the advantages that the automatic regulation function of a large ramp signal is added, the output signal of a superior sampling and holding circuit can be matched to complete multiple times of sampling, the conversion speed of the ADC is greatly improved, and the power consumption of the ADC part is greatly reduced.

Drawings

FIG. 1 is a schematic diagram of the overall architecture of a CMS based ultra low noise image sensor readout circuit of the present invention;

FIG. 2 is a schematic diagram of a CMS enabled sample-and-hold circuit of the present invention;

FIG. 3 is a timing diagram illustrating the operation of the CMS enabled sample-and-hold circuit of the present invention;

FIG. 4 is a schematic diagram of a ramp ADC with CMS function according to the present invention;

FIG. 5 is a timing diagram illustrating the operation of the ramp ADC with CMS function according to the present invention;

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

Example 1

The image sensor of the present invention is fully compatible with the standard CMOS process, and the following describes in detail a readout process of an image sensor based on the 0.18 μm standard CMOS process with reference to the drawings and examples.

As shown in fig. 1, a CMS-based ultra-low noise image sensor readout circuit includes an active pixel, a column bus current source, a gain programmable amplifier, a sample-and-hold circuit with CMS function, and an Analog-to-digital converter (ADC) with CMS function; light from a scene is focused on each pixel through an optical system, light intensity information is converted into a voltage signal through the active pixels, the voltage signal is transmitted to the input end of the gain programmable amplifier through a column bus, and a column bus current source provides bias current for a source follower in the pixel and provides pull-down current for the column bus. The voltage signal is zoomed through a gain programmable amplifier, the zoomed voltage amplitude is in a voltage range which can be processed by a subsequent circuit, and then the reference voltage and the signal voltage are respectively sampled and stored through a sampling and holding circuit; and finally, performing digital conversion on the two groups of voltage values stored in the sampling and holding circuit for multiple times by using a slope ADC with CMS function, and subsequently performing data processing and reading.

Specifically, the pixel converts the light intensity information into an electrical signal, performs amplification and noise reduction processing by SF (source follower), performs scaling processing of 0.5 to 8 times on the analog signal by PGA, inputs the signal into a sample-and-hold circuit with CMS function, and then performs analog-to-digital conversion by a ramp ADC capable of automatically adjusting ramp signals. The readout process from the light intensity signal to the digital signal is completed.

As shown in fig. 2, which is a structure diagram of a sample-and-hold circuit with a multiple correlated sampling function, the input terminals of two switches S1 and S3 are connected to the output signal of the pre-gain programmable amplifier, and the output terminals are respectively connected to the positive plates of sampling capacitors C1 and C3, wherein the negative plates of C1 and C3 are grounded. The input ends of the switches S2 and S4 are respectively connected with the positive plates of C1 and C3, the output ends of the switches S2 and S4 are respectively connected with the positive plates of the sampling capacitors C2 and C4, and the negative plates of the C2 and C4 are grounded. Two input ends of the readout switches S5 and S6 are respectively connected to positive plates of the sampling capacitors C2 and C4, and the other two output ends are connected to a positive plate of the readout capacitor COUT, wherein the negative plate of the COUT is grounded. The voltage signal on the COUT positive plate represents the voltage values of VRST and VSIG, i.e. the voltage values to be quantized by the lower level ADC. Fig. 3 shows the timing of the operation of each sampling switch to achieve multiple sampling. Firstly, all switches are opened, the S1 and S2 switches are closed at the time of T1, the voltage V1 at the input end is stored by C1 and C1 capacitors, the S2 switch is opened at the time of T2, then the V1 voltage is stored by C2, the S1 switch is opened at the time of T3, the V2 voltage is sampled and held by the C1 capacitor, then S2 and S5 are closed, the internal charges of C1 and C2 are shared, and the charges are stored in COUT at the same time, and the voltage after the charges are shared is given by formula 1:

at this time, the COUT top plate voltage is 0.5 × (v1+ v2), and two samples are completed at time T4. Meanwhile, the switches S3 and S4 are turned off at time T3, at this time, the voltage V3 at the input end is stored by the capacitors C3 and C4, the switch S4 is turned off at time T4, the voltage V3 is stored by the capacitor C4, the switch S3 is turned off at time T5, the voltage V4 is sampled and held by the capacitor C3, the capacitors S4 and S6 are turned on, the internal charges of the capacitors C3 and C4 are shared, and the charges are stored in the COUT at the same time, according to formula 1, the voltage on the plate of the COUT is 0.25 × at this time (V1+ V2+ V3+ V4), and the sampling is completed 4 times at time T6. By analogy with this sampling, 8 samples are completed at time T10.

As shown in fig. 4, for the overall architecture of the ramp ADC with CMS function, firstly, the VRST and VSIG sampled before are compared with four customized reference voltages, and this procedure only judges and shapes the large ramp signal, so that the 4 reference voltages are set to be 500mV, 1000mV, 1500mV, and 2000mV respectively. Assuming that the voltage value of VSIG is 1300mV, a set of 4-bit digital signals, i.e. 0011, can be obtained from the comparison result of the comparator, the 4-bit digital signals are converted into a voltage value of 1000mV by the DAC, the voltage value is returned to the reset level as a large ramp signal, and the voltage amplitude of the large ramp signal is set to 700mV in order to ensure that the main comparator of the ADC can be correctly inverted. Therefore, the reset level of the large ramp signal is 1000mV, and the maximum voltage value is 1700 mV. This realizes the shaping function of the large ramp signal, and at the same time, each signal is quantized for 4 times, that is, VRST and VSIG are quantized for 4 times, respectively, thereby realizing the function of related multiple sampling.

With the framework of fig. 2, in conjunction with the timing operation of fig. 3, considering the balance between the line frequency and the noise, the optimal sampling number is 8, that is, 8 samplings of VRST are achieved at time T10, and the sampling of VSIG is completed with the same sampling time and the same sampling time interval. While ramp shaping and 4 ADC conversions are performed during the time of readout after sampling. As shown in fig. 5, the four quantizations of VRST are completed by 4 small slopes, the four quantizations of VSIG are completed by 4 large slope signals, and the noise is reduced by subsequent data processing.

The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.

It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.

In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.

Claims

1. A CMS-based ultra-low noise image sensor readout circuit is characterized by comprising active pixels, column bus current sources, a gain programmable amplifier, a sample-and-hold circuit with CMS function and a ramp-mode ADC with CMS function; light from a scene is focused on each pixel through an optical system, light intensity information is converted into a voltage signal through an active pixel, the voltage signal is transmitted to the input end of a gain programmable amplifier through a column bus, a column bus current source provides bias current for a source follower in the active pixel, pull-down current is provided for the column bus, the voltage signal is zoomed through the gain programmable amplifier, the zoomed voltage amplitude is in a voltage range which can be processed by a subsequent circuit, and then, a sampling and holding circuit is used for sampling and storing reference voltage and signal voltage for multiple times; finally, the two groups of voltage values stored in the sampling holding circuit are subjected to digital conversion for multiple times by using a low-power consumption slope ADC with a CMS function, and then data processing and reading are carried out;

the sample-and-hold circuit with CMS function comprises 4 sampling capacitors (C1, C2, C3 and C4), 4 sampling control switches (S1, S2, S3 and S4), 1 readout capacitor and 2 readout switches (S5 and S6); the input ends of the S1 and S3 switches are connected with the output signal of the front gain programmable amplifier, the output ends of the S1 and S3 switches are respectively connected with the positive plates of the sampling capacitors C1 and C3, and the negative plates of the sampling capacitors C1 and C3 are grounded; the input ends of the switches S2 and S4 are respectively connected with the positive plates of C1 and C3, the output ends of the switches S2 and S4 are respectively connected with the positive plates of sampling capacitors C2 and C4, and the negative plates of C2 and C4 are grounded; two input ends of the reading switches S5 and S6 are respectively connected with positive plates of the sampling capacitors C2 and C4, the other two output ends are connected with the positive plate of the reading capacitor, and the negative plate of the reading capacitor is grounded;

the ramp type ADC with the CMS function comprises a main comparator, wherein a normal phase input signal is an output signal of a preceding stage sampling and holding circuit, a reverse phase input end is a shaped ramp signal, and an output comparison result is used as a group of related double sampling results and is also a counting signal of a later stage counter; the ramp signal generator with the shaping function consists of four comparators, a DAC and an analog driver which enables the ramp signal to be pulled down to a reset signal; the four comparators are the same 5-tube comparators, the positive phase input ends of the four comparators are reference voltages (VREF _ S0, VREF _ S1, VREF _ S2 and VREF _ S3) with different voltage values, and the negative phase input ends of the four comparators are connected with the output signal of the preceding stage sample and hold circuit in common; the four comparators can output a group of binary digital codes which are used as four input signals of the DAC, the DAC converts the group of 4-bit digital codes into an analog voltage, and the calibration of the voltage range of the VSIG is completed in the process; the analog voltage is used as a reset voltage value of the large RAMP signal, and the reset voltage is connected with a positive input end of the analog driver to reset the RAMP signal to the voltage value, so that the function of adjusting the reset voltage of the RAMP signal according to the size of the input signal is realized, and the shaping function of the RAMP is realized.