CN217307780U - Image sensor and electronic device - Google Patents

Abstract

The application provides an image sensor and an electronic device, wherein a bit line module is arranged, and a low-gain reset signal is sampled to a first equivalent capacitor in a first state; in a second state, sequentially sampling and outputting the high-gain reset signal and the high-gain image signal through a second gain output bit line; when the second state is restored to the first state, outputting the low-gain reset signal sampled in the first equivalent capacitor through the first gain output bit line, and then sampling and outputting the low-gain image signal through the first gain output bit line; therefore, the high dynamic range of the image sensor is realized, and meanwhile, the cost is reduced and the volume of the image sensor is reduced; because the output of the pixel circuit does not need to be sampled and held to reduce the KT/C noise of the circuit, the noise level of the circuit is lower, and the performance of the image sensor is further improved.

Description

Image sensor and electronic device

Technical Field

The application relates to the technical field of image sensors, in particular to an image sensor and an electronic device.

Background

The dynamic range is a key factor of the imaging quality of the image sensor, the dynamic range is large, scene image information in a wider light intensity range can be output, and richer image details are presented. The dynamic range of the output of the image sensor is about 60-70 db in general, and the dynamic range required for capturing image information of highlight and shadow parts in general natural environment applications is about 100 db. In the design of an image sensor, there are several ways to improve the dynamic range, for example, further improving the full-well charge capacity of a pixel circuit, and obtaining a larger dynamic range; or a mode of reading multi-frame images and performing multi-frame synthesis is adopted to realize the high dynamic range of the image sensor.

A Dual Conversion Gain (DCG) mode is mainly applied to an image sensor, and improves the Conversion Gain by a small integration capacitance under a low illumination condition to improve the sensitivity; the storage charge is increased by a larger integration capacitor under the condition of high illumination, and the conversion gain is reduced to improve the dynamic range. Due to the fact that time difference exists in the process of reading the multiple frames in the implementation mode of the double-conversion gain mode which adopts the high dynamic range of the multiple-frame synthesis, the phenomenon of trailing can occur in the finally synthesized image, and the reading noise of the circuit is large. How to further increase the dynamic range of the image sensor, reduce the noise of the pixel circuit, and at the same time reduce the quantization circuit area is a major problem in the current design.

SUMMERY OF THE UTILITY MODEL

In order to overcome at least the above-mentioned deficiencies in the prior art, the present application is directed to an image sensor and an electronic device.

In a first aspect, an embodiment of the present application provides an image sensor, including:

a pixel circuit having two states, in a first state, outputting a low-gain reset signal or a low-gain image signal, and in a second state, outputting a high-gain reset signal or a high-gain image signal; the pixel circuit is configured to sequentially output a low-gain reset signal, a high-gain image signal, and a low-gain image signal; the bit line module is connected with the pixel circuit and comprises a first gain output bit line and a second gain output bit line, the first gain output bit line comprises a first equivalent capacitor, and the second gain output bit line comprises a second equivalent capacitor; the bit line module is configured to sample the low-gain reset signal to the first equivalent capacitor in a first state of the pixel circuit, sample and output the high-gain reset signal and the high-gain image signal sequentially through the second gain output bit line in a second state of the pixel circuit, output the low-gain reset signal sampled in the first equivalent capacitor through the first gain output bit line when the pixel circuit is restored from the second state to the first state, and then sample and output the low-gain image signal through the first gain output bit line; the reading circuit is connected with the bit line module, has two states, and sequentially receives the high-gain reset signal and the high-gain image signal and respectively quantizes the signals to obtain an effective image signal quantization value under high gain in the first state; and in the second state, the low-gain reset signal and the low-gain image signal are sequentially received and respectively quantized to obtain an effective image signal quantization value under low gain.

In one possible implementation manner, the pixel circuit includes a photosensitive element, a reset transistor, a transmission transistor, a source follower transistor, a dual conversion gain transistor, and a row selection module, where the row selection module includes a low-gain row selection switch and a high-gain row selection switch, and the low-gain row selection switch and the high-gain row selection switch are connected in parallel; the first end of the low-gain row selection switch is connected with the output end of the source electrode following transistor, and the second end of the low-gain row selection switch is connected with the first equivalent capacitor; the low-gain row selection switch is used for sampling the low-gain reset signal to the first equivalent capacitor in a first state of the pixel circuit and outputting the low-gain reset signal through the first gain output bit line when the second state of the pixel circuit is restored to the first state, and transmitting the low-gain image signal from the pixel circuit to the first equivalent capacitor and outputting the low-gain image signal through the first gain output bit line after the second state is restored to the first state; the first end of the high-gain row selection switch is connected with the output end of the source electrode follower transistor, and the second end of the high-gain row selection switch is connected with the second equivalent capacitor; the high-gain row selection switch is used for sequentially transmitting the high-gain reset signal and the high-gain image signal to the second equivalent capacitor in a second state of the pixel circuit and outputting the signals through a second gain output bit line.

In one possible implementation, the bit line module further includes a source follower current source, a low-gain bit line select switch, and a high-gain bit line select switch; a first end of the low-gain bit line selection switch is connected to the source electrode following current source, a second end of the low-gain bit line selection switch is connected to the first gain output bit line, and the low-gain bit line selection switch is used for selecting the source electrode following current source to provide working current for the first gain output bit line; the first end of the high-gain bit line selection switch is connected to the source electrode following current source, the second end of the high-gain bit line selection switch is connected to the second gain output bit line, and the high-gain bit line selection switch is used for selecting the source electrode following current source to provide working current for the second gain output bit line.

In one possible implementation, the readout circuit includes a gain quantization selection circuit, a comparison circuit, a counter and a memory, which are connected in sequence, and the gain quantization selection circuit is configured to sequentially access the high-gain reset signal and the high-gain image signal to the comparison circuit in a first state of the readout circuit; the gain quantization selection circuit is further configured to sequentially switch in the low gain reset signal and the low gain image signal to the comparison circuit in a second state of the readout circuit.

In one possible implementation, when the readout circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare a ramp voltage with the high-gain reset signal and output a first comparison signal; the counter is configured to count when the first comparison signal is received and record a first count result when the ramp voltage and the high-gain reset signal overlap; when the readout circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter is configured to count in an opposite direction from the first count result when the second comparison signal is received, and output a second count result when the ramp voltage and the high-gain image signal overlap, the second count result being a difference between a high-gain image signal quantization result and a high-gain reset signal quantization result; the memory is configured to store the second count result and to use the second count result as an effective image quantization value at the high gain; when the readout circuit quantizes the low-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the low-gain reset signal and output a third comparison signal; the counter is configured to count when the third comparison signal is received and record a third counting result when the ramp voltage and the low-gain reset signal overlap; when the readout circuit quantizes the low-gain image signal, the comparison circuit is configured to compare the ramp voltage and the low-gain image signal and output a fourth comparison signal; the counter is configured to count in an opposite direction from the third count result when the fourth comparison signal is received, and output a fourth count result when the ramp voltage and the low-gain image signal overlap, the fourth count result being a difference between a low-gain image signal quantization result and a low-gain reset signal quantization result; the memory is configured to store the fourth count result and to use the fourth count result as an effective image quantization value at the low gain.

In one possible implementation manner, the comparison circuit includes a comparator, a first capacitor, a second capacitor, a first zero clearing switch, and a second zero clearing switch; the positive phase input end of the comparator is connected to a ramp voltage through the first capacitor, and the negative phase input end of the comparator is connected to the gain quantization selection circuit through the second capacitor; the positive phase input end of the comparator is connected with the first end of the first zero clearing switch, and the negative phase input end of the comparator is connected with the first end of the second zero clearing switch; and a positive phase output end of the comparator is connected with the second end of the first zero clearing switch, and a first reverse phase output end of the comparator is connected with the second end of the second zero clearing switch.

In one possible implementation, the first capacitor is a variable capacitor.

In one possible implementation, the slope of the ramp voltage is adjustable.

In one possible implementation, the gain quantization selection circuit includes a high gain quantization switch and a low gain quantization switch; a first end of the high-gain quantization switch is connected to the second gain output bit line to serve as a high-gain reset signal input end of the gain quantization selection circuit and a high-gain image signal input end of the gain quantization selection circuit; a first end of the low-gain quantization switch is connected to the first gain output bit line to serve as a low-gain reset signal input end of the gain quantization selection circuit and a low-gain image signal input end of the gain quantization selection circuit; the second end of the high-gain quantization switch and the second end of the low-gain quantization switch are connected with the first end of the second capacitor in parallel, and the second end of the second capacitor is connected with the inverting input end of the comparator.

In a second aspect, an embodiment of the present application further provides an electronic device, which includes the above image sensor.

According to the image sensor and the electronic equipment provided by the embodiment of the application, the bit line module is arranged, and in a first state, a low-gain reset signal is sampled to the first equivalent capacitor; under a second state, sequentially sampling and outputting the high-gain reset signal and the high-gain image signal through a second gain output bit line; when the second state is restored to the first state, outputting the low-gain reset signal sampled in the first equivalent capacitor through the first gain output bit line, and then sampling and outputting the low-gain image signal through the first gain output bit line; the high dynamic range of the image sensor is realized, and meanwhile, the cost is reduced and the size of the image sensor is reduced. Because the output of the pixel circuit does not need to be sampled and held to reduce the KT/C noise of the circuit, the noise level of the circuit is lower, and the performance of the image sensor is further improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that need to be called in the embodiments are briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of an image sensor provided in the present application;

FIG. 2 is a circuit schematic diagram of an image sensor provided herein;

fig. 3 is a circuit timing diagram of the image sensor provided in the present application.

Detailed Description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are only for illustration and description purposes and are not used to limit the protection scope of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some of the embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.

In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

As mentioned in the background section, in the prior art, the dual conversion gain mode requires a smaller integration capacitance to increase the gain under low light conditions to increase the sensitivity; under the condition of high illumination, the storage charge is increased by a larger integration capacitor, and the gain is reduced to improve the dynamic range. In a pixel circuit including a dual conversion gain mode, a high-gain reset signal, a high-gain image signal, a low-gain reset signal, and a low-gain image signal are generally sequentially output to a readout circuit at the time of signal readout; therefore, in the prior art, when the readout circuit reads out signals, two or more sets of analog-to-digital conversion circuits are usually required to be designed to quantize the reset signal and the image signal under low gain and the reset signal and the image signal under high gain respectively, so as to ensure the dynamic range of the image sensor; however, the adoption of two or more sets of analog-to-digital conversion circuits requires the adoption of a high dynamic range of multi-frame synthesis, time difference exists in the reading process, the phenomenon of tailing can occur in the finally synthesized image, the reading noise of the circuits is large, and meanwhile, because two or more sets of analog-to-digital conversion circuits actually occupy larger circuit area, under the condition that the pixel functions are gradually enriched, the volume of a photosensitive element is generally increased when an image sensor is designed, and then the adoption of a large-scale analog-to-digital conversion circuit on the basis can cause overlarge circuit area.

In view of the above technical problem, the present application provides an image sensor, which at least includes a pixel circuit 11, a bit line module 12 and a readout circuit 13, and referring to fig. 1 and fig. 2, specifically:

a pixel circuit 11 having two states, in a first state, outputting a low-gain reset signal lcg _ rst or a low-gain image signal lcg _ sig, and in a second state, outputting a high-gain reset signal hcg _ rst or a high-gain image signal hcg _ sig; the pixel circuit 11 is configured to sequentially output a low-gain reset signal lcg _ rst, a high-gain reset signal hcg _ rst, a high-gain image signal hcg _ sig, and a low-gain image signal lcg _ sig;

a bit line module 12 connected to the pixel circuit 11 and including a first gain output bit line Pixout _ l and a second gain output bit line Pixout _ h, where the first gain output bit line Pixout _ l includes a first equivalent capacitor Cbll and the second gain output bit line Pixout _ h includes a second equivalent capacitor Cblh; the bit line module 12 is configured to sample the low gain reset signal lcg _ rst to the first equivalent capacitance Cbll in the first state of the pixel circuit 11; the bit line block 12 is configured to sample and output the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig sequentially through the second gain output bit line Pixout _ h in the second state of the pixel circuit 11, and is configured to output the low-gain reset signal lcg _ rst sampled in the first equivalent capacitor Cbll through the first gain output bit line Pixout _ l and then sample and output the low-gain image signal lcg _ sig through the first gain output bit line Pixout _ l when the pixel circuit 11 returns to the first state after returning from the second state.

It is understood that the first equivalent capacitor Cbll may be the first gain output bit line Pixout _ l itself, either parasitic or having a device capacitance added thereto, a first end of the first equivalent capacitor Cbll being connected to the first gain output bit line Pixout _ l, and a second end of the first equivalent capacitor Cbll being connected to a ground signal; on the one hand, the first equivalent capacitor Cbll is used for sampling the low-gain reset signal lcg _ rst transmitted by the pixel circuit 11, and when the readout circuit 13 is in the working state, the first equivalent capacitor Cbll is directly output to the first gain output bit line Pixout _ l without being turned on again by the pixel circuit 11; on the other hand, the pixel circuit 11 outputs a low-gain image signal lcg _ sig, the low-gain image signal lcg _ sig is transmitted to the first equivalent capacitor Cbll to change the potential thereof, and at this time, the first end and the second end of the first equivalent capacitor Cbll are different in potential, so that charging and discharging are performed, and the low-gain image signal lcg _ sig is output through the first gain output bit line Pixout _ l; it is also understood that the second equivalent capacitor Cblh may be the second gain output bit line Pixout _ l itself, i.e. the second equivalent capacitor Cblh has or is parasitic, or may be added in the form of a device capacitor, a first end of the second equivalent capacitor Cblh is connected to the second gain output bit line Pixout _ h, and a second end of the second equivalent capacitor Cblh is connected to the ground signal; the pixel circuit 11 outputs a high-gain reset signal hcg _ rst and a high-gain image signal hcg _ sig, the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig are transmitted to the second equivalent capacitor Cblh to change the potential of the second equivalent capacitor Cblh, and the first end and the second end of the second equivalent capacitor Cblh are different in potential, so that a discharging operation is performed, and the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig are output through a second gain output bit line Pixout _ h.

The readout circuit 13 is connected to the bit line module 12, the readout circuit 13 has two states, and in the first state, the readout circuit 13 sequentially receives the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig and respectively quantizes the signals to obtain an effective image signal quantized value under high gain; in the second state, the low-gain reset signal lcg _ rst and the low-gain image signal lcg _ sig are sequentially received and quantized to obtain the effective image signal quantization value at low gain.

In the image sensor provided by the present application, the pixel circuit 11 includes a photosensitive element PD, a reset transistor RST, a transmission transistor TX, a source follower transistor SF, a dual conversion gain transistor DCG, and a row selection module, where the row selection module includes a low-gain row selection switch LRS and a high-gain row selection switch HRS, and the low-gain row selection switch LRS and the high-gain row selection switch HRS are connected in parallel.

Optionally, in some embodiments, the pixel circuit 11 further includes a dual conversion gain capacitance Cdcg.

Further, a drain of the reset transistor RST and a drain of the source follower transistor SF are commonly connected to the first power supply PIXVDD, a source of the reset transistor RST is connected to a first end of the dual conversion gain capacitor Cdcg and a drain of the dual conversion gain transistor DCG, a source of the dual conversion gain transistor DCG and a gate of the source follower transistor SF and a source of the transfer transistor TX are commonly connected to the floating diffusion FD, a drain of the transfer transistor TX is connected to a negative electrode of the photosensitive element PD, the source follower transistor SF sequentially amplifies through its source to output a low-gain reset signal lcg _ RST, a high-gain image signal hcg _ sig, a high-gain reset signal hcg _ RST and a low-gain image signal lcg _ sig, a gate of the reset transistor RST is connected to the reset signal RST, a gate of the dual conversion gain transistor DCG is connected to the conversion gain control signal DCG, a gate of the transfer transistor TX is connected to the control signal TX, the second end of the double-conversion gain capacitor Cdcg is connected with a power supply VC, and the anode of the photosensitive element PD is connected with the power supply ground.

A first end of the low-gain row selection switch LRS is connected with the source follower transistor SF, and a second end of the low-gain row selection switch LRS is connected with the first equivalent capacitor Cbll; the low-gain row select switch LRS is controlled by the low-gain row select signal lcg _ rowsel, the low-gain row select switch LRS is turned on under the control of the low-gain row select signal lcg _ rowsel for sampling the low-gain reset signal lcg _ rst to the first equivalent capacitor Cbll in the first state and returning to the first state to be output through the first gain output bitline Pixout _ l in the second state, and for transferring the low-gain image signal lcg _ sig from the pixel circuit 11 to the first equivalent capacitor Cbll and output through the first gain output bitline Pixout _ l after returning to the first state in the second state; a first end of the high-gain row selection switch HRS is connected with the source follower transistor SF, and a second end of the high-gain row selection switch HRS is connected with the second equivalent capacitor Cblh; the high-gain row selection switch HRS is controlled by the high-gain row selection signal hcg _ rowsel, and the high-gain row selection switch HRS is turned on under the control of the high-gain row selection signal hcg _ rowsel, for sequentially transmitting the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig to the second equivalent capacitor Cblh and outputting through the second gain output bit line Pixout _ h in the second state.

The bit line module 12 further includes a source follower current source CC, a low-gain bit line select switch LBS, and a high-gain bit line select switch HBS; a first terminal of the low-gain bitline selection switch LBS is connected to the source follower current source CC, a second terminal of the low-gain bitline selection switch LBS is connected to the first gain output bitline Pixout _ l, in other words, the second terminal of the low-gain line selection switch LRS is connected in series to the first terminal of the first equivalent capacitor Cbll, the low-gain bitline selection switch LBS is controlled by a low-gain bitline selection signal lcg _ bl _ sel, and the low-gain bitline selection switch LBS is used for providing a working current for the first gain output bitline Pixout _ l; a first terminal of the high-gain bitline select switch HBS is connected to the source follower current source CC, a second terminal of the high-gain bitline select switch HBS is connected to the second gain output bitline Pixout _ h, in other words, the second terminal of the high-gain row select switch HRS is connected in series with a first terminal of the second equivalent capacitor Cblh, the high-gain bitline select switch HBS is controlled by a high-gain bitline select signal hcg _ bl _ sel, and the high-gain bitline select switch HBS is used to provide a working current for the second gain output bitline Pixout _ h.

Specifically, as shown in fig. 2, the source follower current source block functions to supply operating currents to the first gain output bitline Pixout _ l and the second gain output bitline Pixout _ h; in the embodiment of the present application, by sequentially turning on and off the low-gain bitline select signal lcg _ bl _ sel and the low-gain row select signal lcg _ rowsel, the high-gain bitline select signal hcg _ bl _ sel and the high-gain row select signal hcg _ rowsel, sampling of the low-gain reset signal lcg _ rst to the first equivalent capacitance Cbll, driving the transfer of the low-gain image signal lcg _ sig to the first gain output bitline Pixout _ l and the transfer of the high-gain image signal hcg _ sig and the high-gain reset signal hcg _ rst to the second gain output bitline Pixout _ h may be accomplished, when the readout circuit 13 is turned on, the first gain output bit line Pixout _ l transmits the low gain reset signal lcg _ rst and the low gain image signal lcg _ sig, and the second gain output bit line Pixout _ h transmits the high gain reset signal hcg _ rst and the high gain image signal hcg _ sig, and the signals are compared and quantized in the readout circuit 13.

The readout circuit 13 includes a gain quantization selection circuit 131, a comparison circuit 132, a counter 133, and a memory 134 which are connected in this order. The gain quantization selection circuit 131 is configured to sequentially switch in the first state the high gain reset signal hcg _ rst and the high gain image signal hcg _ sig to the comparison circuit 132; the gain quantization selection circuit 131 is further configured to sequentially switch in the second state the low gain reset signal lcg _ rst and the low gain image signal lcg _ sig to the comparison circuit 132.

In the first state and the second state of the readout circuit, the comparison circuit 132 compares the ramp voltage vramp as a reference value with the voltage values of the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig, and the low-gain reset signal lcg _ rst and the low-gain image signal lcg _ sig, respectively obtains corresponding comparison results, stores the comparison results in the memory 134 as count results, obtains and outputs a low-gain effective image quantization value and a high-gain effective image quantization value, specifically:

when the readout circuit 13 quantizes the high-gain reset signal hcg _ rst, the comparison circuit 132 is configured to compare the ramp voltage vramp with the high-gain reset signal hcg _ rst and output a first comparison signal; the counter 133 is configured to count when the first comparison signal is received, specifically, the counting direction is downward, and to record the first count result when the ramp voltage vramp and the high-gain reset signal hcg _ rst overlap; when the readout circuit 13 quantizes the high-gain image signal hcg _ sig, the comparison circuit 132 is configured to compare the ramp voltage vramp with the high-gain image signal hcg _ sig, and output a second comparison signal; the counter 133 is configured to count in the opposite direction from the first count result when the second comparison signal is received, specifically, count in the upward direction, and output a second count result when the ramp voltage vramp and the high-gain image signal hcg _ sig overlap, the second count result being a difference between the high-gain image signal hcg _ sig and the quantization result of the high-gain reset signal hcg _ rst; the memory 134 is configured to store the second count result, and to take the second count result as an effective image quantization value at a high gain; when the readout circuit 13 quantizes the low-gain reset signal lcg _ rst, the comparison circuit 132 is configured to compare the ramp voltage vramp with the low-gain reset signal lcg _ rst and output a third comparison signal; the counter 133 is configured to count when the third comparison signal is received, specifically, the counting direction is downward, and to record the third counting result when the ramp voltage vramp and the low-gain reset signal lcg _ rst overlap; when the readout circuit 13 quantizes the low-gain reset signal lcg _ rst, the comparison circuit 132 is configured to compare the ramp voltage vramp with the low-gain image signal lcg _ sig and output a fourth comparison signal; the counter 133 is configured to count in the opposite direction from the third count result when the fourth comparison signal is received, specifically, the count direction is upward, and output a fourth count result when the ramp voltage vramp and the low-gain image signal lcg _ sig overlap, the fourth count result being a difference between the low-gain image signal lcg _ sig and the quantization result of the low-gain reset signal lcg _ rst; the memory 134 is configured to store the fourth count result as an effective image quantization value at a low gain.

The readout circuit 13 includes a comparator, a first capacitor C1, a second capacitor C2, a first clear switch CAZ1, and a second clear switch CAZ 2;

the positive phase input end of the comparator is connected with the ramp voltage vramp through a first capacitor C1, and the negative phase input end of the comparator is connected with the gain quantization selection circuit 131 through a second capacitor C2; the positive phase input end of the comparator is connected with the first end of the first zero clearing switch CAZ1, the negative phase input end of the comparator is connected with the first end of the second zero clearing switch CAZ2, the first positive phase output end of the comparator is connected with the second end of the first zero clearing switch CAZ1, and the first negative phase output end of the comparator is connected with the second end of the second zero clearing switch CAZ 2.

In some embodiments, the comparator comprises a first input Vinp connected to the non-inverting input of the comparator, a second input Vinn connected to the inverting input of the comparator, and a first gain output bit line Vop1 and a second gain output bit line Von1 connected to the first clear switch CAZ1 and the second clear switch CAZ2, respectively, except that in the comparison circuit 132, the comparator is connected to the counter 133 through a third output Vout.

Optionally, the first capacitor C1 is a variable capacitor, and adjusting the variable capacitor can further improve the circuit gain.

Optionally, the slope of the ramp voltage vramp is adjustable; especially, in the process of quantizing the output of the pixel circuit 11, the slopes of the low-gain down-ramp voltage and the high-gain down-ramp voltage thereof may be set to be different, and thus the circuit gain may be further increased, thereby further increasing the dynamic range of the image sensor.

The gain quantization selection circuit 131 further includes a high gain quantization switch HEN and a low gain quantization switch LEN; the high-gain quantization switch HEN is controlled by a high-gain quantization switch signal hcg _ en, and a first end of the high-gain quantization switch HEN is connected to a second gain output bit line Pixout _ h to serve as a high-gain reset signal hcg _ rst input end of the readout circuit 13 and a high-gain image signal hcg _ sig input end of the readout circuit 13; the low-gain quantization switch LEN is controlled by a low-gain quantization switch signal lcg _ en, and a first end of the low-gain quantization switch LEN is connected to a first gain output bit line Pixout _ l to serve as a low-gain reset signal lcg _ rst input end of the readout circuit 13 and a low-gain image signal lcg _ sig input end of the readout circuit 13; the second terminal of the high-gain quantization switch HEN and the second terminal of the low-gain quantization switch LEN are connected in parallel to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the inverting input terminal of the comparator.

It will be appreciated that the high gain quantization switch HEN receiving the high gain quantization switch signal hcg _ en and the low gain quantization switch LEN receiving the low gain quantization switch signal lcg _ en in the readout circuit 13 connect the second gain output bitline Pixout _ h and the first gain output bitline Pixout _ l, respectively, to the second capacitor C2 at different times, thereby coupling the high gain reset signal hcg _ rst and the high gain image signal hcg _ sig, respectively, to the inverting input of the comparison circuit 132 via the second gain output bitline Pixout _ h and the second capacitor C2, and coupling the low gain reset signal lcg _ rst and the low gain image signal lcg _ sig to the inverting input of the comparison circuit 132 via the first gain output bitline Pixout _ l and the second capacitor C2.

It can be understood that the low-gain bit line select switch LBS, the high-gain bit line select switch HBS, the low-gain row select switch LRS, the high-gain row select switch HRS, the high-gain quantization switch HEN, the low-gain quantization switch LEN, the first clear switch CAZ1, and the second clear switch CAZ2 are all fully-controlled switch devices, and as an optional implementation, may also be MOS transistors, and the present application does not specifically limit the switch types.

As shown in fig. 2, it can be understood that each column of pixel cells includes two output bit lines, a first output bit line Pixout _ l and a second output bit line Pixout _ h.

Besides, the present application also provides an operating method of an image sensor, which is applied to the image sensor, fig. 3 is a timing control diagram of the image sensor in fig. 2, and the following detailed description is provided:

inputting the low-gain row selection signal lcg _ rowsel and the low-gain bit line selection signal lcg _ bl _ sel, turning on the low-gain row selection switch LRS and the low-gain bit line selection switch LBS, sampling the low-gain reset signal lcg _ rst output by the pixel circuit 11 to the first equivalent capacitance Cbll of the first output bit line Pixout _ l, refer to fig. 3:

at the time of t0, the reset signal rst is set to be at a low level, the low-gain row selection signal lcg _ rowsel is set to be at a high level, the low-gain bit line selection signal lcg _ bl _ sel is set to be at a high level, the first gain output bit line Pixout _ l, the source follower transistor SF and the source follower current source CC are switched on, and the low-gain reset signal lcg _ rst is obtained;

at time t1, the low-gain bit line select signal lcg _ bl _ sel is set to low level, and the first gain output bit line Pixout _ l, the source follower transistor SF, and the source follower current source CC are disconnected;

at time t2, the low-gain row select signal lcg _ rowsel is asserted low, and the low-gain reset signal lcg _ rst is sampled onto the first gain output bit line Pixout _ l equivalent capacitor, i.e., the first equivalent capacitor Cbll.

A high-gain row select signal hcg _ rowsel and a high-gain bit line select signal hcg _ bl _ sel are input, the high-gain row select switch HRS and the high-gain bit line select switch HBS are turned on, and a high-gain reset signal hcg _ rst and a high-gain image signal hcg _ sig output from the pixel circuit 11 are transmitted to the second gain output bit line Pixout _ h and output.

Specifically, the signal is transmitted to the second equivalent capacitor Cblh first, and then is connected to the second gain output bit line Pixout _ h for output; the first zero clearing switch CAZ1 and the second zero clearing switch CAZ2 are switched on, and zero clearing and resetting are carried out on the comparator; the readout circuit 13 quantizes the high gain reset signal hcg _ rst, with reference to fig. 3:

at time t3, setting a high-gain row selection signal hcg _ rowsel to be at a high level, conducting a high-gain row selection switch HRS, setting a high-gain bit line selection signal hcg _ bl _ sel to be at a high level, conducting a high-gain bit line selection switch HBS, switching on a second gain output bit line Pixout _ h, a source follower transistor SF and a source follower current source CC, switching in a comparator clear signal cmp _ az, switching on a first clear switch CAZ1 and a second clear switch CAZ2, shorting a first input end Vinp and a first gain output bit line Vop1 of a comparator together, shorting a second input end Vinn and a second gain output bit line Von1 together, and clearing the comparator clear signal cmp _ az to the comparator; the dual conversion gain signal DCG is asserted high, the dual conversion gain transistor DCG is turned on, and the second gain output bitline Pixout _ h receives the high gain reset signal hcg _ rst.

At time t4, the high-gain quantization switch signal hcg _ en is set to high level, and the high-gain quantization switch HEN is turned on, so that the second gain output bit line Pixout _ h is connected to the comparator;

at time t5, the comparator clear switch signal cmp _ az is turned off, and the first clear switch CAZ1 and the second clear switch CAZ2 are turned off.

The ramp voltage vramp is connected to the positive phase input end of the comparator, a high gain quantization switch signal hcg _ en is input, the high gain quantization switch HEN is turned on, a high gain reset signal hcg _ rst is coupled to the inverting input end of the comparator through a second capacitor C2, and the readout circuit 13 quantizes the high gain reset signal hcg _ rst to obtain a high gain reset signal quantization value; specifically, during the quantization of the high-gain reset signal lcg _ rst, the ramp voltage vramp decreases, the comparison circuit 132 compares the ramp voltage vramp with the high-gain reset signal hcg _ rst, and outputs a first comparison signal; the counter 133 starts counting, and when the ramp voltage vramp and the high-gain reset signal hcg _ rst overlap, records a first counting result, resets the ramp voltage vramp, and outputs a high-gain reset signal hcg _ rst; referring to FIG. 3:

at time t6, the ramp voltage vramp starts to fall, the comparison circuit 132 compares the ramp voltage vramp with the high-gain reset signal hcg _ rst, and outputs a first comparison signal; the count enable signal count _ en of the counter 133 counts when receiving the first comparison signal, records the first count result when the ramp voltage vramp and the high-gain reset signal hcg _ rst overlap, and outputs the high-gain reset signal hcg _ rst.

Specifically, the ramp voltage vramp and the second gain output bit line Pixout _ h are respectively coupled to positive input terminals of comparators of the comparators through capacitors, and respectively correspond to first input terminals Vinp and second input terminals Vinn of the comparators, when the first input terminals Vinp and the second input terminals Vinn are overlapped, the comparators output 0, and at this time, the counter 133 stops counting, and obtains the reset signal at high gain.

At time t7, the high-gain reset signal hcg _ rst is quantized to the end, and the ramp voltage vramp is reset.

Inputting a high-gain row selection signal hcg _ rowsel and a high-gain bit line selection signal hcg _ bl _ sel, turning on a low-gain row selection switch HRS and a low-gain bit line selection switch HBS, and transmitting and outputting a high-gain image signal hcg _ sig output by the pixel circuit to a second gain output bit line Pixout _ h;

the ramp voltage vramp is connected to a positive input end of the comparator, a high-gain quantization switch signal hcg _ en is input, the high-gain quantization switch HEN is turned on, the high-gain image signal hcg _ sig is coupled to an inverting input end of the comparator through a second capacitor C2, the readout circuit 13 quantizes the high-gain image signal hcg _ sig to obtain a difference value between a high-gain reset signal quantization value and a high-gain image signal quantization value, and the high-gain effective image quantization value is obtained.

Specifically, in the step of quantizing the high-gain image signal hcg _ sig, the ramp voltage vramp falls, the comparison circuit 132 compares the ramp voltage vramp with the high-gain image signal hcg _ sig, and outputs a second comparison signal; the counter 133 counts in the opposite direction from the first count result when receiving the second comparison signal, and records the second count result, which is the difference between the quantization result of the high-gain reset signal hcg _ rst and the quantization result of the high-gain image signal hcg _ sig, and resets the ramp voltage vramp when the ramp voltage vramp overlaps with the high-gain image signal hcg _ sig; configured by the memory 134 to store the second count result as a high gain effective image quantization value; referring to fig. 3:

at the time point t 8-t 9, the transmission control signal TX is set to be at a high level, the transmission transistor TX is turned on, the image signal starts to be transmitted, the second gain output bit line Pixout _ h is coupled to the second input terminal Vinn of the comparator through the second capacitor C2, the image signal is transmitted to the comparator, and the high-gain image signal hcg _ sig is obtained;

at time t10, when the ramp voltage vramp drops again, the comparison circuit 132 compares the ramp voltage vramp with the high-gain image signal hcg _ sig and outputs a second comparison signal; when the count enable count _ en is switched in, that is, when a second comparison signal is received, the counter 133 counts in the opposite direction from the first count result, the ramp voltage vramp and the second gain output bit line Pixout _ h are coupled to the first input terminal Vinp and the second input terminal Vinn of the comparator through the first capacitor C1 and the second capacitor C2, respectively, when the first input terminal Vinp and the second input terminal Vinn overlap, the comparator outputs 0, and at this time, the counter 133 stops counting to obtain a second count result; the memory 134 stores the second count result, and obtains the difference between the image signal and the reset signal at high gain, which is the high gain effective image quantization value;

at time t11, high-gain image signal hcg _ sig is quantized to the end, and ramp voltage vramp is reset and starts returning to the reference state.

At time t12, the high-gain row select signal hcg _ rowsel is set to low level, the high-gain row select switch HRS is turned off, the high-gain bitline select signal hcg _ bl _ sel is set to low level, the high-gain bitline select switch HBS is turned off, the high-gain quantization switch signal hcg _ en is set to low level, the high-gain quantization switch HEN is turned off, the second gain output bitline Pixout _ h, the source follower transistor SF, and the source follower current source CC are turned off, and the second gain output bitline Pixout _ h is turned off from the comparator.

Since the low-gain reset signal lcg _ rst is sampled onto the first gain output bit line Pixout _ l equivalent capacitor, i.e., the first equivalent capacitor Cbll, at time t2, when the low-gain reset signal lcg _ rst is quantized, the low-gain reset signal lcg _ rst is output through the first gain output bit line Pixout _ l by discharging the first equivalent capacitor Cbll when the switch control circuit 13 is turned on. After the low gain quantization switch LEN is turned on and the comparator is cleared and reset for inputting the low gain quantization switch signal lcg _ en, the low gain reset signal lcg _ rst is coupled to the inverting input terminal of the comparator through the second capacitor C2, with reference to fig. 3:

at the time of t13, setting a double-conversion gain signal DCG to be at a high level, turning on a double-conversion gain transistor DCG, turning on a zero clearing switch signal cmp _ az of an access comparator, turning on a first zero clearing switch CAZ1 and a second zero clearing switch CAZ2, short-circuiting a first input end Vinp of the comparator and a first gain output bit line Vop1 together, short-circuiting a second input end Vinn of the comparator and a second gain output bit line Von1 together, and resetting the comparator in a zero clearing mode;

at time t14, the low-gain quantization switch signal lcg _ en is set to a high level, the low-gain quantization switch LEN is turned on, and the equivalent capacitance of the first gain output bit line Pixout _ l, i.e., the low-gain reset signal lcg _ rst stored in the first equivalent capacitance Cbll, is coupled to the second input terminal Vinn of the comparator through the second capacitor C2.

At time t15, the comparator clear switch signal cmp _ az is turned off, and the first clear switch CAZ1 and the second clear switch CAZ2 are turned off.

The ramp voltage vramp is connected to the non-inverting input terminal of the comparator, and the readout circuit 13 quantizes the low-gain reset signal lcg _ rst to obtain a quantized value of the low-gain reset signal. Specifically, during the quantization of the low-gain reset signal lcg _ rst, the ramp voltage vramp falls, the comparison circuit 132 compares the ramp voltage vramp with the low-gain reset signal lcg _ rst, and outputs a third comparison signal; the counter 133 counts when receiving the third comparison signal, and records the third count result and resets the ramp voltage vramp when the ramp voltage vramp and the low-gain reset signal lcg _ rst overlap. Referring to fig. 3:

at time t16, the ramp voltage vramp starts to fall, the comparison circuit 132 compares the ramp voltage vramp with the low-gain reset signal lcg _ rst, and outputs a third comparison signal; the counter 133 starts counting when the count enable signal count _ en is accessed; the ramp voltage vramp and the first gain output bit line Pixout _ l are coupled to a first input end Vinp and a second input end Vinn of the comparator through a first capacitor C1 and a second capacitor C2, respectively, when the first input end Vinp and the second input end Vinn are overlapped, the comparator outputs 0, at this time, the counter 133 stops counting, a third counting result is obtained, and a low gain reset signal lcg _ rst is obtained;

at time t17, the low-gain reset signal lcg _ rst is quantized, and the ramp voltage vramp is reset and returns to the reference state;

inputting a low-gain row selection signal lcg _ rowsel and a low-gain bit line selection signal lcg _ bl _ sel, turning on a low-gain row selection switch LRS and a low-gain output selection transistor LBS, transmitting a low-gain image signal lcg _ sig to a first gain output bit line Pixout _ l for sampling and outputting; the ramp voltage vramp is connected to a positive phase input end of the comparator, a low gain quantization switch signal lcg _ en is input, a low gain quantization switch LEN is turned on, a low gain image signal lcg _ sig is coupled to an inverting input end of the comparator through a second capacitor C2, the readout circuit 13 quantizes the low gain image signal lcg _ sig to obtain a difference value between a low gain reset signal quantization value and a low gain image signal quantization value, and a low gain effective image quantization value is obtained. Specifically, in the quantization step of the low-gain image signal lcg _ sig, the ramp voltage vramp falls again, the comparison circuit 132 compares the ramp voltage vramp with the low-gain image signal lcg _ sig, and outputs a fourth comparison signal; the counter 133 counts in the opposite direction from the third count result when receiving the fourth comparison signal, and when the ramp voltage vramp overlaps the high-gain image signal hcg _ sig, records the fourth count result, which is the difference between the quantization result of the high-gain reset signal hcg _ rst and the quantization result of the high-gain image signal hcg _ sig, and resets the ramp voltage vramp. Referring to fig. 3:

at time t18, the low-gain row select signal lcg _ rowsel is set to high, the low-gain row select switch LRS is turned on, the low-gain bitline select signal lcg _ bl _ sel is set to high, the low-gain output select transistor LBS is turned on, and the first gain output bitline Pixout _ l and the source follower current source CC are turned on.

At the time point t19 to t20, the transmission control signal TX is set to a high level, the transmission transistor TX is turned on, the image signal starts to be transmitted, and the first gain output bit line Pixout _ l is coupled to the second input terminal Vinn of the comparator through the second capacitor C2, so as to obtain the low-gain image signal lcg _ sig.

At time t21, when the ramp voltage vramp drops again, the comparison circuit 132 compares the ramp voltage vramp with the low-gain image signal lcg _ sig and outputs a fourth comparison signal; when the count enable signal count _ en is turned on, the counter 133 counts in the opposite direction from the third count result, the ramp voltage vramp and the first gain output bit line Pixout _ l are respectively coupled to the first input terminal Vinp and the second input terminal Vinn of the comparator through the first capacitor C1 and the second capacitor C2, when the ramp voltage vramp and the high-gain image signal hcg _ sig overlap, in other words, the first input terminal Vinp and the second input terminal Vinn overlap, the comparator outputs 0, at which time the counter 133 stops counting, and the memory 134 stores the fourth count result, so as to obtain a difference between the image signal at low gain and the reset signal, which is a related effective image quantization value at low gain;

at time t22, low-gain image signal lcg _ sig ends quantization, and ramp voltage vramp resets and returns to the reference state.

In the working method of the image sensor provided by the application, in one quantization period, the low-gain reset signal lcg _ rst, the high-gain reset signal hcg _ rst, the high-gain image signal hcg _ sig and the low-gain image signal lcg _ sig are sequentially read, and an analog-to-digital conversion circuit in the readout circuit performs quantization processing on the signals so as to achieve high dynamic range output of the image sensor.

Besides, the application also provides an electronic device comprising the image sensor.

In summary, in the image sensor and the electronic device provided by the present application, the bit line module 12 is arranged, and in the first state, the low-gain reset signal lcg _ rst is sampled to the first equivalent capacitor Cbll; in a second state, the high-gain reset signal hcg _ rst and the high-gain image signal hcg _ sig are sequentially sampled and output by a second gain output bit line Pixout _ h; when the second state is restored to the first state after the second state, outputting the low-gain reset signal lcg _ rst sampled in the first equivalent capacitor Cbll through the first gain output bit line Pixout _ l, and then sampling and outputting the low-gain image signal lcg _ sig through the first gain output bit line Pixout _ l; meanwhile, the bit line module 12 is connected to a matched reading circuit 13, so that effective image quantization is realized; the high dynamic range of the image sensor is realized, and meanwhile, the cost is reduced and the size of the image sensor is reduced. Since the output of the pixel circuit does not need to be sampled and held to reduce the KT/C noise of the circuit, the noise level of the circuit is lower, and the performance of the image sensor is further improved.

The embodiments described above are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the application, but is merely representative of selected embodiments of the application. Based on this, the protection scope of the present application shall be subject to the protection scope of the claims. Moreover, all other embodiments that can be made by a person skilled in the art based on the embodiments of the present application without making creative efforts shall fall within the protection scope of the present application.

Claims (10)

1. An image sensor, comprising:

a pixel circuit having two states, in a first state, outputting a low-gain reset signal or a low-gain image signal, and in a second state, outputting a high-gain reset signal or a high-gain image signal; the pixel circuit is configured to sequentially output a low-gain reset signal, a high-gain image signal, and a low-gain image signal;

the bit line module is connected with the pixel circuit and comprises a first gain output bit line and a second gain output bit line, the first gain output bit line comprises a first equivalent capacitor, and the second gain output bit line comprises a second equivalent capacitor; the bit line module is configured to sample the low-gain reset signal to the first equivalent capacitor in a first state of the pixel circuit, sequentially sample and output the high-gain reset signal and the high-gain image signal through the second gain output bit line in a second state of the pixel circuit, output the low-gain reset signal sampled in the first equivalent capacitor through the first gain output bit line when the pixel circuit is restored from the second state to the first state, and then sample and output the low-gain image signal through the first gain output bit line;

the reading circuit is connected with the bit line module, has two states, and sequentially receives the high-gain reset signal and the high-gain image signal and respectively quantizes the high-gain reset signal and the high-gain image signal to obtain an effective image signal quantization value under high gain in the first state; and in the second state, the low-gain reset signal and the low-gain image signal are sequentially received and respectively quantized to obtain an effective image signal quantization value under low gain.

2. The image sensor of claim 1, wherein the pixel circuit comprises a photosensitive element, a reset transistor, a transfer transistor, a source follower transistor, a dual conversion gain transistor, and a row select module, the row select module comprises a low-gain row select switch, a high-gain row select switch, and the low-gain row select switch and the high-gain row select switch are connected in parallel;

the first end of the low-gain row selection switch is connected with the output end of the source electrode following transistor, and the second end of the low-gain row selection switch is connected with the first equivalent capacitor; the low-gain row selection switch is used for sampling the low-gain reset signal to the first equivalent capacitor in a first state of the pixel circuit and outputting the low-gain reset signal through the first gain output bit line when the pixel circuit is restored to the first state from a second state, and transmitting the low-gain image signal from the pixel circuit to the first equivalent capacitor and outputting the low-gain image signal through the first gain output bit line after the pixel circuit is restored to the first state from the second state;

the first end of the high-gain row selection switch is connected with the output end of the source follower transistor, and the second end of the high-gain row selection switch is connected with the second equivalent capacitor; the high-gain row selection switch is used for sequentially transmitting the high-gain reset signal and the high-gain image signal to the second equivalent capacitor in a second state of the pixel circuit and outputting the signals through a second gain output bit line.

3. The image sensor of claim 1, wherein the bitline module further comprises a source-follower current source, a low-gain bitline select switch, and a high-gain bitline select switch;

a first end of the low-gain bit line selection switch is connected to the source electrode following current source, a second end of the low-gain bit line selection switch is connected to the first gain output bit line, and the low-gain bit line selection switch is used for selecting the source electrode following current source to provide working current for the first gain output bit line;

the first end of the high-gain bit line selection switch is connected to the source electrode following current source, the second end of the high-gain bit line selection switch is connected to the second gain output bit line, and the high-gain bit line selection switch is used for selecting the source electrode following current source to provide working current for the second gain output bit line.

4. The image sensor of claim 1, wherein the readout circuit comprises a gain quantization selection circuit, a comparison circuit, a counter, and a memory connected in sequence, the gain quantization selection circuit configured to sequentially switch in the high gain reset signal and the high gain image signal to the comparison circuit in a first state of the readout circuit; the gain quantization selection circuit is further configured to sequentially switch in the low gain reset signal and the low gain image signal to the comparison circuit in a second state of the readout circuit.

5. The image sensor of claim 4, wherein when the readout circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare a ramp voltage and the high-gain reset signal and output a first comparison signal; the counter is configured to count when the first comparison signal is received and record a first count result when the ramp voltage and the high-gain reset signal overlap;

when the readout circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter is configured to count in an opposite direction from the first count result when the second comparison signal is received, and output a second count result when the ramp voltage and the high-gain image signal overlap, the second count result being a difference between a high-gain image signal quantization result and a high-gain reset signal quantization result;

the memory is configured to store the second count result and to use the second count result as an effective image quantization value at the high gain;

when the readout circuit quantizes the low-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the low-gain reset signal and output a third comparison signal; the counter is configured to count when the third comparison signal is received and record a third counting result when the ramp voltage and the low-gain reset signal overlap;

when the readout circuit quantizes the low-gain image signal, the comparison circuit is configured to compare the ramp voltage and the low-gain image signal and output a fourth comparison signal; the counter is configured to count in an opposite direction from the third count result when the fourth comparison signal is received, and output a fourth count result when the ramp voltage and the low-gain image signal overlap, the fourth count result being a difference between a low-gain image signal quantization result and a low-gain reset signal quantization result;

the memory is configured to store the fourth count result and to use the fourth count result as an effective image quantization value at the low gain.

6. The image sensor of claim 4, wherein the comparison circuit comprises a comparator, a first capacitor, a second capacitor, a first clear switch, and a second clear switch;

a positive phase input end of the comparator is connected to a ramp voltage through the first capacitor, and an inverted phase input end of the comparator is connected to the gain quantization selection circuit through the second capacitor;

the positive phase input end of the comparator is connected with the first end of the first zero clearing switch, and the negative phase input end of the comparator is connected with the first end of the second zero clearing switch; and the positive phase output end of the comparator is connected with the second end of the first zero clearing switch, and the first reverse phase output end of the comparator is connected with the second end of the second zero clearing switch.

7. The image sensor of claim 6, wherein the first capacitance is a variable capacitance.

8. The image sensor of claim 6, wherein a slope of the ramp voltage is adjustable.

9. The image sensor of claim 6, wherein the gain quantization selection circuit comprises a high gain quantization switch and a low gain quantization switch;

a first end of the high-gain quantization switch is connected to the second gain output bit line to serve as a high-gain reset signal input end of the gain quantization selection circuit and a high-gain image signal input end of the gain quantization selection circuit;

a first end of the low-gain quantization switch is connected to the first gain output bit line to serve as a low-gain reset signal input end of the gain quantization selection circuit and a low-gain image signal input end of the gain quantization selection circuit;

the second end of the high-gain quantization switch and the second end of the low-gain quantization switch are connected with the first end of the second capacitor in parallel, and the second end of the second capacitor is connected with the inverting input end of the comparator.

10. An electronic device, characterized in that it comprises an image sensor according to any one of claims 1-9.

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