CN111935427B

CN111935427B - CMOS image sensor, pixel unit and control method thereof

Info

Publication number: CN111935427B
Application number: CN202010888334.2A
Authority: CN
Inventors: 王林; 胡万景; 黄金德
Original assignee: Rockchip Electronics Co Ltd
Current assignee: Rockchip Electronics Co Ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2022-08-19
Anticipated expiration: 2040-08-28
Also published as: CN111935427A

Abstract

The embodiment of the invention provides a CMOS image sensor, a pixel unit and a control method thereof, wherein the pixel unit comprises a global exposure structure and an extension structure, the global exposure structure is suitable for outputting a first frame of analog signals, the extension structure is suitable for being coupled with the global exposure structure to output a second frame of analog signals, the extension structure comprises a first control transistor, a third capacitor, a second control transistor, a fourth capacitor, a third control transistor and a fifth capacitor, the storage capacity of the third capacitor is larger than that of a first storage node, the full-well capacity of a pixel is not limited by a full-well of a photodiode through a transverse overflow accumulation capacitor, and the third capacitor is selectively connected with the first storage node in parallel by combining with the first control transistor.

Description

CMOS image sensor, pixel unit and control method thereof

Technical Field

The invention relates to the technical field of sensors, in particular to a CMOS image sensor, a pixel unit and a control method thereof.

Background

An image sensor is a semiconductor device that converts an optical signal into an electrical signal. Image sensors are classified into two major types, Complementary Metal Oxide Semiconductor (CMOS) image sensors and Charge Coupled Device (CCD) image sensors. Since the CMOS image sensor has advantages of low power consumption, low cost, and easy integration of other devices, it has been widely used in still digital cameras, digital video cameras, medical imaging devices, vehicle imaging devices, and the like.

The dynamic range of an image sensor is an important index parameter of the image sensor. The dynamic range represents the range of the maximum intensity signal and the minimum intensity signal that the image sensor can detect in the same image at the same time. Generally expressed in dB, the formula is as follows:

wherein P is _max Indicating a maximum detectable intensity, P _min Indicating a minimum intensity of light that can be detected. The dynamic range of a general image sensor is between 60-70dB, the dynamic range of human eyes is between 100-120dB, and a high dynamic range image sensor is very important for considering both dark details and bright details.

The Full Well Capacity (FWC) of an image sensor refers to the maximum number of electrons that a pixel can collect and hold. For a typical linear response image sensor, the maximum detectable intensity corresponds to the full well capacity and the minimum intensity corresponds to the number of image noise electrons, so the dynamic range can also be expressed in terms of the full well capacity/noise electrons. Generally, the larger the full well of the image sensor, the higher the dynamic range.

The pixel unit of the CMOS image sensor generally includes one photodiode and a plurality of transistors, and the global exposure structure of the pixel unit of the CMOS image sensor includes a 5-transistor (5T) type, an 8-transistor (8T) type, a 9-transistor (9T) type, and the like, according to the number of transistors included in the pixel unit of the CMOS image sensor.

As shown in fig. 1, a pixel unit of a 5T-type global exposure CMOS image sensor includes an Anti-Blooming transistor (Anti-Blooming), a transfer transistor TX, a reset transistor RST, a source follower transistor sf (source follower), a row selection transistor SEL, and 5 transistors in total, and further includes a photodiode ppd (pinned photodiode), and a storage node FD.

There are technical drawbacks to a pixel cell that includes a 5T global exposure structure. For example, the parasitic light sensation effect is large. The pixel unit of the 5T global exposure structure uses an FD point as a signal temporary storage node, the node is usually a PN junction, and metal is covered on the node to reduce parasitic light sensation effect. The node is close to PPD, and if the metal covered area is too large, the node can cover the normal photosensitive PPD, so that the photosensitive effect of the PPD is influenced; the pixel unit of the 5T global exposure structure reads the reset analog signal firstly and then reads the exposure analog signal, and the two times of sampling are not related sampling, so that the related double sampling cannot be realized, so that the reset noise cannot be eliminated by subtracting, and the noise of an output image is very large.

In order to overcome the technical drawbacks described above, the prior art provides a global exposure structure including two stages of source followers (i.e., a first stage source follower and a second stage source follower), the global exposure structure further including a photoelectric conversion element, a transfer transistor, a reset transistor, a storage node FD, a first capacitor, and a second capacitor. This global exposure structure can realize correlated double sampling, that is, after the pixel unit is exposed, the reset level of the storage node FD is read out, the sampling level of the storage node FD is read out, after quantization, the reset quantized data and the sampled quantized data are subtracted, and since the reset noise generated by two times of sampling is correlated, the reset noise can be eliminated.

The global exposure structure having the two-stage source follower includes an 8T type global exposure structure (which has 8 transistors), a 9T type global exposure structure (which has 9 transistors), and the like.

As shown in fig. 2, the pixel unit of the 9T-type global exposure structure is composed of 9 transistors, including a transmission transistor TX, a reset transistor RST, a first-stage source follower transistor SF1, a second-stage source follower transistor SF2, an isolation transistor AMS, a discharge transistor Bias, switching transistors SWR and SWS, and a row selection transistor SEL, and further includes a photodiode PPD and two sampling capacitors Cr and Cs.

However, the pixel cells of the existing global exposure architecture do not have a high dynamic range.

Disclosure of Invention

The invention solves the technical problem of how to improve the dynamic range of the pixel unit of the global exposure structure.

To solve the above technical problem, an embodiment of the present invention provides a pixel unit of a CMOS image sensor, including a global exposure structure adapted to output an analog signal of a first frame, including a photoelectric conversion element, a transfer transistor, a first storage node, a second storage node, a first capacitor, and a second capacitor, the pixel unit further including: the extension structure is suitable for being coupled with the global exposure structure to output a second frame of analog signals and comprises a first control transistor, a third capacitor, a second control transistor, a fourth capacitor, a third control transistor and a fifth capacitor, wherein the first end of the first control transistor is coupled with the first end of the third capacitor, and the second end of the first control transistor is coupled with the first storage node; the second end of the third capacitor is coupled with a first power line, the first end of the fourth capacitor is coupled with the second end of the second control transistor, the second end of the fourth capacitor is coupled with the first power line, the first end of the fifth capacitor is coupled with the second end of the third control transistor, the second end of the fifth capacitor is coupled with the first power line, the first ends of the second control transistor and the third control transistor are both coupled with the second storage node, and the first power line is a power line for providing a common ground voltage; the storage capacity of the third capacitor is larger than that of the first storage node, and the first control transistor enables the third capacitor to be selectively connected with the first storage node in parallel.

Optionally, the storage capacity of the third capacitor is N times the storage capacity of the first storage node, where N is an integer greater than or equal to 8.

Optionally, a control module is included that is adapted to control the turning on or off of the first control transistor to control the storage of charge collected during exposure onto the first storage node, or onto the first storage node and the third capacitance.

Optionally, the global exposure structure is a 9T-type global exposure structure, which further includes: a reset transistor, a first stage source follower, an isolation transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a second stage source follower, and a row selection transistor, wherein the anode terminal of the photoelectric conversion element is coupled to a first power line, the cathode terminal is coupled to the first terminal of the transmission transistor, the second terminal of the transmission transistor is coupled to the second terminal of the first control transistor, the first terminal of the reset transistor is coupled to a second power line, the second terminal is coupled to the first terminal of a third capacitor, the gate of the first stage source follower is coupled to a first storage node, the first terminal is coupled to the second power line, the first terminal of the isolation transistor is coupled to the second terminal of the first stage source follower, the first terminal of the fourth control transistor is coupled to the second storage node, the second terminal is coupled to the first power line, the first terminal of the fifth control transistor is coupled to the second storage node, the second terminal is coupled to the first terminal of the first capacitor, the second end of the first capacitor is coupled to a first power line, the first end of the sixth control transistor is coupled to the second storage node, the second end of the sixth control transistor is coupled to the first end of the second capacitor, the second end of the second capacitor is coupled to the first power line, the gate of the second stage source follower is coupled to the second storage node, the first end of the second stage source follower is coupled to the second power line, the first end of the row selection transistor is coupled to the second end of the second stage source follower, the second end of the row selection transistor is coupled to a bit line of the pixel unit, and the second power line is a power line for providing working voltage for the pixel unit.

Optionally, the pixel unit further comprises a quantization structure adapted to receive the first frame analog signal, quantize the first frame analog signal and obtain first frame quantized data based on the quantized first frame analog signal, receive the second frame analog signal, quantize the second frame analog signal and obtain second frame quantized data based on the quantized second frame analog signal, and add the first frame quantized data and the second frame quantized data to obtain final quantized data.

Optionally, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal, and the quantization structure includes: a first quantization sub-module adapted to quantize the first frame reset analog signal to obtain first frame reset quantized data, quantize the first frame exposure analog signal to obtain first frame exposure quantized data, subtract the first frame reset quantized data and the first frame exposure quantized data to obtain first frame quantized data; a second quantization sub-module adapted to quantize the second frame reset analog signal to obtain second frame reset quantized data, quantize the second frame exposure analog signal to obtain second frame exposure quantized data, subtract the second frame reset quantized data and the second frame exposure quantized data to obtain second frame quantized data; a processing sub-module adapted to add the first frame quantized data and the second frame quantized data to obtain final quantized data.

The embodiment of the invention also provides a method for controlling the pixel unit, which comprises the following steps: setting gate control signals of a reset transistor and a transfer transistor to a high level to reset the first storage node and the photoelectric conversion element; setting gate control signals of a reset transistor and a transmission transistor to be low level so as to enable the pixel unit to start exposure; setting a grid control signal of the first control transistor to be high level, and enabling the charges to flow to the first storage node and the third capacitor through the transmission transistor after the photoelectric conversion element is filled with the charges; after exposure is finished, setting grid control signals of the isolation transistor and the fourth control transistor to be high level; setting a gate control signal of the first control transistor to a low level, setting a gate control signal of the fifth control transistor to a high level, charging the first capacitor, and then setting the gate control signal of the fifth control transistor to a low level while storing the reset analog signal of the first frame on the first capacitor; setting a gate control signal of the transfer transistor to a high level, transferring charges collected during exposure from the photoelectric conversion element onto the first storage node, and setting the gate control signal of the transfer transistor to a low level after the transfer is completed; setting a grid control signal of a sixth control transistor to be at a high level, charging a second capacitor, and setting the grid control signal of the sixth control transistor to be at a low level after the signal is established so as to store the exposure analog signal of the first frame on the second capacitor; setting gate control signals of the first control transistor and the transmission transistor to be high level so as to transfer charges remaining in the photoelectric conversion element to the first storage node and the third capacitor; setting a grid control signal of a third control transistor to be at a high level, charging a fifth capacitor, and setting the grid control signal of the third control transistor to be at a low level after the signal is established so as to store a second frame exposure analog signal on the fifth capacitor; the gate control signal of the reset transistor is set to a high level to reset the first storage node and the third capacitor, the second control transistor gate control signal is set to a high level to charge the fourth capacitor, and then the second control transistor gate control signal is set to a low level to store the reset analog signal of the second frame on the fourth capacitor of the capacitor.

Optionally, setting the gate control signals of the first control transistor, the isolation transistor and the fourth control transistor to be at a low level to start entering a row-by-row readout stage; setting a grid control signal of a row selection transistor to be high level, setting a grid control signal of a fourth control transistor to be high level, then setting the grid control signal to be low level again to empty a second storage node, then setting a grid control signal of a fifth control transistor to be high level, and transmitting a first frame of reset analog signals of the second storage node to a bit line by a second-stage source follower to sample the first frame of reset analog signals; setting a gate control signal of the fourth control transistor to a high level, and then to a low level to reset the second storage node, and then setting a gate control signal of the sixth control transistor to a high level, the second stage source follower transferring an exposure analog signal of a first frame of the second storage node onto the bit line to sample the exposure analog signal of the first frame, and then setting the gate control signal of the sixth control transistor to a low level; setting a gate control signal of the fourth control transistor to a high level and then to a low level to reset the second storage node, and then setting a gate control signal of the second control transistor to a high level, the second stage source follower transferring a reset analog signal of a second frame of the second storage node onto the bit line to sample the reset analog signal of the second frame, and then setting the gate control signal of the second control transistor to a low level; the gate control signal of the fourth control transistor is set to a high level, then set to a low level to reset the second storage node, then the gate control signal of the third control transistor is set to a high level, the second stage source follower transmits the second frame exposure analog signal of the second storage node onto the bit line to sample the exposure analog signal of the second frame, and then the gate control signal of the third control transistor is set to a low level.

Alternatively, the first frame reset quantized data is obtained by quantizing the first frame reset analog signal, the first frame exposure quantized data is obtained by quantizing the first frame exposure analog signal, and the first frame exposure quantized data is obtained by subtracting the first frame reset quantized data and the first frame exposure quantized data; quantizing the second frame reset analog signal to obtain second frame reset quantized data, quantizing the second frame exposure analog signal to obtain second frame exposure quantized data, and subtracting the second frame reset quantized data from the second frame exposure quantized data to obtain second frame quantized data; the first frame quantized data and the second frame quantized data are added to obtain final quantized data.

The embodiment of the invention also provides a CMOS image sensor which comprises a row selection circuit, a column selection circuit and a pixel array, wherein the pixel array comprises a plurality of pixel units which are arranged in an array, and the pixel units are any one of the pixel units.

Compared with the prior art, the technical scheme of the embodiment of the invention adds an extension structure and the like in the global exposure structure of the existing two-stage source follower, and improves the dynamic range of the pixel unit of the image sensor.

Drawings

FIG. 1 is a schematic structural diagram of a 5T-type global exposure structure pixel unit in the prior art;

FIG. 2 is a schematic structural diagram of a pixel unit with a 9T-type global exposure structure in the prior art;

FIG. 3 is a schematic diagram of a lateral overflow reservoir capacitor according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to an embodiment of the invention;

FIG. 5 is a schematic diagram of a pixel unit of a CMOS image sensor according to another embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a pixel unit having a 9T-type global exposure structure according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a method for controlling the pixel cell shown in FIG. 6 according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating global operation and row-by-row readout of the pixel cells of FIG. 6 according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the invention.

Detailed Description

In an image sensor including an existing Global exposure structure, a dynamic range of a pixel unit is small, a high dynamic range is not provided, and the requirement of high dynamic range application under Global exposure (Global Shutter) cannot be met.

According to different exposure modes, the conventional CMOS sensor can be classified into a CMOS sensor with line-by-line exposure and a CMOS sensor with global exposure. Global exposure refers to all pixels in a frame of image, and exposure starts at one time and ends at another time. The global exposure can eliminate the defect of motion blur of line-by-line exposure because the starting point and the ending point of each line of exposure time are the same, and clear image output is realized. Both 5T and 9T belong to globally exposed CMOS sensors.

Pixel unit of existing global exposure structure

V＝Q/C (2)

Wherein V, Q and C are voltage, charge and capacitance parameters, respectively.

From the above formula, it can be known that, in the case of a constant charge amount, the smaller the capacitance, the larger the voltage fluctuation, that is, the higher the sensitivity. Therefore, in order to improve the photosensitivity, FD cannot be made large, which makes the Full Well Capacity (FWC) of the pixel small, resulting in a small dynamic range of the pixel cell.

Fig. 3 is a schematic diagram of a structure of a Lateral Overflow accumulation Capacitor (LOFIC) according to an embodiment of the present invention, and the principle of the Lateral Overflow accumulation Capacitor is as follows: during pixel exposure, since the potential of electrons under the transfer transistor TX is lower than the potential around the photodiode PPD, when the light intensity is strong, after the photodiode PPD is filled with electrons, the electrons overflow to the storage node or the storage node and the lateral overflow accumulation capacitance through the bottom of the transfer transistor TX. The LOFIC can effectively extend the full well capacity of the image sensor such that the full well capacity of the pixel is no longer limited by the photodiode PPD full well, but depends on the magnitude of the lateral overflow accumulation capacitance.

The technical scheme of the invention utilizes the existing global exposure structure with two stages of source followers and utilizes correlated double sampling to subtract two signals and eliminate reset noise. Meanwhile, an extension structure is added, and the storage nodes are selectively extended. The first frame analog signal can be a high-sensitivity frame corresponding to the details of the dark part of the image; the second frame analog signal may be a low sensitivity frame corresponding to the details of the bright portion of the image. The full-well capacity of the pixel is not limited by the full-well of the photodiode any more by laterally overflowing the accumulation capacitor, and the third capacitor is selectively connected in parallel with the first storage node in combination with the first control transistor, so that the purpose of expanding the dynamic range can be achieved.

In an embodiment of the present invention, the global exposure structure includes 7T type, 8T type, 9T type, and the like, and the global exposure structure of this type includes a reset capacitor, a sampling capacitor, a transistor for controlling the reset capacitor, a transistor for controlling the sampling capacitor, a first source follower, and a second source follower.

In the description of the present invention, components having the same name have the same or similar functions, positional relationships, and connection relationships; signals having the same or similar labels have the same or similar functions, transmitting means and receiving means.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Fig. 4 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to an embodiment of the invention. The pixel cell 10 includes a global exposure structure 100 having a two-stage source follower, an extension structure 200.

The global exposure structure 100 is adapted to a global exposure structure outputting an analog signal of a first frame, and includes a photoelectric conversion element PPD, a transfer transistor TX, a first storage node FD, a second storage node SD, a first capacitance Cr1, a second capacitance Cs1, and the like. Specifically, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal; after the exposure of the pixel unit 10, the first frame reset analog signal of the first storage node FD is read out, and the first frame exposure analog signal of the first storage node FD is read out, wherein the noise of the respectively sampled first frame reset analog signal and first frame exposure analog signal is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the first frame analog signal can be eliminated.

The extension structure 200 is adapted to be coupled to the global exposure structure to output a second frame analog signal, the extension structure 200 includes a first control transistor SS1, a third capacitor C1, a second control transistor SWR2, a fourth capacitor Cr2, a third control transistor SWS2, and a fifth capacitor Cs2, a first terminal of the first control transistor SS1 is coupled to a first terminal of the third capacitor C1, and a second terminal of the first control transistor SS1 is coupled to the first storage node FD; a second terminal of the third capacitor C1 is coupled to the first power line, a first terminal of the fourth capacitor Cr2 is coupled to a second terminal of the second control transistor SWR2, a second terminal of the second capacitor is coupled to the first power line, a first terminal of the fifth capacitor Cs2 is coupled to a second terminal of the third control transistor SWS2, a second terminal of the fifth capacitor Cs2 is coupled to the first power line, first terminals of the second control transistor SWR2 and the third control transistor SWS2 are both coupled to the second storage node SD, and the first power line is a power line providing a voltage of the common ground; wherein the storage capacity of the third capacitor C1 is greater than that of the first storage node FD, and the first control transistor selectively connects the third capacitor C1 in parallel with the first storage node FD.

Specifically, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal; after the pixel unit 10 is exposed, the second frame reset analog signal of the first storage node FD and the third capacitor C1 is read out, and the second frame exposure analog signal of the first storage node FD and the third capacitor C1 is read out, wherein the noise of the respectively sampled second frame reset analog signal and second frame exposure analog signal is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the second frame analog signal can be eliminated.

In a specific implementation, after the pixel unit 10 is exposed to light, there are four readout operations, that is, a first frame reset analog signal (first readout operation) for reading out the first storage node FD, a first frame exposure analog signal (second readout operation) for reading out the first storage node FD, a second frame exposure analog signal (third readout operation) for reading out the first storage node FD and the third capacitance C1, and a second frame reset analog signal (fourth readout operation) for reading out the first storage node FD and the third capacitance C1, and the order of the four readout operations may be arbitrary. Preferably, both the first sensing operation and the second sensing operation, or both the third sensing operation and the fourth sensing operation are continuously operated to reduce the number of times the first control transistor SS1 is turned on; more preferably, both the first sensing operation and the second sensing operation are continuously operated, and both the third sensing operation and the fourth sensing operation are continuously operated, to further reduce the number of times the first control transistor SS1 is turned on.

During pixel exposure, since the potential of electrons under the transmission transistor TX is lower than the potential around the photodiode PPD, when the light intensity is strong, after the photodiode PPD is filled with electrons, the electrons overflow to the first storage node FD or the first storage node FD and the third capacitor C1 through the bottom of the transmission transistor TX. The third capacitor C1 is a lateral overflow accumulation capacitor, and the full-well capacity of the image sensor can be effectively expanded through the lateral overflow accumulation capacitor C1, so that the full-well capacity of the pixel is no longer limited by the full-well of the photodiode PPD. The low level of the transfer transistor TX is adjustable in a range of 0-0.5V in order to raise the potential of the channel of the transfer transistor TX so that the charge overflows to the first storage node FD or the first storage node FD and the third capacitor C1 through the channel of the transfer transistor TX after the photoelectric conversion element PDD is fully charged.

In some embodiments, the turning on or off of first control transistor SS1 is controlled by the control module. The control module may be an isp (image Signal processor) image processor. When the light intensity is small, the first control transistor SS1 is turned off to store the charge collected during the exposure on the first storage node FD, which stores the details of the dark portion of the image for the high-sensitivity frame corresponding to the first frame analog signal. When the light intensity is large, the control module controls the conduction of the first control transistor SS1, the first storage node FD and the third capacitor C1 are connected in parallel, charges collected during exposure are stored on the first storage node FD and the third capacitor C1, at this time, details of a bright place of an image are stored corresponding to a second frame analog signal and are low-sensitivity frames, and the full-well capacity of a pixel is not limited by the full-well of the photodiode any more by expanding the LOFIC capacitor, namely the third capacitor, but depends on the size of the third capacitor C1. This makes the full well capacity of the pixel cell 10 large, thereby improving the dynamic range of the pixel cell 10.

The storage capacity of the third capacitance C1 is larger than that of the first storage node FD. For example, the storage capacity of the third capacitor C1 is N times the storage capacity of the first storage node, where N is an integer greater than or equal to 8.

In a specific implementation, the optical signal is converted into an electric charge by the photodiode, and the electric charge is stored on the first storage node FD or on the first storage node FD and the third capacitance C1 by the transfer transistor.

As shown in formula (1), wherein P _max The representation can be detectedCorresponds to the capacitance values of the third capacitance C1 and the first storage node FD; p _min Representing the minimum intensity of light detectable, corresponds to the capacitance value of the first storage node FD. The increased value of the dynamic range may be represented by 20lgN, where N is a multiple of the sum of the capacitance value of the third capacitor C1 and the capacitance value of the first storage node FD with respect to the capacitance value of the first storage node FD, as shown in equation (3):

wherein, C _FD Is the capacitance value of the first storage node FD, C _C1 Is the capacitance value of the third capacitor C1. For example, when the sum of the capacitance value of the first storage node FD and the capacitance value of the third capacitance C1 is 32 times the capacitance value of the first storage node FD, the dynamic range may be improved by about 30 dB; when the sum of the capacitance value of the first storage node FD and the capacitance value of the third capacitor C1 is 100 times the capacitance value of the first storage node FD, the dynamic range may be improved by about 40 dB. Since increasing the dynamic range tends to come at the expense of sensitivity, and increasing the third capacitor C1 also increases the size of the circuit board, the larger the third capacitor C1 is, the better.

Fig. 5 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to another embodiment of the present invention. The pixel cell 20 includes a global exposure structure 100 with a two-stage source follower, an extension structure 200, and a quantization structure 300.

Specifically, the pixel unit 20 may further include a quantization structure 300 adapted to receive a first frame analog signal, quantize the first frame analog signal and obtain first frame quantized data based on the quantized first frame analog signal, receive a second frame analog signal, quantize the second frame analog signal and obtain second frame quantized data based on the quantized first frame analog signal, and add the first frame quantized data and the second frame quantized data to obtain final quantized data.

Specifically, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal, and the quantization structure 300 includes: a first quantization sub-module adapted to quantize the first frame reset analog signal to obtain first frame reset quantized data, quantize the first frame exposure analog signal to obtain first frame signal quantized data, subtract the first frame reset quantized data and the first frame signal quantized data to obtain first frame quantized data; a second quantization sub-module adapted to quantize the second frame reset analog signal to obtain second frame reset quantized data, quantize the second frame exposure analog signal to obtain second frame signal quantized data, subtract the second frame reset quantized data and the second frame signal quantized data to obtain second frame quantized data; a processing sub-module adapted to add the first frame quantized data and the second frame quantized data to obtain final quantized data.

In a specific implementation, the first control transistor SS1 is controlled by the control module to be turned on or off.

When the first control transistor SS1 is turned off, a first frame analog signal may be output as a high-sensitivity frame, which may correspond to details of an image dark place. Specifically, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal; after the exposure of the pixel unit 20, the first frame reset analog signal of the first storage node FD and the first frame exposure analog signal of the first storage node FD are read out, wherein the noise of the respectively sampled first frame reset analog signal and first frame exposure analog signal is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the first frame analog signal can be eliminated.

When the first control transistor SS1 is turned on, a second frame analog signal may be output, which is a low-sensitivity frame and may correspond to the details of the bright portion of the image. Specifically, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal; after the pixel unit 20 is exposed, the second frame reset analog signal of the first storage node FD and the third capacitor C1 is read out, the first frame exposure analog signal of the first storage node FD and the third capacitor C1, wherein the noise of the respectively sampled second frame reset analog signal and second frame exposure analog signal is correlated, i.e. correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the second frame analog signal can be eliminated.

The high-sensitivity frame and the low-sensitivity frame may be quantized separately. And the quantized high-sensitivity frame and the low-sensitivity frame are fused, so that the detail information of a bright area and a dark area in the transient image is reflected in the same image, a clear image is obtained, and the dynamic range of pixels is expanded.

For example, when adding the first frame quantized data and the second frame quantized data, the image data that is not saturated in the second frame quantized data may be taken, and the image data that is saturated or oversaturated in the second frame quantized data may be replaced by the quantized data at the corresponding position in the first frame multiplied by a multiple (sensitivity ratio of the second frame to the first frame), thereby fusing the first frame quantized data and the second frame quantized data.

Fig. 6 is a schematic structural diagram of a pixel unit having a 9T-type global exposure structure according to an embodiment of the present invention. The pixel unit 30 includes a 9T-type global exposure structure 110 and an extension structure 210.

The 9T-type global exposure structure 110 includes, in addition to the photoelectric conversion element PPD, the transfer transistor TX, the first storage node FD, the second storage node SD, the first capacitance Cr1, and the second capacitance Cs 1: a reset transistor RST, a first stage source follower SF1, an isolation transistor AMS, a fourth control transistor BIAS, a fifth control transistor SWR1, a sixth control transistor SWS1, a second stage source follower SF2, and a row select transistor SEL.

An anode terminal of the photoelectric conversion element PDD is coupled to a first power line, a cathode terminal of the photoelectric conversion element PDD is coupled to a first terminal of a transmission transistor TX, a second terminal of the transmission transistor TX is coupled to a second terminal of a first control transistor SS1, a first terminal of a reset transistor RST is coupled to a second power line VDD, a second terminal of the reset transistor RST is coupled to a first terminal of a third capacitor C1, a gate of a first stage source follower SF1 is coupled to a first storage node FD, a first terminal of the first control transistor AMS is coupled to a second terminal of the first stage source follower SF1, a first terminal of a fourth control transistor BIAS is coupled to a second storage node SD, a second terminal of the fourth control transistor BIAS is coupled to a first power line, a first terminal of a fifth control transistor SWR1 is coupled to a second storage node SD, a second terminal of the fifth control transistor SWR1 is coupled to a first terminal of a first capacitor Cr1, a second terminal of the first capacitor Cr1 is coupled to a first power line, a first terminal of a sixth control transistor SWS1 is coupled to a second storage node SD, a second storage node SD, A second terminal of the second capacitor Cs1 is coupled to the first terminal of the second capacitor Cs1, a second terminal of the second capacitor Cs1 is coupled to a first power line, a gate of the second stage source follower SF2 is coupled to the second storage node SD, a first terminal of the second stage source follower SF2 is coupled to the second power line VDD, a first terminal of the row selection transistor SEL is coupled to the second terminal of the second stage source follower SF2, and a second terminal of the row selection transistor SEL is coupled to the bit line Bitline of the pixel unit 30, wherein the second power line VDD is a power line for providing a working voltage to the pixel unit 30.

In the embodiment shown in the figure, all transistors of the 9T-type global exposure structure 110 are NMOS transistors, but in other embodiments, PMOS transistors may be used instead of all NMOS transistors.

Fig. 7 is a method for controlling the pixel unit 30 according to an embodiment of the present invention, which can be based on the exposure timing chart shown in fig. 8. The method 40 comprises the steps of:

step S110: the gate control signals of the reset transistor RST and the transmission transistor TX are set to a high level to reset the first storage node FD and the photoelectric conversion element PPD, and the gate control signals of the reset transistor RST and the transmission transistor TX are set to a low level to start exposure of the pixel unit.

Step S120: the gate control signal of the first control transistor SS1 is set to a high level, and the charge flows to the first storage node FD and the third capacitance through the transfer transistor TX after the photoelectric conversion element PPD is filled with the charge.

Step S130: after exposure is finished, grid control signals of the isolation transistor AMS and the fourth control transistor BIAS are set to be high level.

Step S140: the gate control signal of the first control transistor SS1 is set to a low level, the gate control signal of the fifth control transistor SWR1 is set to a high level, the first capacitor Cr1 is charged, then the gate control signal of the fifth control transistor SWR1 is set to a low level, and the reset analog signal of the first frame is stored on the first capacitor Cr 1.

Step S150: the gate control signal of the transmission transistor TX is set to a high level, the charges collected during exposure are transferred from the photoelectric conversion element PPD onto the first storage node FD, and the gate control signal of the transmission transistor TX is set to a low level after the transfer is completed.

Step S160: the gate control signal of the sixth control transistor SWS1 is set to a high level, the second capacitor Cs1 is charged, the gate control signal of the sixth control transistor SWS1 is set to a low level after the signal is established, and the exposure analog signal of the first frame is stored on the second capacitor Cs 1.

Step S170: the gate control signals of the first control transistor SS1 and the transfer transistor TX are set to a high level, and the charges remaining in the photoelectric conversion element PPD are transferred to the first storage node FD and the third capacitor C1.

Step S180: the gate control signal of the third control transistor SWS2 is set to a high level, the fifth capacitor Cs2 is charged, and the gate control signal of the third control transistor SWS2 is set to a low level after the signal is established, so that the second frame exposure analog signal is stored on the fifth capacitor Cs 2.

Step S190: the gate control signal of the reset transistor RST is set to a high level to reset the first storage node FD and the third capacitor C1, the gate control signal of the second control transistor SWR2 is set to a high level to charge the fourth capacitor Cr2, and then the gate control signal of the second control transistor SWR2 is set to a low level to store the reset analog signal of the second frame on the capacitor fourth capacitor Cr 2.

In the execution of the step S140, the control module may control the first control transistor SS1 to be turned off, i.e., the gate control signal of the first control transistor SS1 is set to a low level, through which the first capacitor Cr1 is charged and the reset analog signal of the first frame is stored on the first capacitor Cr 1.

In the execution of step S150, by this step, the electric charges collected during exposure are transferred from the photoelectric conversion element PPD onto the first storage node FD.

In the execution of step S160, by this step, the second capacitance Cs1 is charged, and the exposure analog signal of the first frame is stored on the second capacitance Cs 1.

In the execution of step 170, by this step, the charge remaining in the photoelectric conversion element PPD can be transferred to the first storage node FD and the third capacitance C1.

In execution of step S180, through this step, the fifth capacitance Cs2 is charged, and the second frame exposure analog signal is stored on the fifth capacitance Cs 2.

In the execution of step 190, the first storage node FD and the third capacitor C1 are reset first, by which the fourth capacitor Cr2 is charged and the reset analog signal of the second frame is stored on the fourth capacitor Cr 2.

In the above embodiment of the present invention, the fifth control transistor SWR1, the sixth control transistor SWS1, the third control transistor SWS2 and the second control transistor SWR2 are sequentially operated, so as to reduce the turn-on and turn-off times of the first control transistor SS1 and improve the working efficiency of the pixel unit 30.

In other embodiments of the present invention, the operation sequence of the fifth control transistor SWR1, the sixth control transistor SWS1, the third control transistor SWS2, and the second control transistor SWR2 may be arbitrarily adjusted.

Specifically, after the pixel unit 30 is exposed to light, there are four readout operations, that is, a first frame reset analog signal (first readout operation) to read out the first storage node FD based on the turning on and off of the fifth control transistor SWR1, a first frame exposure analog signal (second readout operation) to read out the first storage node FD based on the turning on and off of the sixth control transistor SWS1, a second frame exposure analog signal (third readout operation) to read out the first storage node FD and the third capacitance C1 based on the turning on and off of the third control transistor SWS2, and a second frame reset analog signal (fourth readout operation) to read out the first storage node FD and the third capacitance C1 based on the turning on and off of the second control transistor SWR 2.

The order of these four read operations may be arbitrary. Preferably, both the first sensing operation and the second sensing operation, or both the third sensing operation and the fourth sensing operation are continuously operated to reduce the number of times the first control transistor SS1 is turned on; more preferably, both the first sensing operation and the second sensing operation are continuously operated, and both the third sensing operation and the fourth sensing operation are continuously operated, to further reduce the number of times the first control transistor SS1 is turned on.

The steps S110 to S190 belong to a global operation phase, and after the global operation phase is completed, a row-by-row readout phase may be performed. Accordingly, the method of embodiments of the present invention may include the following steps S210-S250.

Step S210: the gate control signals of the first control transistor SS1, the isolation transistor AMS, and the fourth control transistor BIAS are set to a low level to start entering the progressive readout phase.

Step S220: the gate control signal of the row selection transistor SEL is set to a high level, the gate control signal of the fourth control transistor BIAS is set to a high level, and then set to a low level again to empty the second storage node SD, and then the gate control signal of the fifth control transistor SWR1 is set to a high level, and the second stage source follower SF2 passes the reset analog signal of the first frame of the second storage node SD (i.e., the voltage at the first capacitor Cr 1) onto the bit line Bitline to sample the reset analog signal of the first frame.

Step S230: the gate control signal of the fourth control transistor BIAS is set to a high level and then set to a low level to reset the second storage node SD, the gate control signal of the sixth control transistor SWS1 is then set to a high level, and the second stage source follower SF2 passes the exposure analog signal of the first frame of the second storage node SD (i.e., the voltage at the second capacitor Cs 1) onto the bit line Bitline to sample the exposure analog signal of the first frame, and then the gate control signal of the sixth control transistor SWS1 is set to a low level.

Step S240: the gate control signal of the fourth control transistor BIAS is set to a high level and then set to a low level to reset the second storage node SD, and then the gate control signal of the second control transistor SWR2 is set to a high level, and the second stage source follower SF2 passes the reset analog signal of the second frame of the second storage node SD (i.e., the voltage at the fourth capacitor Cr 2) onto the bit line Bitline to sample the second frame reset analog signal, and then the gate control signal of the second control transistor SWR2 is set to a low level.

Step S250: the gate control signal of the fourth control transistor BIAS is set to a high level and then set to a low level to reset the second storage node SD, and then the gate control signal of the third control transistor SWS2 is set to a high level, and the second-stage source follower SF2 passes the second frame exposure analog signal (i.e., the voltage at the fifth capacitor Cs 2) of the second storage node SD onto the bit line Bitline to sample the exposure analog signal of the second frame, and then the gate control signal of the third control transistor SWS2 is set to a low level.

In the execution of steps S220 and S230, the first frame reset analog signal and the first frame exposure analog signal collected during the exposure period are read out to the bit line Bitline, the first frame analog signal includes the first frame reset analog signal and the first frame exposure analog signal, and the first frame analog signal is a high-sensitivity frame and stores details of a dark image.

In the execution of steps S240 and S250, the second frame reset analog signal and the second frame exposure analog signal collected during the exposure period are read out to the bit line Bitline, the second frame analog signal includes the second frame reset analog signal and the second frame exposure analog signal, and the second frame analog signal is a low-sensitivity frame and stores details of a bright portion of an image.

In the above embodiment of the present invention, the fifth control transistor SWR1, the sixth control transistor SWS1, the second control transistor SWR2, and the third control transistor SWS2 are operated in sequence.

It is to be understood that in other embodiments of the present invention, the operation sequence of the fifth control transistor SWR1, the sixth control transistor SWS1, the second control transistor SWR2, and the third control transistor SWS2 may be freely adjusted.

The above steps S210-S250 belong to the progressive readout phase, after which the quantization phase can be entered. Accordingly, the method of an embodiment of the present invention may include the following steps S310-S330.

Step S310: the method includes quantizing a first frame reset analog signal to obtain first frame reset quantized data, quantizing a first frame exposure analog signal to obtain first frame exposure quantized data, and subtracting the first frame reset quantized data and the first frame exposure quantized data to obtain first frame quantized data.

Step S320: quantizing the second frame reset analog signal to obtain second frame reset quantized data, quantizing the second frame exposure analog signal to obtain second frame exposure quantized data, and subtracting the second frame reset quantized data and the second frame exposure quantized data to obtain second frame quantized data.

Step S330: the first frame quantized data and the second frame quantized data are added to obtain final quantized data.

In the execution of step S310, the first frame reset analog signal may be quantized in the quantization structure 300 to obtain first frame reset quantized data, the first frame exposure analog signal may be quantized to obtain first frame exposure quantized data, and the first frame reset quantized data and the first frame exposure quantized data may be subtracted to obtain first frame quantized data, thereby eliminating reset noise of the first frame analog signal.

In the execution of step S320, the second frame exposure analog signal may be quantized in the quantization structure 300 to obtain second frame exposure quantized data, and the second frame reset quantized data and the second frame exposure quantized data may be subtracted to obtain second frame quantized data, thereby eliminating reset noise of the second frame analog signal.

In the step S330, the quantized high-sensitivity frame (first frame analog signal) and the low-sensitivity frame (second frame analog signal) may be fused, and the details of the bright area and the area in the transient image are embodied in the same image by an image fusion method, so as to obtain a clear image and expand the dynamic range of the pixels.

Fig. 9 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the present invention.

The CMOS image sensor 400 includes a row selection circuit 410, a column selection circuit 420 and a pixel array 430, and the pixel array 430 includes a plurality of pixel units arranged in an array, and the pixel units may be the pixel units described above with reference to fig. 4 to 6.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pixel cell of a CMOS image sensor including a global exposure structure adapted to output a first frame of analog signals, which includes a photoelectric conversion element, a transfer transistor, a first storage node, a second storage node, a first capacitance, and a second capacitance, the pixel cell further comprising:

an extension structure adapted to be coupled to the global exposure structure and output a second frame of analog signals, the extension structure including a first control transistor, a third capacitor, a second control transistor, a fourth capacitor, a third control transistor, and a fifth capacitor, a first terminal of the first control transistor being coupled to a first terminal of the third capacitor, a second terminal of the first control transistor being coupled to the first storage node; a second terminal of the third capacitor is coupled to a first power line, a first terminal of the fourth capacitor is coupled to a second terminal of the second control transistor, a second terminal of the fourth capacitor is coupled to the first power line, a first terminal of the fifth capacitor is coupled to a second terminal of the third control transistor, a second terminal of the fifth capacitor is coupled to the first power line, first terminals of the second control transistor and the third control transistor are both coupled to the second storage node, and the first power line is a power line providing a common ground voltage; wherein the storage capacity of the third capacitance is greater than the storage capacity of the first storage node, the first control transistor selectively connecting the third capacitance in parallel with the first storage node.

2. The pixel cell of claim 1, wherein the storage capacity of the third capacitor is N times the storage capacity of the first storage node, wherein N is an integer greater than or equal to 8.

3. The pixel cell of claim 1, comprising a control module adapted to control the turning on or off of the first control transistor to control the storage of charge collected during exposure onto the first storage node, or onto the first storage node and the third capacitance.

4. The pixel cell of claim 1, wherein the global exposure structure is a 9T-type global exposure structure, further comprising: a reset transistor, a first stage source follower, an isolation transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a second stage source follower, and a row selection transistor, wherein an anode terminal of the photoelectric conversion element is coupled to the first power line, a cathode terminal of the photoelectric conversion element is coupled to the first terminal of the transmission transistor, a second terminal of the transmission transistor is coupled to the second terminal of the first control transistor, a first terminal of the reset transistor is coupled to the second power line, a second terminal of the reset transistor is coupled to the first terminal of the third capacitor, a gate of the first stage source follower is coupled to the first storage node, a first terminal of the first stage source follower is coupled to the second power line, a first terminal of the fourth control transistor is coupled to the second storage node, and a second terminal of the fourth control transistor is coupled to the first power line, a first terminal of the fifth control transistor is coupled to the second storage node, a second terminal of the fifth control transistor is coupled to a first terminal of the first capacitor, a second terminal of the first capacitor is coupled to the first power line, a first terminal of the sixth control transistor is coupled to the second storage node, a second terminal of the sixth control transistor is coupled to a first terminal of the second capacitor, a second terminal of the second capacitor is coupled to the first power line, a gate of the second-stage source follower is coupled to the second storage node, a first terminal of the second-stage source follower is coupled to the second power line, a first terminal of the row selection transistor is coupled to a second terminal of the second-stage source follower, and a second terminal of the row selection transistor is coupled to a bit line of the pixel unit, wherein the second power line is a power line for providing a working voltage to the pixel unit.

5. The pixel cell of claim 4, further comprising a quantization structure adapted to receive the first frame analog signal, quantize the first frame analog signal and obtain first frame quantized data based on the quantized first frame analog signal, receive the second frame analog signal, quantize the second frame analog signal and obtain second frame quantized data based on the quantized second frame analog signal, and add the first frame quantized data and the second frame quantized data to obtain final quantized data.

6. The pixel cell of claim 5, wherein the first frame analog signal comprises a first frame reset analog signal and a first frame exposure analog signal, wherein the second frame analog signal comprises a second frame reset analog signal and a second frame exposure analog signal, and wherein the quantization structure comprises:

a first quantization sub-module adapted to quantize the first frame reset analog signal to obtain first frame reset quantized data, quantize the first frame exposure analog signal to obtain first frame exposure quantized data, and subtract the first frame reset quantized data and the first frame exposure quantized data to obtain the first frame quantized data;

a second quantization sub-module adapted to quantize the second frame reset analog signal to obtain second frame reset quantized data, quantize the second frame exposure analog signal to obtain second frame exposure quantized data, and subtract the second frame reset quantized data and the second frame exposure quantized data to obtain the second frame quantized data;

a processing sub-module adapted to add the first frame quantized data and the second frame quantized data to obtain the final quantized data.

7. A method of controlling the pixel cell of claim 6, comprising:

setting gate control signals of the reset transistor and the transfer transistor to a high level to reset the first storage node and the photoelectric conversion element;

setting gate control signals of the reset transistor and the transmission transistor to a low level to start exposure of the pixel unit;

setting a gate control signal of the first control transistor to a high level, and allowing charges to flow to the first storage node and the third capacitor through the transmission transistor after the photoelectric conversion element is filled with the charges;

after exposure is finished, setting the grid control signals of the isolation transistor and the fourth control transistor to be high level;

setting a gate control signal of the first control transistor to a low level, setting a gate control signal of the fifth control transistor to a high level, charging the first capacitor, and then setting the gate control signal of the fifth control transistor to a low level while storing a reset analog signal of the first frame on the first capacitor;

setting a gate control signal of the transfer transistor to a high level, transferring charges collected during exposure from the photoelectric conversion element onto the first storage node, and setting the gate control signal of the transfer transistor to a low level after the transfer is completed;

setting a grid control signal of the sixth control transistor to be at a high level, charging the second capacitor, and setting the grid control signal of the sixth control transistor to be at a low level after the signal is established so as to store the exposure analog signal of a first frame on the second capacitor;

setting gate control signals of the first control transistor and the transmission transistor to a high level to transfer charges remaining in the photoelectric conversion element to a first storage node and the third capacitor;

setting a grid control signal of the third control transistor to be at a high level, charging the fifth capacitor, and setting the grid control signal of the third control transistor to be at a low level after the signal is established so as to store a second frame exposure analog signal on the fifth capacitor;

setting a gate control signal of the reset transistor to a high level to reset the first storage node and the third capacitor, setting a gate control signal of the second control transistor to a high level to charge the fourth capacitor, and then setting the gate control signal of the second control transistor to a low level to store a reset analog signal of a second frame on the fourth capacitor.

8. The method of claim 7, comprising:

setting gate control signals of the first control transistor, the isolation transistor and the fourth control transistor to be low level so as to start entering a line-by-line reading stage;

setting the gate control signal of the row selection transistor to be at a high level, setting the gate control signal of the fourth control transistor to be at a high level, then setting the gate control signal of the fourth control transistor to be at a low level again to empty the second storage node, then setting the gate control signal of the fifth control transistor to be at a high level, and transmitting the reset analog signal of the first frame of the second storage node onto the bit line by the second-stage source follower to sample the reset analog signal of the first frame;

setting a gate control signal of the fourth control transistor to a high level and then to a low level to reset the second storage node, and then setting a gate control signal of the sixth control transistor to a high level, the second stage source follower passing an exposure analog signal of a first frame of the second storage node onto the bit line to sample the exposure analog signal of the first frame, and then setting the gate control signal of the sixth control transistor to a low level;

setting a gate control signal of the fourth control transistor to a high level and then to a low level to reset the second storage node and then setting a gate control signal of the second control transistor to a high level, the second stage source follower passing a reset analog signal of a second frame of the second storage node onto the bit line to sample the second frame reset analog signal and then setting the gate control signal of the second control transistor to a low level;

setting a gate control signal of the fourth control transistor to a high level, then to a low level to reset a second storage node, then setting a gate control signal of the third control transistor to a high level, and the second stage source follower transmits a second frame exposure analog signal of the second storage node onto a bit line to sample an exposure analog signal of a second frame, and then sets the gate control signal of the third control transistor to a low level.

9. The method of claim 8, comprising:

quantizing the first frame reset analog signal to obtain first frame reset quantized data, quantizing the first frame exposure analog signal to obtain first frame exposure quantized data, and subtracting the first frame reset quantized data and the first frame exposure quantized data to obtain the first frame quantized data;

quantizing the second frame reset analog signal to obtain second frame reset quantized data, quantizing the second frame exposure analog signal to obtain second frame exposure quantized data, and subtracting the second frame reset quantized data and the second frame exposure quantized data to obtain the second frame quantized data;

adding the first frame quantized data and the second frame quantized data to obtain the final quantized data.

10. A CMOS image sensor, comprising a row selection circuit, a column selection circuit and a pixel array, wherein the pixel array comprises a plurality of pixel units arranged in an array, and the pixel unit is the pixel unit as claimed in any one of claims 1 to 6.