CN110971844B - Circuit for expanding full-well capacity of pixels of CMOS image sensor - Google Patents
Circuit for expanding full-well capacity of pixels of CMOS image sensor Download PDFInfo
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- CN110971844B CN110971844B CN201911171858.3A CN201911171858A CN110971844B CN 110971844 B CN110971844 B CN 110971844B CN 201911171858 A CN201911171858 A CN 201911171858A CN 110971844 B CN110971844 B CN 110971844B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Abstract
The invention relates to a circuit for expanding the full well capacity of a pixel of a CMOS image sensor, which is technically characterized in that: the source electrode of the second transistor is connected with the drain electrode of the third transistor, and the source electrode of the third transistor is connected to the analog column output bus; the grid of the second transistor, the source of the fifth transistor and the cathode of the photodiode are connected to one input end of the comparator, the output end of the comparator is connected with the drain of the first transistor, the source of the first transistor is connected with the first inverter, the output end of the first inverter is connected with one input end of the second inverter and the NAND gate, and the output end of the NAND gate is connected with the grid of the fifth transistor; the output end of the second inverter is connected with a counter, the output end of the counter is connected with a tri-state control switch, and the output end of the tri-state control switch is connected with a digital column output bus. The invention realizes the ultra-large expansion function of the full-well capacity in a single pixel of the CMOS image sensor by carrying out multiple transfer counting reset on the full-well charges.
Description
Technical Field
The invention belongs to the technical field of semiconductor photoelectric detection, and particularly relates to a circuit for expanding the full well capacity of a pixel of a CMOS image sensor.
Background
The current image sensor mainly comprises a CCD and a CMOS. In the early stage, due to the limitation of the process level, the CMOS image sensor has problems of high noise, low sensitivity, etc., and the CCD image sensor invented later relative to the CMOS image sensor is rapidly developed and widely used in various fields such as military, aerospace, civil and industrial fields. However, with the progress of CMOS technology, CMOS image sensors have been rapidly developed in the nineties by virtue of their advantages of low power consumption, low cost, high integration, and strong radiation interference resistance, and have substantially reached the characteristic level of CCD image sensors.
Unlike the MOS capacitor structure of the CCD, many of the current CMOS image sensors rely on a photodiode for photoelectric conversion and charge collection, and are classified into a passive type and an active type. Due to the fact that the passive pixels are poor in performance, and there are few major breakthroughs in real application research, the passive pixel structure is quickly replaced by the active pixels due to the superiority of the active pixels. While the common active pixels mainly have 3T and 4T and improved structures based on the two structures. The increase of the full-well capacity of the traditional 3T structure depends heavily on the expansion of the pixel area, so that the full-well capacity is difficult to realize overlarge expansion under the restriction of the pixel size, the potential well is easily saturated in the longer exposure time under the strong light intensity in the practical application, the detection of an object and the imaging in a large dynamic range are difficult to realize under the high-intensity background light, and further the practical application requirements under some special occasions are difficult to meet.
At present, the full-well capacity of the most representative CMOS image sensor pixel unit is mainly expanded by integrating a large-capacity capacitor in a pixel and transferring the full-well charge stored in the photodiode capacitor to an expansion capacitor through a transfer gate. In this way, the korean academy of science and technology of the optical state expands the full well capacity to 100ke by three transfers of the full well charge of the diode in the pixel; the northeast university in japan gradually expands the full well capacity from 70ke to 100ke to the current 200ke in a similar manner, and has better robustness while limiting the area below 7 um. However, the full-well capacity obtained by the above method still far cannot meet the requirement of some specific applications on the ultra-large well capacity, for example, when the full-well capacity is applied to a CMOS image sensor for time-and-day star-sensitive detection, during the daytime, the intensity of the sky background is extremely strong relative to the starlight, the charge of the image sensor is easily saturated, and the full-well capacity needs to reach Me level to realize daytime detection.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a circuit for expanding the full-well capacity of a pixel of a CMOS image sensor, wherein a relevant logic circuit is integrated in a pixel unit, and the full-well capacity of the pixel of the CMOS image sensor is expanded by carrying out transfer counting reset on full-well charges stored in a photodiode.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
a circuit for expanding the full well capacity of a pixel of a CMOS image sensor comprises five transistors, a photodiode, a NAND gate, a comparator, a counter and a tri-state control switch, wherein the drains of a second transistor, a fifth transistor and a fourth transistor are connected with a voltage end, the source of the second transistor is connected with the drain of a third transistor, the grid of the third transistor is connected with a column selection circuit control signal, and the source of the third transistor is connected with an analog column output bus; the grid of the second transistor, the source of the fifth transistor and the cathode of the photodiode are connected to one input end of the comparator together, the anode of the photodiode is grounded, the other input end of the comparator is connected with a reference voltage, the output end of the comparator is connected with the drain of the first transistor, the grid of the first transistor is connected with a reset and counting stop signal when the charges in the photodiode are read out, the source of the first transistor is connected with a first inverter, the output end of the first inverter is connected with one input end of a second inverter and a NAND gate, the other input end of the NAND gate is connected with a low-level reset signal before exposure of the photodiode, and the output end of the NAND gate is connected with the grid of the fifth transistor; the output end of the second inverter is connected with a counter, the counter is simultaneously connected with a counter reset signal, the output end of the counter is connected with a tristate control switch, the control end of the tristate control switch is connected with the source electrode of a fourth transistor, the grid electrode of the fourth transistor is connected with a column selection signal, and the output end of the tristate control switch is connected with a digital column output bus.
Further, the transistor is an NMOS transistor.
The invention has the advantages and positive effects that:
1. according to the invention, the full-well charge is transferred, counted and reset for multiple times, and the related circuit is integrated in a single pixel unit based on a 3T active pixel structure, so that the ultra-large expansion function of the full-well capacity in a single pixel of the CMOS image sensor is realized.
2. The invention reads out a large amount of stored full-trap charge information in a digital mode, has high signal reading precision and strong anti-interference performance, and is convenient for direct and rapid processing and storage of signals.
Drawings
FIG. 1 is a block diagram of a detector pixel cell of the present invention;
FIG. 2 is a timing diagram of the detector pixel cell full well extension of the present invention
In FIG. 1, PD is a photodiode, M1、M2、M3、M4、M5Are all NMOS transistors; m1For reading out control switches, M2And M3Forming an analog signal read-out source follower, M3Control signal SEL of selected column circuit1Control, M5For resetting the switch for the photodiode, M4Control enable signal, selected-column signal SEL, of three-state switch2Control, VrefIs the reference voltage of the comparator and is used for judging whether the diode is full, N is a NAND gate, Qn (N is 1,2,3 and 4) is the output count of the counter, and R is the output count of the counterPFor low-level reset signals, R, before exposure of the photodiodeCFor reset and count stop signals during charge readout in the photodiode, RDFor resetting the counter signal, VoutAn analog output for the diode to store charge, X, Y the corresponding position node;
in FIG. 2, tnFor pre-exposure (or post-signal read) reset time, tc1、tc2、tc3…tcnCounting time, t, for a single full well transfer, respectivelysFor the reset time after full well during exposure, trFor pixel data read-out time, tdFor reset time after data read-out, tpFor the exposure time, t is the single frame imaging time.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The invention is an improvement of the 3T active pixel structure of a CMOS image sensor, the circuit structure of which is shown in figure 1 and comprises five NMOS transistors M1～M5The device comprises a photodiode PD, an NAND gate N, a comparator, a counter and a tri-state control switch. The transistor M2、M5、M4Is connected to a voltage terminal VDD, said transistor M2Source and transistor M3Is connected to the drain of the transistor M3Is connected to the analog column output bus, transistor M3Is connected with a control signal SEL of the column selection circuit1(ii) a Transistor M2Gate of (1), transistor M5The source of the photodiode and the negative electrode of the photodiode PD are jointly used as a node Y and connected to one input end (negative) of the comparator, and the positive electrode of the photodiode PD is grounded; the other input end (+) of the comparator is connected with a reference voltage, and the output end of the comparator is connected with the transistor M1Of the drain electrode of transistor M1The grid of the photodiode is connected with a reset and counting stop signal R during the reading of the charges in the photodiodeCTransistor M1The source of the first inverter is connected with a first inverter, the output end of the first inverter is connected with a second inverter and one input end of a NAND gate N, and the other input end of the NAND gate N is connected with a low-level reset signal R before exposure of the photodiodePThe output end of the NAND gate N is used as a node X and a transistor M5The grid electrodes are connected; the output end of the second inverter is connected with a counter which is simultaneously connected with a counter reset signal, the output end Qn (n is 1,2,3,4) of the counter is connected with a three-state control switch, the control end of the three-state control switch is connected with the source electrode of a transistor M4, and the gate electrode of the transistor M4 is connected with a column selection signal SEL2The output terminal of the tri-state control switch is connected to the digital column output bus.
The full-well capacity expansion method of the CMOS image sensor provided by the invention is used for realizing the functions of resetting control and counting storage of the diode full well by integrating the comparator and the counter in a single pixel, reading out the charge information stored in the last photodiode by the source follower, and finally outputting analog and digital signals including detection information. As shown in fig. 2, the working process of the present invention is:
(1) resetting the image sensor before exposure, mainly including resetting RpSet to low level to generate high level signal to turn on M through NAND gate5Resetting of photodiode and pass RDResetting the counter.
(2) The detection is started, during the exposure, the voltage at the node Y during the reset period of the photodiode is detectedPull-up, reset switch M5After disconnection, the PD is in a floating state. When radiation is incident on the pn junction, photoelectric conversion occurs, photo-generated charge is generated, and the potential of the diode starts to decrease.
(3) Assuming that the light intensity is strong, the photo-generated charge quickly reaches the full well, and the voltage at node Y reaches a minimum when the photodiode voltage is at the full well. At this time, the reference voltage V set by the comparatorrefAnd comparing to judge whether the voltage reaches the lowest value, namely whether the diode is full of the well. When the judgment is true, the comparator outputs a high level signal and passes through M1The phase inverter and the NAND gate respectively output high level signals to the counter and the transistor switch, at the moment, the counter counts once when a rising edge arrives, and resets the photodiode, the voltage of the node Y is pulled up instantly, and the counting reset is performed by full-well transfer. And repeatedly carrying out transfer counting reset of the full wells for multiple times in the whole exposure time, and realizing counting storage of the charges in the full wells.
(4) When reading out the exposure end signal, the external circuit sets the control signal Rc to high level to make M1And disconnecting the subsequent reset and counting circuit to stop resetting and counting and prevent the reset signal from interfering the reading of the analog signal. Then the column select signal SEL1Set to high level, turn on M3Last stored charge information V in the back output photodiodeout. Likewise, will SEL2Set to high level to conduct M4And applying an enable signal to the tri-state control switch to output the digital signal Qn of the counter, so as to finish the detection imaging and reading of the single pixel, and realize the ultra-large expansion of the full-well capacity and the detection imaging of the CMOS image sensor.
(5) And repeating the steps to perform next detection.
The circuit for expanding the pixel full-well capacity of the CMOS image sensor can realize long-time exposure under strong light intensity and realize related detection imaging. For example, the pixel size may be set to 25um × 25 um. And inside the pixel, the exposure time is 100ms, a sixteen-bit counter is adopted, the full-well capacity of the photodiode exceeds 100ke, the full-well capacity of the pixel unit is expanded to exceed 1.5Me through transferring for 15 times, and a 12-bit output signal is generated in each frame, wherein the digital signal is 4 bits, and the analog signal is 8 bits.
Nothing in this specification is said to apply to the prior art.
It should be emphasized that the embodiments described herein are illustrative rather than restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but also includes other embodiments that can be derived from the technical solutions of the present invention by those skilled in the art.
Claims (2)
1. A circuit for extending the full well capacity of a CMOS image sensor pixel, comprising: the analog column selection circuit comprises five transistors, a photodiode, a NAND gate, a comparator, a counter and a three-state control switch, wherein the drains of the second transistor, the fifth transistor and the fourth transistor are connected with a voltage end, the source of the second transistor is connected with the drain of the third transistor, the grid of the third transistor is connected with a column selection circuit control signal, and the source of the third transistor is connected with an analog column output bus; the grid of the second transistor, the source of the fifth transistor and the cathode of the photodiode are connected to one input end of the comparator together, the anode of the photodiode is grounded, the other input end of the comparator is connected with a reference voltage, the output end of the comparator is connected with the drain of the first transistor, the grid of the first transistor is connected with a reset and counting stop signal when the charges in the photodiode are read out, the source of the first transistor is connected with a first inverter, the output end of the first inverter is connected with one input end of a second inverter and a NAND gate, the other input end of the NAND gate is connected with a low-level reset signal before exposure of the photodiode, and the output end of the NAND gate is connected with the grid of the fifth transistor; the output end of the second inverter is connected with a counter, the counter is simultaneously connected with a counter reset signal, the output end of the counter is connected with a tristate control switch, the control end of the tristate control switch is connected with the source electrode of a fourth transistor, the grid electrode of the fourth transistor is connected with a column selection signal, and the output end of the tristate control switch is connected with a digital column output bus;
the method includes resetting the image sensor before exposure, and includes RpSet to low level to generate high level signal to turn on M through NAND gate5Resetting of photodiode and pass RDResetting the counter;
the detection is started, in the exposure process, the voltage of the photodiode at the node Y is pulled high during the resetting, and the reset switch M is reset5After the diode is disconnected, the PD is in a floating state, when rays enter a pn junction, photoelectric conversion is carried out, photo-generated charges are generated, and the potential of the diode begins to be reduced;
thirdly, assuming that the light intensity is very strong, the photo-generated charges quickly reach the full well, and when the voltage of the photodiode is in the full well, the voltage of the node Y is the lowest; at this time, the reference voltage V set by the comparatorrefComparing to determine whether the voltage reaches the minimum value, i.e. whether the diode is full of the well, and when the voltage is true, outputting a high level signal by the comparator, and passing through M1The inverter and the NAND gate respectively output high level signals to the counter and the transistor switch, at the moment, the counter counts once when a rising edge arrives, and resets the photodiode, the voltage of the node Y is pulled up instantly, and the counting and resetting are performed by full-well transfer at the moment; repeatedly carrying out transfer counting reset of the full wells for multiple times in the whole exposure time, and realizing counting storage of the charges of the full wells;
fourth, when the exposure completion signal is read, the control signal Rc is set to a high level by the external circuit, and M is set to a high level1Disconnecting the subsequent reset and count circuits to stop resetting and counting, preventing the reset signal from interfering with the readout of the analog signal, and then applying the column select signal SEL to the analog signal1Set to high level, turn on M3Last stored charge information V in the back output photodiodeoutSimilarly, will SEL2Set to high level to conduct M4Applying an enable signal to a tri-state control switch to output a digital signal Qn of a counter, so as to finish detection imaging and reading of a single pixel, and realize super-large expansion of full-well capacity and detection imaging of the CMOS image sensor;
and fifthly, repeating the steps to carry out next detection.
2. The circuit of claim 1, wherein the circuit comprises: the transistor is an NMOS transistor.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051850A (en) * | 2011-10-11 | 2013-04-17 | 全视科技有限公司 | Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination |
| WO2016089547A1 (en) * | 2014-12-05 | 2016-06-09 | Qualcomm Incorporated | Pixel readout architecture for full well capacity extension |
| CN109068075A (en) * | 2018-08-21 | 2018-12-21 | 德淮半导体有限公司 | Cmos image sensor, pixel unit and its driving method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103051850A (en) * | 2011-10-11 | 2013-04-17 | 全视科技有限公司 | Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination |
| WO2016089547A1 (en) * | 2014-12-05 | 2016-06-09 | Qualcomm Incorporated | Pixel readout architecture for full well capacity extension |
| CN109068075A (en) * | 2018-08-21 | 2018-12-21 | 德淮半导体有限公司 | Cmos image sensor, pixel unit and its driving method |
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