CN116419077A - Dual conversion gain image reading method, image forming apparatus, and readable storage medium - Google Patents
Dual conversion gain image reading method, image forming apparatus, and readable storage medium Download PDFInfo
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- CN116419077A CN116419077A CN202111676362.9A CN202111676362A CN116419077A CN 116419077 A CN116419077 A CN 116419077A CN 202111676362 A CN202111676362 A CN 202111676362A CN 116419077 A CN116419077 A CN 116419077A
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Abstract
The application provides a dual conversion gain image reading method, an imaging device and a readable storage medium, wherein the image reading method comprises the following steps: starting a high conversion gain reset mode, and controlling a reading circuit to quantize the high conversion gain reset signal; starting a high conversion gain image mode, and controlling a reading circuit to quantize the high conversion gain image signal; starting a low conversion gain reset mode, and controlling a read-out circuit to quantize the low conversion gain reset signal; the low conversion gain image mode is turned on, and the readout circuit is controlled to perform quantization processing on the low conversion gain image signal. Through the optimized gain signal quantization sequence, the same column of reading circuit can be used for finishing the reading operation of a column of pixel signals, thereby greatly reducing the reading time and accelerating the reading speed.
Description
Technical Field
The present invention relates to the field of high-dynamic image processing technology, and in particular, to an image reading method with dual conversion gain, an imaging apparatus, and a readable storage medium.
Background
Dynamic Range (DR) is a key indicator that characterizes the maximum range of an input optical signal that a CMOS Image Sensor (CIS) can recognize. The requirements of certain application occasions on the dynamic range are high, and the bright area and the dark area of the image can be more vivid and rich through the higher dynamic range. In the design of CMOS Image Sensor (CIS) imaging, the realization of High Dynamic Range (HDR) of CMOS Image Sensor (CIS) by reading multi-frame images with Dual Conversion Gain (DCG) and synthesizing is currently the mainstream approach.
A conventional pixel structure and control timing for realizing a High Dynamic Range (HDR) using a dual conversion gain switches two modes, high Conversion Gain (HCG) and Low Conversion Gain (LCG), each mode respectively reading a reset (rst) signal and an image (sig) signal, by switching a Dual Conversion Gain (DCG) switch. Applicants have found that in conventional readout schemes, two columns of readout circuits process the High Conversion Gain (HCG) signal and the Low Conversion Gain (LCG) signal of a column of pixel bit lines, respectively, while only one column of readout circuits is active, wasting a portion of the readout circuits and increasing readout time.
Disclosure of Invention
The application provides a dual conversion gain image reading method, an imaging device and a readable storage medium, which are used for relieving the problem of low image reading speed.
In one aspect, the present application provides an image reading method of dual conversion gain, specifically, the image reading method includes:
starting a high conversion gain reset mode, and controlling a reading circuit to quantize the high conversion gain reset signal;
starting a high conversion gain image mode, and controlling the reading circuit to quantize the high conversion gain image signal;
starting a low conversion gain reset mode, and controlling the reading circuit to quantize the low conversion gain reset signal;
and starting a low conversion gain image mode and controlling the read-out circuit to carry out quantization processing on the low conversion gain image signal.
Optionally, the image reading method further includes, after performing the controlling the readout circuit to quantize the high conversion gain image signal and the low conversion gain image signal, respectively
The readout circuit is controlled to store the quantization result.
Optionally, the readout circuit includes a comparator and a counter, and the readout circuit sequentially quantizes the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal through the same comparator and counter.
Optionally, the image reading method includes, in executing the step of quantizing the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal by the control readout circuit:
according to the high conversion gain reset signal of the first input end of the comparator, a high conversion gain slope voltage is input to the second input end of the comparator, and the counter is controlled to count downwards;
when the state of the output signal of the comparator is reversed, controlling the counter to stop counting;
according to the high conversion gain image signal of the first input end of the comparator, inputting a high conversion gain ramp voltage to the second input end of the comparator, and controlling the counter to count upwards;
when the state of the output signal of the comparator is reversed, controlling the counter to stop counting;
according to the low conversion gain reset signal of the first input end of the comparator, a low conversion gain slope voltage is input to the second input end of the comparator, and the counter is controlled to count downwards;
when the state of the output signal of the comparator is reversed, controlling the counter to stop counting;
according to the low conversion gain image signal of the first input end of the comparator, a low conversion gain slope voltage is input to the second input end of the comparator, and the counter is controlled to count upwards;
and when the state of the output signal of the comparator is reversed, controlling the counter to stop counting.
Optionally, before the readout circuit quantizes the high conversion gain reset signal and the low conversion gain reset signal, the method further includes:
and performing conversion gain zero clearing on a comparator in the reading circuit.
Optionally, the step of turning on the high conversion gain reset mode further includes:
the turn-on reset switch and the conversion gain switch reset the floating diffusion node.
Optionally, before the readout circuit finishes quantizing the high conversion gain reset signal, the readout circuit further includes:
the reset switch and the conversion gain switch are turned off to read the high conversion gain reset signal.
Optionally, before the readout circuit performs quantization on the high conversion gain image signal, the readout circuit further includes:
and keeping the reset switch piece and the conversion gain switch piece to be disconnected, and disconnecting the transmission switch piece after the reset switch piece and the conversion gain switch piece are connected so as to read the high conversion gain image signal.
Optionally, the turning on the low conversion gain reset mode includes:
the reset switch is kept off, and the conversion gain switch is turned on to read the low conversion gain reset signal.
Optionally, before the readout circuit finishes quantizing the low-gain image signal, the readout circuit further includes:
and keeping the reset switch element to be disconnected and the conversion gain switch element to be conducted, and disconnecting the transmission switch element after the conversion gain switch element is conducted so as to read the low-gain image signal.
Optionally, the step of executing the low conversion gain reset mode comprises:
and increasing the capacitance of the floating diffusion node to a preset capacitance interval.
In another aspect, the present application further provides an imaging apparatus, specifically, the imaging apparatus includes a control circuit, and a pixel circuit and a readout circuit connected to the control circuit, respectively, the readout circuit including a comparator;
the pixel circuit is configured to output a pixel signal according to a control signal of the control circuit and is connected to the readout circuit; the readout circuit is configured to perform quantization processing on the pixel signal output from the pixel circuit by the comparator;
the control circuit is used for controlling the pixel circuit to output pixel signals and realizing the image reading method.
Optionally, the pixel circuit includes a photodiode and a transfer switch, the photodiode is connected to the floating diffusion node through the transfer switch; the control end of the transmission switch piece is connected with the control circuit.
Optionally, the pixel circuit includes a supplemental capacitor, a reset switch element, and a conversion gain switch element, wherein control ends of the reset switch element and the conversion gain switch element are connected to the control circuit, a first end of the supplemental capacitor is grounded or a fixed voltage source, and a second end of the supplemental capacitor is connected between the reset switch element and the conversion gain switch element, and is connected to the floating diffusion node through the conversion gain switch element.
Optionally, the readout circuit further includes a counter, the pixel circuit is connected to a first input terminal of the comparator, and a second input terminal of the comparator receives a ramp signal; the output end of the comparator is connected with the input end of the counter.
Optionally, the readout circuit further includes a memory, and an output end of the counter is connected to an input end of the memory.
Optionally, the pixel circuit includes a supplemental capacitor and a supplemental switch, a first end of the supplemental capacitor is grounded or a fixed voltage source, a second end of the supplemental capacitor is connected to the floating diffusion node through the supplemental switch, a control end of the supplemental switch is connected to the control circuit, and the control circuit is configured to control the supplemental switch to be turned on when the low conversion gain image mode is turned on.
In another aspect, the present application also provides a readable storage medium, in particular, a readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the image reading method as described above.
As described above, the dual conversion gain image reading method, imaging apparatus and readable storage medium according to the present invention can read the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal in the same column of readout circuits according to the optimized gain signal quantization sequence, and can complete the reading operation of a column of pixel signals without changing the structure of the pixel circuits, thereby greatly reducing the reading time and increasing the reading speed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a basic structural block diagram of an image sensor system.
Fig. 2 is a diagram of pixel circuit connection in an embodiment of the present application.
Fig. 3 is a pixel circuit connection diagram of a two-way pixel sharing structure according to an embodiment of the present application.
Fig. 4 is a flowchart of a dual conversion gain image reading method according to an embodiment of the present application.
Fig. 5 is a block diagram of an image forming apparatus according to an embodiment of the present application.
FIG. 6 is a schematic diagram of a readout circuit according to an embodiment of the present application.
Fig. 7 is a circuit timing diagram of an image reading method according to an embodiment of the present application.
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The following provides a detailed description of what is presented in connection with the various figures. Fig. 1 is a basic structural block diagram of an image sensor system.
As shown in fig. 1, the image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to a pixel array 101.
The functional logic unit 103 is connected to the readout circuit 102, and performs logic control of reading of the pixel circuit. The readout circuit 102 and the control circuit 104 are connected to a status register 105, and realize read control of the pixel array 101. The pixel array 101 includes a plurality of pixel circuits in rows (R1, R2, R3 … Ry) and columns (C1, C2, C3 … Cx), and pixel signals output from the pixel array 101 are output to the readout circuit 102 via column lines. In one embodiment, after each pixel circuit acquires image data, the image data is read out by the readout circuit 102, which designates a readout mode by the status register 105, and then transferred to the functional logic 103. In particular applications, the readout circuitry 102 may include analog-to-digital conversion (ADC) circuitry, amplification circuitry, and others. In some embodiments, the status register 105 may include a programmable selection system for determining whether the read-out system is to read out in a rolling exposure mode (rolling shutter) or a global exposure mode (global shutter). The functional logic 103 may store only image data or image data applied or processed by an image effect. In one application, the readout circuitry 102 may read out a row of image data at a time along readout column lines (as shown in fig. 1), or may read out the image data in various other ways. The operation of the control circuit 104 may be determined by the current setting of the status register 105. For example, the control circuit 104 generates a shutter signal for controlling image acquisition. In some applications, the shutter signal may be a global exposure signal such that all pixels of the pixel array 101 acquire their image data simultaneously through a single acquisition window. In some other applications, the shutter signal may be a rolling exposure signal, with each pixel row implementing a read operation in succession through the acquisition window.
First embodiment
Fig. 2 is a diagram of pixel circuit connection in an embodiment of the present application. The pixel array of the image sensor includes a plurality of pixel circuits arranged in rows and columns as shown in fig. 2, and the photosensitive pixels in each pixel circuit include a photosensitive diode PD and a transfer switch TX, which transfers electrons generated by the photosensitive diode PD through a photoelectric effect to a floating diffusion FD. The dual conversion gain control circuit includes a conversion gain switch DCG and a supplemental capacitor Cdcg connected between a reset switch RST and a floating diffusion FD for implementing a pixel circuit operating in a low conversion gain or high conversion gain mode according to a control signal.
The pixel signal is amplified by the source follower switch SF and outputted to a column line (pixel out output) by the row select switch RS. In another embodiment, the pixel circuit may be a photosensitive pixel employing a shared structure.
Second embodiment
Fig. 3 is a pixel circuit connection diagram of a two-way pixel sharing structure according to an embodiment of the present application.
As shown in fig. 3, the photo diode PD1 and the transfer switching element TX1 and the photo diode PD2 and the transfer switching element TX2 constitute a photosensitive pixel of a shared structure, which is shared and connected to the floating diffusion FD. The pixel circuit with the shared structure can reduce the number of switch pieces in the pixel circuit and the design area of a chip; it can be understood that the area of the photosensitive area can be increased under the condition that the design area of the pixel circuit is unchanged, so that the photosensitivity of the pixel circuit is improved, and the performance of the pixel circuit is improved. The drawings and embodiments presented herein are not limited to the two-way pixel sharing mode, and in some embodiments, a four-way pixel sharing architecture may be used, such as where the pixel sharing units are connected and share the floating diffusion FD by PD1 and TX1, PD2 and TX2, PD3 and TX3, and PD4 and TX4 in a four-way sharing architecture.
With continued reference to fig. 2, the supplemental capacitance Cdcg may be a device capacitance or a parasitic capacitance of the junction of the reset switch RST and the conversion gain switch DCG to ground. The embodiment shown in fig. 2 is a device capacitance, the other pole of the supplemental capacitance Cdcg being connected to a voltage VC. In another embodiment, the complementary capacitance Cdcg capacitance is a parasitic capacitance of the connection point of the reset switch RST and the conversion gain switch DCG to ground, and the other pole of the capacitance may be grounded.
Third embodiment
In another embodiment, the pixel circuit includes a supplemental capacitor and a supplemental switching element. The first end of the supplementary capacitor is grounded or is connected with a fixed voltage source, the second end of the supplementary capacitor is connected with the floating diffusion node through the supplementary switch element, the control end of the supplementary switch element is connected with the control circuit, and the control circuit is configured to control the conduction of the supplementary switch element when the low conversion gain image mode is started.
When entering the low conversion gain reset mode, the control circuit may control the supplemental switch to conduct, causing the supplemental capacitor to be incorporated into the floating diffusion node to increase the capacitance at the floating diffusion node.
Fourth embodiment
Fig. 4 is a flowchart of a dual conversion gain image reading method according to an embodiment of the present application.
Referring to fig. 4, in an embodiment, the image reading method includes:
s10: and starting a high conversion gain reset mode, and controlling the reading circuit to quantize the high conversion gain reset signal.
The image sensor may be controlled to turn off the reset switch and the conversion gain switch to turn on the high conversion gain reset mode, and first read the high conversion gain reset signal.
In an embodiment, the step of turning on the high conversion gain reset mode may include, prior to performing the step of:
the turn-on reset switch and the conversion gain switch reset the floating diffusion node.
Before the image signal is read and quantized once, the floating diffusion node is reset, so that the accuracy of the quantization and the readout of a readout circuit can be ensured.
In one embodiment, the comparator may be further cleared of the conversion gain before the readout circuit quantizes the high conversion gain reset signal. The readout circuit including a comparator and a counter, the step of performing quantization processing on the high conversion gain reset signal by the control readout circuit may include:
according to a high conversion gain reset signal of a first input end of the comparator, inputting a high conversion gain ramp voltage to a second input end of the comparator, and controlling the counter to count downwards;
when the state of the output signal of the comparator is reversed, the control counter stops counting.
The reset signal level can be subjected to A/D conversion by a down-counting method, so that the reset signal quantization of the image sensor is realized.
S20: the high conversion gain image mode is turned on, and the readout circuit is controlled to perform quantization processing on the high conversion gain image signal.
The image sensor is controlled to keep the reset switch element and the conversion gain switch element to be disconnected, and then the transmission switch element is disconnected after the disconnection, so that the charges after the light sensing of the light sensing diode are led into the floating diffusion node to enter a high conversion gain image mode, and the readout circuit is used for high conversion gain image signals.
In one embodiment, the high conversion gain image mode is turned on to turn on the transmission switch in the pixel circuit; and then opening the transmission switch piece after a preset time period. The step of performing quantization processing on the high conversion gain image signal by the control readout circuit includes:
according to the high conversion gain image signal of the first input end of the comparator, inputting a high conversion gain ramp voltage to the second input end of the comparator, and controlling the counter to count upwards;
when the state of the output signal of the comparator is reversed, the control counter stops counting.
The short-time conduction transmission switch element can lead the charges after the light sensing of the light sensing diode to be led into the floating diffusion node and enter a high conversion gain image mode. The image signal level of the image sensor can be subjected to A/D conversion by an up-counting method, so that the image signal quantization of the image sensor is realized.
S30: and starting a low conversion gain reset mode, and controlling the read-out circuit to quantize the low conversion gain reset signal.
In one embodiment, the step of performing the low conversion gain reset mode comprises:
and increasing the capacitance of the floating diffusion node to a preset capacitance interval.
The image sensor may be controlled to remain off for the reset switch and turn on the conversion gain switch, incorporating parasitic capacitance or device capacitance between the reset switch and the conversion gain switch to the floating diffusion node. The high conversion gain reset signal is read by increasing the capacitance of the floating diffusion node to turn on the low conversion gain reset mode. In another embodiment, the capacitance of the floating diffusion node may also be increased by incorporating other capacitances.
In one embodiment, the comparator may be further cleared of the conversion gain before the readout circuit quantizes the low conversion gain reset signal. The step of performing quantization processing on the low conversion gain reset signal by the control readout circuit may include:
according to a low conversion gain reset signal of a first input end of the comparator, inputting a low conversion gain ramp voltage to a second input end of the comparator, and controlling the counter to count down;
when the state of the output signal of the comparator is reversed, the control counter stops counting.
The reset signal level can be subjected to A/D conversion by a down-counting method, so that the reset signal quantization of the image sensor is realized.
S40: the low conversion gain image mode is turned on, and the readout circuit is controlled to perform quantization processing on the low conversion gain image signal.
The image sensor is controlled to keep the reset switch element to be turned off and the conversion gain switch element to be turned on, and then the transmission switch element is turned off after the reset switch element is turned on, so that residual charges of the light-sensing diode are led into the floating diffusion node to enter a low conversion gain image mode, and the readout circuit reads out high conversion gain image signals.
In one embodiment, the low conversion gain image mode is turned on to turn on the transfer switch in the pixel circuit; and then opening the transmission switch piece after a preset time period. The step of controlling the readout circuit to perform quantization processing on the low conversion gain image signal includes:
according to the low conversion gain image signal of the first input end of the comparator, inputting a low conversion gain ramp voltage to the second input end of the comparator, and controlling the counter to count upwards;
when the state of the output signal of the comparator is reversed, the control counter stops counting.
The short-time conduction transmission switch element can lead the residual charges of the light-sensing diode to the floating diffusion node and enter a low conversion gain image mode. The image signal level of the image sensor can be subjected to A/D conversion by an up-counting method, so that the image signal quantization of the image sensor is realized.
In one embodiment, the control readout circuit further includes, after quantizing the high conversion gain image signal and the low conversion gain image signal:
the control readout circuit stores the quantization result.
After the quantization of the high conversion gain and the low conversion gain is finished, the quantization result is stored, so that the functional logic unit can conveniently read when the data needs to be processed.
In this embodiment, the readout circuit sequentially performs quantization processing on the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal by the same comparator and counter. Through the optimized gain signal quantization sequence, the quantization results can be read by the same column of reading circuit according to the sequence of the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal and the low conversion gain image signal, and the reading operation of a column of pixel signals can be completed on the basis of not changing the structure of the pixel circuit, so that the reading time is greatly shortened, and the reading speed is accelerated. When it should be noted that, the conventional quantization circuits with two columns of readout circuits for respectively reading the high conversion gain and the low conversion gain may also use the method provided in the present application.
Fifth embodiment
The application also provides an imaging device. Fig. 5 is a block diagram of an image forming apparatus according to an embodiment of the present application.
Referring to fig. 5, in one embodiment, the imaging device includes a control circuit 104, and a pixel circuit 30 and a readout circuit 102 respectively connected to the control circuit 104, wherein the readout circuit 102 includes a comparator (not shown).
The pixel circuit 30 is configured to output a pixel signal in accordance with a control signal of the control circuit 104, and is connected to the readout circuit 102. The readout circuit 102 is configured to perform quantization processing on the pixel signal output from the pixel circuit 30 by a comparator.
The control circuit 104 is used to implement the image reading method as described above.
Through the optimized gain signal quantization sequence, the same column of reading circuit can be used for reading according to the sequence of the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal and the low conversion gain image signal, and the reading operation of a column of pixel signals can be completed on the basis of not changing the structure of the pixel circuit, so that the reading time is greatly shortened, and the reading speed is accelerated.
Referring to fig. 2 and 5, in one embodiment, the pixel circuit 30 includes a photodiode PD and a transfer switch TX, and the photodiode PD is connected to a floating diffusion node FD through the transfer switch TX; the control terminal of the transmission switch TX is connected to the control circuit 104.
In an embodiment, the pixel circuit 30 further includes a supplemental capacitor Cdcg, a reset switch RST and a conversion gain switch DCG, wherein control terminals of the reset switch RST and the conversion gain switch DCG are connected to the control circuit 104, a first terminal of the supplemental capacitor Cdcg is grounded or a fixed voltage source, and a second terminal of the supplemental capacitor Cdcg is connected between the reset switch RST and the conversion gain switch DCG, and is connected to the floating diffusion node FD through the conversion gain switch DCG.
FIG. 6 is a schematic diagram of a readout circuit according to an embodiment of the present application.
As shown in fig. 6, in an embodiment, the readout circuit further includes a counter 502 and a memory 503, the pixel circuit is connected to the first input Vinn of the comparator 501, and the second input Vinp of the comparator 501 receives the ramp signal vramp; the output Vout of the comparator 501 is connected to the input of the counter 502. The output of the counter 502 is connected to a memory 503. The comparator 501 may perform a zero clearing operation by switching the gain zero clearing switch cmp_az closed.
In one embodiment, the pixel circuit includes a supplemental capacitor and a supplemental switch, a first end of the supplemental capacitor being connected to the ground or to a fixed voltage source, a second end of the supplemental capacitor being connected to the floating diffusion node through the supplemental switch, a control end of the supplemental switch being connected to the control circuit, the control circuit being configured to control the supplemental switch to conduct when the low conversion gain image mode is turned on.
Sixth embodiment
Fig. 7 is a circuit timing diagram of an image reading method according to an embodiment of the present application. Please refer to fig. 2, 5 and 7, the specific timing is as follows:
turning on a column selection switch RS at time t0, setting a row selection signal rowsel to be high level, and connecting a pixel circuit to a first input end of a comparator;
turning on a conversion gain zero clearing switch piece cmp_az at the moment t1 to enable two input ends and an output end of the comparator to be short-circuited together, and enabling the comparator to start zero clearing;
turning off the reset switch rst and the conversion gain switch dcg at the time t2 to obtain a high conversion gain reset signal HCG rst;
turning off a conversion gain zero clearing switch component cmp_az at the moment t3, so that a first input end of the comparator is sampled to a high conversion gain reset signal HCG rst through capacitive coupling;
at time t4 the enable signal cmp_integer_en is set high while the ramp voltage vramp starts to fall, which signal is capacitively coupled into the second input of the comparator;
the enabling signal count_en is set to be high level at the moment t5, the counter starts to count downwards, when signals at two input ends of the comparator are overlapped, the state of the comparator is turned over, the counter stops counting, and the reading of the high conversion gain reset signal HCG rst is completed;
the enabling signal count_en is set to be low level at the time t6, the enabling signal cmp_integer_en is set to be low level at the time t7, and the ramp voltage vramp returns to the reference state;
at the time t8 to t9, the transmission switch tx is turned on, the control signal is set to be high level, the photo diode PD is communicated with the floating diffusion node FD, photo-generated charges drift from the photo diode PD to the floating diffusion node FD under the action of potential difference, so that the node potential of the floating diffusion node FD is reduced, and the pixel circuit obtains a high conversion gain image signal HCG sig;
the enable signal cmp_integer_en is set to a high level at time t10, and the ramp voltage vramp starts to drop;
the enabling signal count_en signal is set to be high level at the moment of t11, so that the counter starts to count upwards, when signals at two input ends of the comparator are overlapped, the state of the comparator is turned over, the counter stops counting, reading of the high conversion gain image signal HCG sig is completed, two signals of the high conversion gain HCG are quantized, the counter obtains the count value of the pixel signal, and the count value is written into the memory;
the enabling signal count_en is set to be low level at the time t12, the enabling signal cmp_integer_en is set to be low level at the time t13, and the ramp voltage vramp returns to the reference state;
turning on the conversion gain switch dcg at time t14, setting the conversion gain control signal to be high level, and increasing the floating diffusion node FD capacitance by the additional supplementary capacitance Cx to increase the potential, so that the pixel circuit obtains a low conversion gain reset signal LCG rst;
the conversion gain zero clearing switch piece cmp_az is conducted at the moment from t15 to t16, so that two input ends and output ends of the comparator are short-circuited together, and the comparator starts zero clearing.
After the time t16, closing a conversion gain zero clearing switch piece cmp_az to enable the input end of the comparator to sample a low conversion gain reset signal LCG rst;
the enable signal cmp_integer_en is set to a high level at time t17, and the ramp voltage vramp starts to decrease;
the enabling signal count_en signal is set to be high level at the moment of t18, so that the counter starts to count downwards, when signals at two input ends of the comparator are overlapped, the state of the comparator is turned over, the counter stops counting, and the low conversion gain reset signal LCG rst is read;
the enabling signal count_en is set to be low level at the time t19, the enabling signal cmp_integer_en is set to be low level at the time t20, and the ramp voltage vramp returns to the reference state;
at time t21 to time t22, the transfer switch tx is turned on, the control signal is set to be high level, the photodiode PD is communicated with the floating diffusion node FD, the charge left by the photodiode PD when the previous control signal is set to be high level and the charge additionally generated by exposure between the two high level operations of the control signal are transferred to the floating diffusion node FD, so that the potential of the floating diffusion node FD is reduced, and a low conversion gain image signal LCG sig is obtained;
at time t23, the enable signal cmp_integer_en is set to a high level, and the ramp voltage vramp starts to drop;
the enabling signal count_en signal is set to be high level at the time t24, so that the counter starts to count upwards, when signals at two input ends of the comparator are overlapped, the state of the comparator is turned over, the counter stops counting, the reading of the low conversion gain image signal LCG sig is completed, the two signals of the low conversion gain LCG are quantized, the counter obtains the count value of the pixel signal, and the count value is written into the memory;
the enabling signal count_en is set to be low level at the time of t25, the enabling signal cmp_integer_en is set to be low level at the time of t26, and the ramp voltage vramp returns to the reference state;
closing a reset switch element rst at the moment of t27, and setting a reset signal to be high level;
at time t28, the column select switch RS is turned off, and the row select signal rowsel is set to low. This is one quantization period of the pixel output.
Seventh embodiment
In another aspect, the present application also provides a readable storage medium, optionally, a computer program stored on the readable storage medium, which when executed by a processor, implements the steps of the image reading method as described above.
As described above, the dual conversion gain image reading method, imaging apparatus and readable storage medium according to the present invention can read quantization results in the same column readout circuit according to the order of the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal through the optimized gain signal quantization order, and can complete a column of pixel signal reading operation without changing the structure of the pixel circuit, thereby greatly reducing the reading time and accelerating the reading speed. When it is to be noted, the conventional quantization circuits in which two columns of readout circuits respectively read high conversion gain and low conversion gain may also use the method provided in the present application.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.
Claims (18)
1. A dual conversion gain image reading method, comprising:
starting a high conversion gain reset mode, and controlling a reading circuit to quantize the high conversion gain reset signal;
starting a high conversion gain image mode, and controlling the reading circuit to quantize the high conversion gain image signal;
starting a low conversion gain reset mode, and controlling the reading circuit to quantize the low conversion gain reset signal;
and starting a low conversion gain image mode and controlling the read-out circuit to carry out quantization processing on the low conversion gain image signal.
2. The method of claim 1, wherein controlling the readout circuit to quantize the high conversion gain image signal and the low conversion gain image signal further comprises:
the readout circuit is controlled to store the quantization result.
3. The method of claim 1, wherein the readout circuit quantizes the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal sequentially through the same comparator and counter.
4. The method of claim 3, wherein the step of controlling the readout circuit to quantize the high conversion gain reset signal, the high conversion gain image signal, the low conversion gain reset signal, and the low conversion gain image signal comprises:
according to the high conversion gain reset signal of the first input end of the comparator, a high conversion gain slope voltage is input to the second input end of the comparator, and the counter is controlled to count downwards;
when the state of the output signal of the comparator is reversed, controlling the counter to stop counting;
according to the high conversion gain image signal of the first input end of the comparator, inputting a high conversion gain ramp voltage to the second input end of the comparator, and controlling the counter to count upwards;
when the state of the output signal of the comparator is reversed, controlling the counter to stop counting;
according to the low conversion gain reset signal of the first input end of the comparator, a low conversion gain slope voltage is input to the second input end of the comparator, and the counter is controlled to count downwards;
when the state of the output signal of the comparator is reversed, controlling the counter to stop counting;
according to the low conversion gain image signal of the first input end of the comparator, a low conversion gain slope voltage is input to the second input end of the comparator, and the counter is controlled to count upwards;
and when the state of the output signal of the comparator is reversed, controlling the counter to stop counting.
5. The method of claim 1, wherein prior to the readout circuit quantizing the high conversion gain reset signal and the low conversion gain reset signal, further comprising:
and resetting the comparator in the reading circuit.
6. The method of claim 1, wherein the step of turning on the high conversion gain reset mode is preceded by the step of:
the turn-on reset switch and the conversion gain switch reset the floating diffusion node.
7. The method of claim 6, wherein the readout circuit further comprises, before the quantization of the high conversion gain reset signal is completed:
the reset switch and the conversion gain switch are turned off to read the high conversion gain reset signal.
8. The method of claim 7, wherein the readout circuit further comprises, before quantizing the high conversion gain image signal:
and keeping the reset switch piece and the conversion gain switch piece to be disconnected, and disconnecting the transmission switch piece after the reset switch piece and the conversion gain switch piece are connected so as to read the high conversion gain image signal.
9. The method of claim 8, wherein the turning on a low conversion gain reset mode comprises:
the reset switch is kept off, and the conversion gain switch is turned on to read the low conversion gain reset signal.
10. The method of claim 9, wherein the readout circuit further comprises, before quantizing the low gain image signal:
and keeping the reset switch element to be disconnected and the conversion gain switch element to be conducted, and disconnecting the transmission switch element after the conversion gain switch element is conducted so as to read the low-gain image signal.
11. The method of claim 1, wherein the step of performing the turn-on low conversion gain reset mode comprises:
and increasing the capacitance of the floating diffusion node to a preset capacitance interval.
12. An imaging device comprising a control circuit and a pixel circuit and a readout circuit respectively connected to the control circuit, the readout circuit comprising a comparator;
the pixel circuit is configured to output a pixel signal according to a control signal of the control circuit and is connected to the readout circuit;
the readout circuit is configured to perform quantization processing on the pixel signal output from the pixel circuit by the comparator;
the control circuit is configured to control the pixel circuit to output a pixel signal and to implement the image reading method according to any one of claims 1 to 11.
13. The imaging apparatus of claim 12, wherein the pixel circuit comprises a photodiode and a transfer switch, the photodiode being connected to the floating diffusion node through the transfer switch; the control end of the transmission switch piece is connected with the control circuit.
14. The imaging apparatus of claim 12, wherein the pixel circuit comprises a supplemental capacitor, a reset switch, and a conversion gain switch, control terminals of the reset switch and the conversion gain switch being connected to the control circuit, a first terminal of the supplemental capacitor being connected to ground or a fixed voltage source, a second terminal of the supplemental capacitor being connected between the reset switch and the conversion gain switch, the floating diffusion node being connected through the conversion gain switch.
15. The imaging apparatus of claim 12, wherein the readout circuit further comprises a counter, the pixel circuit being coupled to a first input of the comparator, a second input of the comparator receiving a ramp voltage; the output end of the comparator is connected with the input end of the counter.
16. The imaging apparatus of claim 15, wherein the readout circuit further comprises a memory, an output of the counter being coupled to an input of the memory.
17. The imaging apparatus of claim 12, wherein the pixel cell comprises a supplemental capacitor and a supplemental switch, a first terminal of the supplemental capacitor being connected to a ground or a fixed voltage source, a second terminal of the supplemental capacitor being connected to the floating diffusion node through the supplemental switch, a control terminal of the supplemental switch being connected to the control circuit, the control circuit being configured to control the supplemental switch to conduct when the low conversion gain image mode is turned on.
18. A readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the image reading method according to any of claims 1 to 17.
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