CN218103275U

CN218103275U - Lens focusing assembly and image sensor

Info

Publication number: CN218103275U
Application number: CN202222242354.XU
Authority: CN
Inventors: 林文龙; 侯金剑
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2022-08-24
Filing date: 2022-08-24
Publication date: 2022-12-20
Anticipated expiration: 2032-08-24

Abstract

The application provides a camera lens focus subassembly and image sensor, the camera lens focus subassembly includes: the pixel unit respectively outputs a reset signal, a pixel signal of a first side pixel circuit and pixel signals of the first side pixel circuit and a second side pixel circuit to the quantization circuit through a floating diffusion point; the quantization circuit includes: a comparator, a counter, and a storage unit; the lens focusing assembly further comprises an image processing unit configured to obtain a first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value so as to adjust a focal length of the lens. According to the focusing method, the lens focusing assembly and the image sensor, the quantized relative values of the pixel circuits on different sides are obtained, the focusing application requirement of a high frame rate can be met, and the area and the power consumption are saved.

Description

Lens focusing assembly and image sensor

Technical Field

The application relates to the technical field of imaging, in particular to a lens focusing assembly and an image sensor.

Background

The image sensor converts the light image on the light sensing surface into an electric signal in a proportional relation with the light image by utilizing the photoelectric conversion function of the photoelectric device. In contrast to the photosensitive elements of "point" light sources such as photodiodes, phototransistors, etc., image sensors are functional devices that divide the light image on their light-receiving surface into many small cells and convert it into usable electrical signals. The exposure mode of the existing image sensor comprises a plurality of modes such as a rolling shutter, a global shutter and the like, and the image sensor is gradually developed to have the characteristics of small volume, light weight, high integration level, high resolution, low power consumption, long service life, low price and the like, and is widely applied to various industries.

In the course of conceiving and implementing the present application, the inventors found that at least the following problems existed: the automatic focusing technology plays an important role in the image sensor, and especially when consumer electronics such as mobile phones are used for shooting, the automatic focusing technology can greatly improve user experience. The Phase Detection Auto Focus (PDAF) technology is widely applied to high-end CMOS image sensor chips, and its main principle is: some pixel points are selected in a pixel array as phase detection pixels, and the left half and the right half (or the upper half and the lower half) of the phase detection pixels are respectively shielded by special materials, so that the phase detection pixels are equivalent to the left eye and the right eye of a person, the left phase information and the right phase information of incident light can be respectively obtained during reading, and the amount of movement of a lens can be calculated through an algorithm, so that automatic focusing is realized. The disadvantages of this approach are: the pixels used for phase detection cannot be imaged normally, and algorithm compensation is performed on the actual image according to the imaging information of the surrounding pixels, so the number of pixels used for phase detection cannot be too large (e.g., 3% or 6%PDAF); and the amount of light entering is small in a dim light condition, which may result in insufficient accuracy of phase detection and compensation.

Disclosure of Invention

In order to alleviate the above problems, the present application provides a lens focusing assembly, specifically, the lens focusing assembly comprising:

the pixel unit comprises a floating diffusion point, a first side pixel circuit and a second side pixel circuit, wherein the output end of the first side pixel circuit and the output end of the second side pixel circuit are connected to the floating diffusion point together, so that a reset signal, a pixel signal of the first side pixel circuit and pixel signals of the first side pixel circuit and the second side pixel circuit are respectively output to the quantization circuit through the floating diffusion point;

wherein the quantization circuit comprises:

a comparator connected to an output of the pixel unit, the comparator configured to quantize a signal output by the pixel unit;

a counter connected to an output of the comparator, the counter configured to count a signal output by the comparator;

a storage unit including a first memory and a second memory, an input terminal of the first memory being connected to an output terminal of the counter to store a reset quantization value corresponding to the reset signal, and an input terminal of the second memory being connected to an output terminal of the counter to store a first pixel quantization relative value corresponding to the reset signal and a pixel signal of the first side pixel circuit, or to store a second pixel quantization relative value corresponding to the reset signal, the pixel signal of the first side pixel circuit, and a pixel signal of the second side pixel circuit;

the lens focusing assembly further comprises an image processing unit configured to obtain a first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value so as to adjust a focal length of the lens.

Optionally, the counter includes a counting unit composed of a selection module, a logic control module and a trigger;

the first input end of the selection module is connected with the output end of the first memory, the second input end of the selection module is connected with a trigger signal, and the selection module is configured to be triggered by a selection control signal to be conducted and selectively output an output signal of the first memory or the trigger signal;

the input end of the logic control module is connected with the selection module, and the output end of the logic control module is connected with the clock input end of the trigger;

the output end of the trigger is connected with the input end of the trigger, and the output end of the trigger is configured as the output end of the counter.

Optionally, the selection module is an alternative data selector.

Optionally, the logic control module includes a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, and a third NMOS;

a control end of the first PMOS is connected with a first control signal, a first end of the first PMOS is connected with a preset voltage, and a second end of the first PMOS is connected with a first end of the second PMOS and a first end of the third PMOS;

the control end of the second PMOS is accessed to a second control signal, the second end of the second PMOS is connected with the second end of the third PMOS, the first end of the first NMOS and the first end of the second NMOS, and the output signal of the logic control module is output;

the control end of the third PMOS switching element is connected to the output signal of the selection module;

the control end of the first NMOS is connected to the output signal of the selection module, and the second end of the first NMOS is connected with the first end of the third NMOS;

the control end of the second NMOS is connected to the first control signal, the control end of the third NMOS is connected to the second control signal, and the second end of the second NMOS and the second end of the third NMOS are grounded.

Optionally, the pixel unit further includes a reset switch, a source follower switch, and a row selection switch, the floating diffusion point is connected to a preset voltage through the reset switch, and the pixel signal is amplified by the source follower switch and output through the row selection switch.

Optionally, the counter includes a first counting unit to an nth counting unit in cascade, where n is an integer greater than 1;

the output end of the first counting unit is correspondingly connected with the first bit value input end of the storage unit, the output end of the nth counting unit is correspondingly connected with the nth bit value input end of the storage unit, the first counting unit takes a clock control signal as the trigger signal, and the output signal of the output end of the trigger in the upper-level counting unit of the nth counting unit is the trigger signal.

Optionally, when the rising edge trigger is set, the counter further includes an odd number of inverters, and the odd number of inverters are connected in series at the output end of the flip-flop and output a signal inverted from the output end of the flip-flop to implement subtraction counting.

Optionally, when the falling edge trigger is set, the counter further includes an even number of inverters, the even number of inverters are connected in series to the output end of the flip-flop, and output a signal in phase with the output end of the flip-flop to implement the addition counting.

The application also provides an image sensor, in particular comprising any one of the lens focusing assemblies as described above.

As described above, the lens focusing assembly and the image sensor provided by the application use a set of quantization circuits, and acquire the quantization relative values of the pixel circuits on different sides for focusing based on two times of reset quantization of the same counter, so that the focusing application requirement of a high frame rate can be met, and the area and the power consumption are saved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a block diagram of a basic structure of an image sensor system.

Fig. 2 is a circuit diagram of a pixel unit according to an embodiment of the present application.

Fig. 3 is a pixel circuit diagram of a two-way photosensitive pixel sharing structure according to an embodiment of the present application.

Fig. 4 is a pixel circuit diagram of a four-way photosensitive pixel sharing structure according to an embodiment of the present disclosure.

Fig. 5 is a flowchart of a lens focusing method according to an embodiment of the present application.

Fig. 6 is a structural diagram of a lens focusing assembly according to an embodiment of the present application.

Fig. 7 is a block diagram of a quantization circuit according to the embodiment of fig. 6.

Fig. 8 is a block diagram of a counter according to the embodiment of fig. 7.

Fig. 9 is a circuit diagram of a logic control module according to the embodiment of fig. 8.

Fig. 10 is a circuit diagram of a counter according to the embodiment of fig. 8.

Fig. 11 is a timing diagram illustrating a method for focusing a lens by an image sensor according to the embodiment of fig. 10.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of a claim "comprising a" 8230a "\8230means" does not exclude the presence of additional identical elements in the process, method, article or apparatus in which the element is incorporated, and further, similarly named components, features, elements in different embodiments of the application may have the same meaning or may have different meanings, the specific meaning of which should be determined by its interpretation in the specific embodiment or by further combination with the context of the specific embodiment.

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The following detailed description is provided for the purpose of illustrating the present disclosure in connection with the accompanying drawings. Fig. 1 is a block diagram of a basic structure of an image sensor system.

As shown in fig. 1, the image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to a pixel array 101.

The functional logic unit 103 is connected to the readout circuit 102, and performs logic control of reading of the pixel circuit. The readout circuit 102 and the control circuit 104 are connected to a status register 105, and read control of the pixel array 101 is realized. The pixel array 101 includes a plurality of pixel units in rows (R1, R2, R3 \8230; ry) and columns (C1, C2, C3 \8230; cx), and pixel signals output from the pixel array 101 are output to the readout circuit 102 through column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out by the readout circuit 102 whose status register 105 designates the readout mode, and then transferred to the functional logic unit 103. In particular applications, the readout circuit 102 may include analog-to-digital conversion (ADC) circuits, amplification circuits, and others. In some embodiments, the status register 105 may include a program selection system for determining whether the read system is read in a rolling shutter mode or a global shutter mode. The function logic unit 103 may store only image data or image data applied or processed by an image effect. In one application, readout circuitry 102 may read out a row of image data at a time along readout column lines (as shown in FIG. 1), or may read out the image data in a variety of other ways. The operation of the control circuit 104 may be determined by the current setting of the status register 105. For example, the control circuit 104 generates a shutter signal for controlling image acquisition. In some applications, the shutter signal may be a global exposure signal such that all pixels of the pixel array 101 simultaneously acquire their image data through a single acquisition window. In some other applications, the shutter signal may be a rolling exposure signal, and each pixel row is sequentially read through the capture window.

First embodiment

Fig. 2 is a circuit diagram of a pixel unit according to an embodiment of the present application. The pixel array of the image sensor includes a plurality of pixel units arranged in rows and columns as shown in fig. 2, and each photosensitive pixel in each pixel unit includes a photosensitive diode PD and a transfer switching device TX that transfers electrons generated by the photosensitive diode PD through a photoelectric effect to a floating diffusion FD connected to a predetermined voltage PIXVDD through a reset switching device RST. The dual conversion gain control unit includes a conversion gain switching part DCG and a complementary capacitor Cdcg connected between the reset switching part RST and the floating diffusion point FD for implementing the pixel circuit to operate in a low conversion gain or high conversion gain mode according to a control signal.

The pixel signal is amplified by the source follower switch SF and output to the column line (pixel out output) via the row selection switch RS. In another embodiment, the pixel unit may be a photosensitive pixel employing a shared structure.

Second embodiment

As shown in fig. 3, the photodiode PD1 and the transfer switching element TX1 constitute a photosensitive pixel of a shared structure with the photodiode PD2 and the transfer switching element TX2, and are shared and connected to the floating diffusion FD. The pixel unit adopting the sharing structure can reduce the number of switching elements in the pixel circuit and reduce the design area of a chip; understandably, the area of the photosensitive area can be increased under the condition that the design area of the pixel circuit is not changed, so that the light sensitivity of the pixel circuit is improved, and the performance of the pixel circuit is improved. The drawings and embodiments presented herein are not limited to the two-way photosensitive pixel sharing mode, and in some embodiments, a four-way photosensitive pixel sharing structure design may be adopted, as shown in fig. 4, and fig. 4 is a pixel circuit diagram of a four-way photosensitive pixel sharing structure in an embodiment of the present disclosure. The photosensitive pixel sharing units are connected by PD1 and TXA, PD2 and TXB, PD3 and TXC, and PD4 and TXD in a four-way sharing structure and share a floating diffusion point FD.

With continued reference to fig. 2, the supplemental capacitance Cdcg may be a device capacitance or a parasitic capacitance of the connection point of the reset switch RST and the conversion gain switch DCG to ground. In the embodiment shown in fig. 2 as the device capacitance, the other pole of the supplementary capacitance Cdcg is connected to the voltage VC. In another embodiment, the supplementary capacitance Cdcg is a parasitic capacitance of the connection point of the reset switching element RST and the conversion gain switching element DCG to ground, and the other pole of the capacitance may be grounded.

Third embodiment

As shown in fig. 5, the pixel unit includes a first side pixel circuit and a second side pixel circuit, the pixel unit is connected to a quantization circuit, and the quantization circuit includes a counter.

In one embodiment, a lens focusing method includes:

s10: and resetting the counter to a state to be read for the first time.

Before the counter starts to count, the counter is reset to the initial state of the count value, so as to avoid the counting from starting at an unknown value. Alternatively, in the counter reset operation, the reset and quantization operations may be performed on the pixel circuit to reset the counter to the reset quantization value of the pixel circuit, or the counter may be directly set to the reset quantization value of the pixel circuit.

S20: and starting a first side pixel reading mode, and controlling a counter to quantize a pixel signal of a first side pixel circuit so as to acquire and store a first pixel quantization relative value.

Illustratively, the pixel signal of the first side pixel circuit is quantized based on the counter after the reset operation. The first side pixel circuit is not limited in the present application, and may be selected from any one of a left side pixel circuit, a right side pixel circuit, an upper side pixel circuit, and a lower side pixel circuit.

S30: and resetting the counter to a state to be read for the second time.

Before starting the second counting operation, the counter is reset to the initial state of the counting value, so as to avoid the second counting starting from the unknown value. Alternatively, in the counter reset operation, the reset and quantization operations may be performed on the pixel circuit to reset the counter to the reset quantization value of the pixel circuit, or the counter may be directly set to the reset quantization value of the pixel circuit.

S40: and starting a first side pixel reading mode and a second side pixel reading mode, and controlling a counter to quantize pixel signals of a first side pixel circuit and a second side pixel circuit so as to acquire and store a second pixel quantization relative value.

Illustratively, the pixel signal of the second-side pixel circuit is quantized based on a counter after the reset operation. The second side pixel circuit is not limited in the present application, and optionally, the second side pixel circuit is different from the first side pixel circuit and may be selected from any one of a left side pixel circuit, a right side pixel circuit, an upper side pixel circuit, and a lower side pixel circuit. Illustratively, the second side pixel circuit is another side pixel circuit corresponding to the first side pixel circuit in the pixel unit. In other embodiments, the pixel area may be divided into more areas according to the direction, which is not limited in this application.

S50: and acquiring first phase results of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value.

For example, calculating the difference between the first pixel quantized relative value and the second pixel quantized relative value may obtain the phase result of the two-side pixel circuit to assist the lens to focus. Alternatively, the image information may be obtained by adding the first pixel quantization relative value and the second pixel quantization relative value.

S60: and adjusting the focal length of the lens according to the first phase result.

In this embodiment, the lens focusing method can read the phase result of the pixel circuits on both sides of the pixel unit through two reset operations in the quantization process of the counter in one set of quantization circuits, thereby not only realizing 100% of omnidirectional automatic focusing, but also greatly saving the area and power consumption of the chip.

In one embodiment, the lens focusing method performs S10: the step of resetting the counter to a state to be read for the first time comprises:

s11: starting a reset mode, and controlling a counter to quantize a reset signal so as to obtain and store a reset quantized value;

s12: the reset quantization value in the counter is inverted.

Illustratively, before reading the charges induced by the photosensitive material, the floating diffusion node and the related peripheral circuits are subjected to charge cleaning reset, so that the circuit noise interference can be effectively eliminated, and the photosensitive quality and the reading accuracy are ensured.

In one embodiment, the lens focusing method performs S20: the method for starting the first side pixel reading mode and controlling the counter to quantize the pixel signal of the first side pixel circuit to acquire and store the first pixel quantization relative value comprises the following steps:

s21: and starting a first side pixel reading mode, and based on the reversed reset quantization value, controlling a counter to quantize the pixel signal of the first side pixel circuit so as to obtain and store the sum of the reversed reset quantization value and the first side pixel quantization value.

Resetting the quantized value may be understood as initial noise in the pixel circuit. Illustratively, a first pixel quantization value is read, and the sum of the reset quantization value after inversion and the first pixel quantization value is calculated as a first pixel quantization relative value which is a first side pixel quantization real value of the image signal after the initial noise is removed. The first pixel quantized relative value represents a difference in the amount of charge induced in the first side pixel circuit in two different states.

In one embodiment, the lens focusing method performs S30: the step of resetting the counter to the state to be read for the second time comprises the following steps:

s31: reading a reset quantization value and writing the reset quantization value into a counter;

s32: the reset quantization value in the counter is inverted.

Resetting the quantized value may be understood as initial noise in the pixel circuit. Illustratively, other pixel quantization values are read, and the sum of the reset quantization value after inversion and other pixel quantization values is calculated to be other pixel quantization relative values which are other side pixel quantization real values of the image signal after the initial noise is removed. The other pixel quantized relative values represent the difference in the amount of charge induced by the other side pixel circuits in the two different states.

The reset quantization value stored during the first reset is read, then the counter inverts the reset quantization value, and the counter only needs to invert in the quantization process, so that the secondary reset quantization operation of the pixel circuit is avoided, and the focusing time is greatly saved.

In one embodiment, the lens focusing method performs S40: the method for starting the reading mode of the first side pixel and the second side pixel and controlling the counter to quantize the pixel signals of the first side pixel circuit and the second side pixel circuit so as to acquire and store the quantization relative value of the second pixel comprises the following steps:

s41: and starting a reading mode of the first side pixel and the second side pixel, and based on the reversed reset quantization value, controlling a counter to quantize pixel signals of the first side pixel circuit and the second side pixel circuit so as to obtain and store the sum of the reversed reset quantization value, the first side pixel quantization value and the second side pixel quantization value.

Illustratively, the first side pixel circuit and the second side pixel circuit are quantized simultaneously to obtain a sum of the first side pixel quantization value and the second side pixel quantization value. And calculating the sum of the reset quantized value after inversion, the first side pixel quantized value and the second side pixel quantized value as a second pixel quantized relative value. The second pixel quantized relative value represents a quantized result of the amount of induced charge after noise is removed from the entire pixel circuit in the in-focus state.

In one embodiment, the lens focusing method performs S50: in the step of obtaining the first phase result of the first side pixel circuit and the second side pixel circuit based on the first pixel quantization relative value and the second pixel quantization relative value, the second side pixel quantization value is calculated according to the following expression:

P＝P ₂ -P ₁

wherein P is the second side pixel quantization value, P ₁ Quantizing the relative value, P, for the first pixel ₂ The relative value is quantized for the second pixel.

Illustratively, the second pixel quantization relative value is a sum of the reset-after-inversion quantization value, the first side pixel quantization value and the second side pixel quantization value, the first pixel quantization relative value is a sum of the reset-after-inversion quantization value and the first side pixel quantization value, and a difference between the second pixel quantization relative value and the first pixel quantization relative value is the second pixel quantization value. The difference between the second pixel quantization value and the first pixel quantization value is a second side pixel quantization value. Optionally, an offset value of focusing of the lens is obtained according to the phase difference information of the first phase result, so as to achieve accurate focusing.

In an embodiment, the lens focusing method further includes: the reset quantized value is stored in a first memory, and the first pixel quantized relative value and/or the second pixel quantized relative value is stored in a second memory.

Illustratively, the reset and pixel quantized values are stored in different memories to facilitate subsequent simultaneous reading of the reset and pixel quantized values.

Fifth embodiment

On the other hand, the present application further provides a lens focusing assembly, and fig. 6 is a structural diagram of the lens focusing assembly according to an embodiment of the present application.

Referring to fig. 6, in an embodiment, a lens focusing assembly includes:

the pixel unit 10, the pixel unit 10 includes a floating diffusion point (not shown), a first side pixel circuit 11 and a second side pixel circuit 12, an output terminal of the first side pixel circuit 11 and an output terminal of the second side pixel circuit 12 are commonly connected to the floating diffusion point to output a reset signal, a pixel signal of the first side pixel circuit 11 and the second side pixel circuit 12 to the quantization circuit 20 through the floating diffusion point respectively.

Referring to the embodiment of fig. 2, optionally, the pixel unit 10 further includes a reset transistor, a source follower transistor, a row selection transistor, and the like, which are not described herein again.

Referring to fig. 6 and 7 in combination, the quantization circuit 20 includes: a comparator 21 connected to an output of the pixel unit 10, the comparator 21 being configured to quantize a signal output by the pixel unit 10. And a counter 22 connected to an output terminal of the comparator 21, the counter 22 being configured to count a signal output from the comparator 21. And a storage unit 23, wherein the storage unit 23 comprises a first memory 231 and a second memory 232, an input terminal of the first memory 231 is connected to the output terminal of the counter 22 to store a reset quantization value corresponding to the reset signal, and an input terminal of the second memory 232 is connected to the output terminal of the counter 22 to store a first pixel quantization relative value corresponding to the reset signal and the pixel signal of the first side pixel circuit, or store a second pixel quantization relative value corresponding to the reset signal, the pixel signal of the first side pixel circuit and the pixel signal of the second side pixel circuit.

Illustratively, the first memory 231 and the second memory 232 receive the quantized values output by the quantization circuit 20 in a parallel connection.

With reference to fig. 6, the lens focusing assembly further includes an image processing unit 30, and the image processing unit 30 is configured to obtain the first phase result of the first side pixel circuit and the second side pixel circuit according to the first pixel quantization relative value and the second pixel quantization relative value, so as to adjust the focal length of the lens.

Optionally, the lens focusing assembly further comprises a readout circuit, and an output terminal of the second memory 232 may be connected to the readout circuit, and the readout circuit transmits a signal output by the second memory 232 to the image processing unit 30.

In this embodiment, the lens focusing assembly uses a set of quantization circuits 20, and obtains quantized relative values of pixel circuits on different sides for focusing based on two reset quantization operations of the same counter 22, so as to meet the requirement of high frame rate focusing application and save area and power consumption.

Fig. 8 is a block diagram of a counter according to the embodiment of fig. 7.

Referring to fig. 7 and 8 in combination, in one embodiment, the counter 22 includes a counting unit consisting of a selection module 220, a logic control module 221 and a flip-flop 222.

The first input terminal of the selection module 220 is connected to the output terminal of the first memory 231, the second input terminal of the selection module 220 is connected to the trigger signal, and the selection module 220 is configured to be triggered by the selection control signal to be turned on and selectively output the output signal or the trigger signal of the first memory 231. The input end of the logic control module 221 is connected to the selection module 220, and the output end of the logic control module 221 is connected to the clock input end of the flip-flop 222. The output of the flip-flop 222 is connected to the input of the flip-flop 222, and the output of the flip-flop 222 is configured as the output of the counter 22.

Illustratively, during the reset signal quantization process, the selection module 220 in the counter 22 outputs a trigger signal for the reset signal quantization to the logic control module 221. The logic control module 221 receives the trigger signal and transmits a count signal to the flip-flop 222. The flip-flop 222 receives the counting signal to perform the quantization counting, and the counting result is written into the first memory 231 as the quantization value of the reset signal. During the second reset of the counter, the selection module 220 is switched to the trigger signal by the selection control signal to make the counter 22 enter the write-back state, and the reset quantization value in the first memory 231 is output to the logic control module 221 through the selection module 220. The logic control module 221 receives the reset quantization value and inverts it, and then writes it into the flip-flop 222 as the basis for the quantization count of the image signal.

In one embodiment, the selection module 220 is an alternative data selector.

Alternatively, the selecting module 220 may be a selector that selects and outputs two signals according to a selection control signal, and the type of the selector is not limited in the present application.

Fig. 9 is a circuit diagram of a logic control module according to the embodiment of fig. 8. Fig. 10 is a circuit diagram of a counter according to the embodiment of fig. 8. Fig. 11 is a timing chart of an image sensor implementing a lens focusing method in one cycle according to the embodiment of the present application and fig. 10.

Referring to fig. 9, in an embodiment, the logic control module 221 includes a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, and a third NMOS. In the figure, P1 denotes a first PMOS, P2 denotes a second PMOS, P3 denotes a third PMOS, N1 denotes a first NMOS, N2 denotes a second NMOS, and N2 denotes a third NMOS.

The control end of the first PMOS is connected with a first control signal (clk _ rstb), the first end of the first PMOS is connected with a preset voltage, and the second end of the first PMOS is connected with the first end of the second PMOS and the first end of the third PMOS. The control terminal of the second PMOS is connected to the second control signal (clk _ ctrl), and the second terminal of the second PMOS is connected to the second terminal of the third PMOS, the first terminal of the first NMOS, and the first terminal of the second NMOS, and outputs the output signal (clkbi) of the logic control module 221. And the control end of the third PMOS switch element is connected to an output signal (di) of the selection module. The control end of the first NMOS is connected to the output signal (di) of the selection module, and the second end of the first NMOS is connected to the first end of the third NMOS. The control end of the second NMOS is connected with a first control signal (clk _ rstb), the control end of the third NMOS is connected with a second control signal (clk _ ctrl), and the second end of the second NMOS and the second end of the third NMOS are grounded.

In this embodiment, the logic function between the output signal clkbi and the input signals di, clk _ ctrl, clk _ rstb of the logic control module 221 is as follows:

alternatively, the logic control module may be implemented by the and or logic described above, or may be implemented by other logic, such as an and or logic, or may implement the same function by using a and/or and or logic, and the flip-flop is changed to be triggered by a rising edge, so that the specific configuration of the logic control module of the present application is not limited herein.

Referring to fig. 9-11, during the operation of the logic control module 221, the first control signal (clk _ rstb) and the second control signal (clk _ ctrl) can output the same-phase signal of the output signal (di) of the selection module when the pixel circuit is quantized and counted, and output the opposite-phase signal of the output signal (di) of the selection module when the selection module 220 reads the reset quantization value from the first memory 231 and transmits the reset quantization value. Illustratively, the logic control module 221 receives the reset quantization value from the selection module 220 and inverts the reset quantization value during a second reset of the counter before sending the reset quantization value to the flip-flop 222.

Referring to fig. 10, in an embodiment, the counter 22 includes a cascade of a first counting unit to an nth counting unit, where n is an integer greater than 1.

The output end of the first counting unit is correspondingly connected with the first bit value input end of the storage unit, the output end of the nth counting unit is correspondingly connected with the nth bit value input end of the storage unit, the first counting unit takes a clock control signal as a trigger signal, and the output signal of the output end of the trigger in the upper-stage counting unit of the nth counting unit is taken as the trigger signal.

Optionally, the clock control signal is provided by an internal phase locked loop. In order to increase loading capacity or realize different calculations, when rising edge triggering is set, signals of the same phase as the output of odd inverters and the Q end of the trigger can be connected in series at the QB end of the trigger to realize subtraction counting; when the falling edge trigger is set, no inverter or even number of inverters can be added in series at the QB end of the trigger, and a signal in phase with the QB end of the trigger is output to realize addition counting.

As shown in fig. 10, no inverter is provided between the flip-flop in each counting unit and the selection module of the next-stage counting unit; in other embodiments, two inverters can be arranged between the trigger in each counting unit and the selection module of the next counting unit. The driving loading capacity of the output signal to the memory is increased on the premise of not changing the output signal by adding two inverters for twice inversion.

Illustratively, when the counter 22 is in the cascade state, the Q terminal of the flip-flop of the previous stage counting unit is connected to the CK terminal of the flip-flop of the next stage counting unit, and the Q terminal of the flip-flop of the previous stage counting unit is connected to the CK terminal of the flip-flop of the next stage counting unit, so that the count is up-down. The present application is not limited to this, and preferably, the count is added, and in the case of the count is subtracted, one inverter may be added.

Sixth embodiment

The application also provides an image sensor, in particular comprising the lens focusing assembly.

The present application further provides an image sensor, in particular comprising a processor and a storage medium connected to each other, wherein: the storage medium is used for storing a computer program. The processor is used to execute a computer program to implement the lens focusing method as described above.

In one embodiment, referring to fig. 4, the pixel unit includes 4 pixels, wherein the 4 pixels are arranged in a 2 × 2 manner and share the transistors FD, SF, RS, RST, and the like.

Referring to fig. 7, the quantization circuit mainly includes a ramp generator (not shown), a comparator, a counter and a storage unit, wherein a row of quantization circuits corresponds to a row of pixel units.

Referring to fig. 10 and 11 in combination, for example, assuming that the counter includes n counting units, the step of the image sensor performing the lens focusing method includes:

count at time t0The counter reset signal count _ rstb is high, and the counter ends the reset state and enters the count state. clk _ rstb is low, clk _ ctrl is high, and clk _ ctrl _ logic is in cascade when the modules are in cascade

At the time of t1, the vramp ramp voltage starts to fall, the count enable count _ en starts to count, and when the vramp ramp voltage and pixout are overlapped, the comparator outputs 0, counting is stopped, and a reset signal quantization value is obtained; at the moment of t2, the quantization of the reset signal is finished, and the vramp ramp voltage begins to return to a reference state;

at the time t3 to t4, a reset memory writing signal rst _ wwl is in a high level, and a reset signal quantized value obtained by quantizing the counter is written into the reset memory.

At time t5, the clk _ ctrl signal is low, the clk _ rstb signal is low, and clkbi is set to "1". At time t6, clk _ rstb goes high, clkbi transitions from "1" to 0, and the quantized value of the reset signal stored in the counter is inverted. At time t7, clk _ rstb is set to low, clk _ ctrl is set to high, and clk _ ctrl _ logic modules are in cascade connection, at which time

At the time of t8, the ramp voltage starts to fall, the count enable count _ en starts to count, when the ramp voltage and pixout are overlapped, the comparator outputs 0, counting is stopped, and the difference value Vsigr-Vrst of the right pixel image signal and the reset signal is obtained; at time t9, the right pixel image signal quantization is finished, and the vramp ramp voltage starts to return to the reference state.

At times t10 to t11, the read memory write signal cds _ wwl is at a high level, and the difference Vsigr-Vrst between the right pixel image signal quantized by the counter and the reset signal is written into the read memory and read.

At time t12 clk _ rstb is set high and clkbi is set to "0". the count _ rstb is set to be a low level at the time t13, and each stage of trigger of the counter is reset to be 0; and rwt _ ctrl is set to be high, di is switched to be output of the reset memory under mux selection, and the counter enters a write-back state. At time t14, count _ rstb goes high and the counter is reset.

At time t15, the clk _ rstb signal is set low, the clk _ ctrl signal is set low, and clkbi is set to "1". At time t16, the clk _ ctrl signal is set to high, and the quantized value of the reset signal stored in the reset memory is written back into the counter.

At time t17 clk _ ctrl signal is low, clk _ rstb signal is low, and clkbi is set to "1". At time t18 clk _ rstb goes high, clkbi transitions from "1" to "0", and the reset signal value stored in the counter is inverted. At time t19, the clk _ ctrl signal is set to high, the rt _ ctrl is set to low, di is switched to the output of the previous stage flip-flop under mux selection, and the counter enters a counting state. At time t20, the clk _ rstb signal is low and the clk _ ctrl _ logic module is in cascade.

At the time of t21, the ramp voltage begins to fall, the count enable count _ en begins to count, when the ramp voltage and pixout are overlapped, the comparator outputs 0, counting is stopped, and the difference value Vsigr + Vsigl-Vrst between an image signal (namely the sum of left and right pixel image signals) and a reset signal is obtained; i.e. the image quantization values of the correlated double samples. At time t22, the quantization of the image signal ends, and the vramp ramp voltage starts to return to the reference state.

the read memory write signal cds _ wwl is at a high level from time t22 to time t23, and the difference Vsigr + Vsigl-Vrst between the image signal and the reset signal quantized by the counter is written into the read memory and read.

In the process of the embodiment, the pixel output of the pixel array reads the reset signal, the right pixel image signal and the image signal in sequence in one quantization period, and the readout circuit performs quantization processing on the signals, so as to realize 100% full-automatic phase focusing of the image sensor.

Seventh embodiment

The present application also provides a storage medium, in particular, a storage medium having stored thereon a computer program, which when executed by a processor, implements the lens focusing method as described above.

Illustratively, the steps of the computer program executed by the processor for the lens focusing method include:

a monoclinic ADC (analog to digital converter) consisting of a slope generator, a comparator and a counter quantizes a reset signal Vrst at first, and a quantized result is stored in a reset memory; and then controlling a clk _ ctrl _ logic module to perform inversion operation on the quantization result stored in the counter to obtain an inversion of the Vrst signal quantization result, quantizing the right pixel signal Vsigr by the counter to obtain a quantization result of Vsigr-Vrst, and storing the result into a read-out memory. The counter is then reset to 0, the MUX, under the control of the rwt _ ctrl signal, taps the value stored in the reset memory to the input of the clk _ ctrl _ logic module, which then controls the clk _ ctrl _ logic module to write back the value stored in the reset memory into the counter; the sum Vsigr + Vsigl (i.e. image signal) of the left and right pixel signals is then quantized by a counter to obtain a quantized result of Vsigr + Vsigl-Vrst, which is stored in a read-out memory. In this process, the reset signal Vrst needs to be quantized once, and the pixel signals Vsig read out twice are time-multiplexed by one set of counters, so that only one set of readout circuits is needed. And according to the left pixel information and the image information, the left pixel information is subtracted from the image information to obtain left and right pixel information, and the phase difference can be obtained by comparing the left and right pixel information to perform automatic focusing. The lens focusing method is suitable for an analog-to-digital converter structure and a conversion method of 100% -ADAF, a set of memory is added on the basis of the traditional single-slope ADC for storing the value of a reset signal Vrst, a clk _ ctrl _ logic module is introduced into a counter, the input clock of a DFF is controlled, the counter can perform the operation of writing CDS and RST values back into the counter, and therefore the CDS and the ADAF can be compatible at the same time. The area of a quantization circuit is effectively reduced, and the effect of improving the frame rate is realized.

As described above, the lens focusing method, the lens focusing assembly, the image sensor and the storage medium provided by the application can realize the focusing application requirement of a high frame rate by using one set of quantization circuit based on the manner of obtaining the quantization relative values of the pixel circuits on different sides for focusing by two times of reset quantization of the counter, thereby saving the area and the power consumption.

In the embodiments of the image sensor and the storage medium provided in the present application, all technical features of any one of the above-described method embodiments may be included, and the expanding and explaining contents of the specification are basically the same as those of the above-described method embodiments, and are not described herein again.

Embodiments of the present application also provide a computer program product, which includes computer program code, when the computer program code runs on a computer, the computer is caused to execute the method in the above various possible embodiments.

Embodiments of the present application further provide a chip, which includes a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device in which the chip is installed executes the method in the above various possible embodiments.

It is to be understood that the foregoing scenarios are only examples, and do not constitute a limitation on application scenarios of the technical solutions provided in the embodiments of the present application, and the technical solutions of the present application may also be applied to other scenarios. For example, as can be known by those skilled in the art, with the evolution of system architecture and the emergence of new service scenarios, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.

In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.

In the present application, each embodiment is described with emphasis, and reference may be made to the description of other embodiments for parts that are not described or illustrated in any embodiment.

The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all the equivalent structures or equivalent processes that can be directly or indirectly applied to other related technical fields by using the contents of the specification and the drawings of the present application are also included in the scope of the present application.

Claims

1. A lens focusing assembly, comprising:

wherein the quantization circuit comprises:

a storage unit, including a first memory and a second memory, wherein an input terminal of the first memory is connected to an output terminal of the counter to store a reset quantization value corresponding to the reset signal, and an input terminal of the second memory is connected to an output terminal of the counter to store a first pixel quantization relative value corresponding to the reset signal and a pixel signal of the first side pixel circuit, or store a second pixel quantization relative value corresponding to the reset signal, the pixel signal of the first side pixel circuit, and a pixel signal of the second side pixel circuit;

2. The lens focusing assembly of claim 1, wherein the counter includes a counting unit consisting of a selection module, a logic control module and a flip-flop;

3. The lens focusing assembly of claim 2, wherein the selection module is an alternative data selector.

4. The lens focusing assembly of claim 2, wherein the logic control module comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, and a third NMOS;

5. The lens focusing assembly of claim 2, wherein the pixel unit further includes a reset switch, a source follower switch, and a row selection switch, the floating diffusion is connected to a preset voltage through the reset switch, and a pixel signal is amplified through the source follower switch and output through the row selection switch.

6. The lens focusing assembly of any one of claims 2 to 5, wherein the counter includes a cascade of a first counting unit to an nth counting unit, where n is an integer greater than 1;

7. The lens focusing assembly of claim 6, wherein when the rising edge trigger is set, the counter further comprises an odd number of inverters connected in series at an output terminal of the flip-flop, and outputting a signal inverted from an output terminal of the flip-flop to perform a down-count.

8. The lens focusing assembly as claimed in claim 6, wherein the counter further comprises an even number of inverters connected in series at the output terminal of the flip-flop when the falling edge trigger is set, outputting a signal in phase with the output terminal of the flip-flop to perform the addition count.

9. An image sensor comprising the lens focusing assembly of any one of claims 1 to 8.