KR101107768B1 - Wide Dynamic Range CMOS Image Sensor - Google Patents

Abstract

The unit pixel of the CMOS image sensor of the present invention comprises a matrix of unit pixels; And an output signal line provided for each column of the matrix,
The unit pixel may include a light receiving element; A first sensing circuit converting the amount of charge accumulated in the light receiving element during a first exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the output signal line; A second sensing circuit converting the amount of charge accumulated in the light receiving element during a second exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the output signal line; A first switch provided between the analog-digital converter for the first sensing circuit and the output signal line; And a second switch provided between the analog digital converter for the second sensing circuit and the output signal line.

Description

Wide Dynamic Range CMOS Image Sensor

The present invention relates to a CMOS image sensor having a wide dynamic range with respect to the brightness of light and a unit pixel constituting the CMOS image sensor.

The present invention relates to a pixel structure of a sensor designed to make CMOS image sensors operating in a wide dynamic range with respect to light brightness, and a method of obtaining an image signal according to the structure.

A Complementary Metal Oxide Semiconductor (CMOS) image sensor is a sensor manufactured using CMOS fabrication technology, which converts light incident to each pixel of the sensor into electrons using a photodiode, which is proportional to the number of electrons. It is an image sensor that outputs a voltage signal.

The typical CMOS image sensor's dynamic range is about 60 dB. In other words, a signal can be output by reacting normally from light with minimum brightness that can be sensed to light that is about 1000 times brighter. Conventionally, various methods for extending the dynamic range of CMOS image sensors have been proposed.

For example, US Patent US 7443427 discloses a pixel structure having a logarithmic dynamic range with respect to light, and US Patent Nos. US 7442910 and US 7209166 switch capacitors which are electron storage sites inside a pixel. It suggests how to increase the dynamic range by changing it through manipulation.

In addition, Korean Patent Nos. 0835894, 0865111, and US Pat. No. 7,489,352 disclose a method of constructing two photodiodes, large and small, and outputting two signals having different responsiveness to light therefrom.

In the process of acquiring a signal from a commonly used 4-transistor structure pixel, a method of extending a dynamic range of a sensor by operating a transfer gate or a reset transistor several times has been published.

These various solutions are in contrast to their advantages and disadvantages, which is not a clear technology.

An object of the present invention is to provide a CMOS image sensor and a unit pixel thereof having a wide dynamic range with respect to sensitivity and simple image processing.

Another object of the present invention is to provide a CMOS image sensor and a unit pixel thereof having a wide dynamic range in both a rolling shuttering method and a global shuttering method.

It is still another object of the present invention to provide a CMOS image sensor that does not require any additional process other than a process for fabricating a conventional 4-transistor CMOS image sensor pixel to fabricate a pixel of a CMOS image sensor having a wide dynamic range. To provide the unit pixel.

CMOS image sensor according to an aspect of the present invention, the matrix of unit pixels; And an output signal line provided for each column of the matrix,

The unit pixel may include a light receiving element; A first sensing circuit converting the amount of charge accumulated in the light receiving element during a first exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the output signal line; A second sensing circuit converting the amount of charge accumulated in the light receiving element during a second exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the output signal line; A first switch provided between the analog-digital converter for the first sensing circuit and the output signal line; And a second switch provided between the analog digital converter for the second sensing circuit and the output signal line.

Here, the first sensing circuit or the second sensing circuit, the floating diffusion region; A transfer transistor for transferring charges accumulated in the light receiving element to the floating diffusion region; A reset transistor for resetting the floating diffusion region; An active transistor for detecting electrical characteristics of the floating diffusion region; And an addressing transistor for outputting a detection signal of the active transistor to the output signal line.

CMOS image sensor according to another aspect of the invention, the matrix of unit pixels; Including a first output signal line and a second output signal line provided for each column of the matrix,

The unit pixel may include a light receiving element; A first sensing circuit converting the amount of charge accumulated in the light receiving element during a first exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical characteristic to the first output signal line; And a second sensing circuit converting the amount of charge accumulated in the light receiving element during the second exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the second output signal line.

The first exposure cumulative time is earlier than the second exposure cumulative time, and in a first time interval before the end of the second exposure cumulative time, the first output signal line is used to store the accumulated amount of charge in the first sensing circuit. Signal is outputted, and a signal in a reset state of the second sensing circuit is output to the second output signal line.

In a second time interval after the end of the second exposure accumulation time, a signal of a reset state of the first sensing circuit is output to the first output signal line, and the signal of the second sensing circuit is output to the second output signal line. The signal may be output based on the accumulated charge amount.

Here, the first sensing circuit or the second sensing circuit, the floating diffusion region; A transfer transistor for transferring charge accumulated in the light receiving element to the floating diffusion region; A reset transistor for resetting the floating diffusion region; An active transistor for detecting electrical characteristics of the floating diffusion region; And an addressing transistor for outputting a detection signal of the active transistor to the first output signal line or the second output signal line.

The signal output from the first sensing circuit and the second sensing circuit may be simultaneously transmitted to the first output signal line and the second output signal line.

CMOS image sensor according to another aspect of the invention, the matrix of unit pixels; At least three output signal lines provided for each column of the matrix,

The unit pixel may include a light receiving element; At least three sensing circuits may be included to amplify the electrical characteristics of the light receiving element to convert the electrical characteristics into easy electrical data to be output to each of the at least three output signal lines.

CMOS image sensor of the present invention according to the above configuration has a wide dynamic range with respect to sensitivity, but there is an advantage that the image processing is simple.

For example, the CMOS image sensor according to the present invention uses a single photodiode to accumulate and accumulate electrons generated by light exposure at several times, and output signals according to the accumulation of exposure as a plurality of signals of one pixel in parallel. The dynamic range that responds to the brightness of the image sensor's light has been significantly improved, including the unit pixel output.

Furthermore, the CMOS image sensor of the present invention does not need to have a separate memory outside the pixel array for a wide dynamic range, and its image processing is relatively simple.

Alternatively, the CMOS image sensor of the present invention can obtain a wide dynamic range in both a global shuttering method and a rolling shuttering method.

Alternatively, in order to fabricate the unit pixel of the CMOS image sensor of the present invention, it is not necessary to develop any additional process other than the process for fabricating the conventional general 4-Tr image sensor pixel.

1 is a circuit diagram illustrating a unit pixel and an output signal line of a CMOS image sensor according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram illustrating a pixel matrix structure of a CMOS image sensor according to an exemplary embodiment of the present invention, comprising unit pixels of FIG. 1.
3 is a timing diagram showing a detection signal acquisition operation of a rolling shuttering method of the CMOS image sensor according to an embodiment of the present invention.
4 is a timing diagram illustrating a detection signal acquisition operation of a rolling shuttering method of the CMOS image sensor according to another exemplary embodiment of the present invention.
5 is a timing diagram illustrating an operation of acquiring a detection signal of a global shuttering method of a CMOS image sensor according to another exemplary embodiment of the present invention.
6 is a circuit diagram illustrating a unit pixel and an output signal line of the CMOS image sensor according to another exemplary embodiment of the present invention.
7 is a circuit diagram illustrating a unit pixel and an output signal line of a CMOS image sensor according to another exemplary embodiment of the present invention.
8 is a timing diagram illustrating an operation of acquiring a detection signal of a CMOS image sensor according to another exemplary embodiment of the present invention.
9 is a circuit diagram illustrating a unit pixel and an output signal line of a CMOS image sensor according to another exemplary embodiment of the present invention.
10 is a block diagram illustrating pixel matrix structures and control configurations of a CMOS image sensor according to an embodiment of the present invention.

1 is a circuit diagram showing the configuration of a CMOS image sensor according to an embodiment of the present invention.

The unit pixel 100 constituting the CMOS image sensor of the present embodiment intends to widen the sensitivity range of the image sensor by using one light receiving element and two sensing circuits.

The light receiving device is a device having a characteristic in which a degree of electrical characteristics is determined according to light energy incident from the outside, and the sensing circuit amplifies the electrical property of the light receiving device to facilitate data processing. Current).

The unit pixel 100 illustrated as a light receiving element generates a photodiode PD for generating charge (a known photodiode generates photoconversion electrons, which will be referred to as charge in the following description) in response to light incident from the outside. Applied.

Also, as the sensing circuit, a 4-Tr sensing structure including a transfer transistor, a reset transistor, an active transistor driven by a source follower method, and an addressing transistor is used. However, since two sensing circuits 110 and 130 are applied to one photodiode PD, the illustrated unit pixel 100 has a 1-photodiode 8-Tr structure.

That is, in the illustrated circuit, one unit pixel 100 includes one photodiode PD having an anode connected to a ground voltage and a cathode connected to a first transfer transistor M11 and a second transfer transistor M21. ; A first transfer transistor (M11) for transferring charge accumulated in the photodiode (PD) to a first floating diffusion region (FD1); A first floating diffusion region FD1 connected to the first transfer transistor M11 to store charges transferred from the photodiode PD; A first reset transistor M13 for resetting the first floating diffusion region FD1; A first active transistor M15 for detecting electrical characteristics of the first floating diffusion region FD1; A first addressing transistor (M17) for outputting outside the detection value of the first active transistor (M15); A second transfer transistor (M21) for transferring charge accumulated in the photodiode (PD) to a second floating diffusion region (FD2); A second floating diffusion region FD2 connected to the second transfer transistor M21 and storing charges transferred from the photodiode PD; A second reset transistor M23 for resetting the second floating diffusion region FD2; A second active transistor M25 for detecting electrical characteristics of the second floating diffusion region FD2; And a second addressing transistor M27 for outputting the detection value of the second active transistor M25 to the outside.

In another embodiment, a phototransistor or the like may be used as the light receiving element, and a 3-Tr sensing structure including a reset transistor, an active transistor, and an addressing transistor may be applied as the sensing circuit.

In the layer on the semiconductor substrate on which the drain (or source) of the first transfer transistor M11 and the gate of the first active transistor M15 constituting the illustrated sensing circuit are formed, they are floated by pn junction capacitance. Charge storage regions called diffusion regions FD1 and FD2 may be formed.

The application of the two sensing circuits 110 and 130 to the one light receiving element is to widen the range (in particular, the dynamic range) of the sensitivity of the image sensor. Different methods may be used to have different sensitivity ranges, and / or two different sensing circuits 110 and 130 may be provided with different exposure times to have different sensitivity ranges.

Briefly, the method of the double electron is as follows. For example, in the case of two sensing circuits having a 4-Tr sensing structure, capacitances of the first floating diffusion region FD1 and the second floating diffusion region FD2 may be different from each other, or the first active transistor and the first active transistor may be different. By varying the source follower driving characteristics of the two active transistors, the sensitivity range of the two sensing circuits may be different.

Next, a more complicated latter method will be described.

By applying the latter method, the pixel 100 emits electrons accumulated in the photodiode PD during a shuttering period for one image frame by shuttering and sampling the plurality of processing units into a plurality of sections. It can broaden the dynamic range of pixel sensitivity in response to.

Each pixel of the image sensor to which the above method is applied has a sampling process for reading out a signal obtained by shuttering through a separate circuit, and has an output signal line equal to the number of processing units (K), so that Make sure the output is done at the same time.

1 is an example (K = 2) including two processing units and having two output signal lines corresponding to the two processing units. That is, the CMOS image sensor illustrated in FIG. 1 is provided with two sensing circuits 110 and 130 with respect to one photodiode PD, and each of the two sensing circuits 110 and 130 has one The sensed signal is output to the output signal lines SL1 and SL2. In detail, the first sensing circuit 110 is connected to the first output signal line SL1, and the second sensing circuit 130 is connected to the second output signal line SL2.

The first sensing circuit 110 and the second sensing circuit 130 preferably have the same circuit structure, but may have different circuit structures. In the latter case, for example, the first sensing circuit may have a 4-Tr sensing structure, and the second sensing circuit 130 may have a 3-Tr sensing structure.

The first sensing circuit 110 and the second sensing circuit 130 of FIG. 1 provide an example of a 4-Tr structure.

The illustrated first sensing circuit 110 includes a first floating diffusion region FD1, a first transfer gate transistor (hereinafter, referred to as a “transfer transistor”) M11, and a first reset transistor M13. ), An active transistor (hereinafter, abbreviated as "active transistor") M15 and a first addressing transistor M17 of a first source follower driving method.

The first floating diffusion region FD1 stores charges (electrons) transferred from the photodiode PD, and has a characteristic that its voltage changes according to the stored charge amount.

The first transfer transistor M11 is connected between the photodiode PD and the first floating diffusion region FD1, and is operated by the transfer gate signal tx1 to generate the photodiode PD. The charge is transferred to the first floating diffusion region FD1.

The first reset transistor M13 is connected between the first floating diffusion region FD1 and the power supply voltage VDD and is operated by the reset signal rst1 to reset the voltage of the first floating diffusion region FD1. Let's do it. The first active transistor M15 receives the voltage of the first floating diffusion region FD1 through the gate terminal and outputs the amplified signal v1 to the source terminal. The first addressing transistor M17 operates by the address signal ad1 to connect the source terminal of the first active transistor M15 to the first output signal line SL1 to output the detection signal v1.

The second sensing circuit 130 having the same structure as the first sensing circuit 110 may include a second transfer transistor M21 operated by the second floating diffusion region FD2 and the transfer gate signal tx2. A second reset transistor M23 operated by the reset signal rst2, a second active transistor M25 operating as a source follower to output the detection signal v2, and an address signal ad2 And a second addressing transistor M27 for transmitting the signal v2 to the second output signal line L2. Each of the transistors M21 to M27 of the second sensing circuit 130 according to the example of FIG. 1 corresponds to each of the transistors M11 to M17 of the first sensing circuit 110. Can be explained.

The first current source I1 connected to the first output signal line SL1 forms a source follower amplifier together with the first active transistor M15 and the second current source I2 connected to the second output signal line SL2. ) Forms a source follower amplifier with the second active transistor M25.

The pixels 100 having the configuration of FIG. 1 described above form the matrix to form the CMOS image sensor of the present invention. FIG. 2 is an example of the CMOS image sensor 200 having an Nr × Nc matrix formed by using the pixel of FIG. 1 as a unit pixel.

For example, the detection signal v1 output to the first output signal line SL1 is an image value obtained during a relatively short exposure time, and the detection signal v2 output to the second output signal line SL2 is a relatively long exposure. It may be an image value obtained during time. In this case, the detection signal v1 is useful when the imaging is performed in an environment with high illumination, and the detection signal v2 is useful when the imaging is performed in an environment with low illumination.

2 illustrates a pixel matrix structure of an image sensor having a structure in which two output signal lines SL1 and SL2 are connected to one unit pixel.

Referring to FIG. 2, each unit pixel 100 is connected to two first output signal lines SL1 and second output signal lines SL2 separately provided for each column, and control signal lines provided for each row. CLs). Since the first output signal line SL1 and the second output signal line SL2 are included in one column, the Nc column of image sensors includes Nc × 2 output signal lines.

The control signal lines CLs supply the transfer gate signals tx1 and tx2, the reset signals rst1 and rst2, and the address signals ad1 and ad2, and are common to the unit pixels in each row. The control signal lines CLs control the unit pixels of the row by designating a specific row of the image sensor 200.

In addition, the CMOS image sensor 200 may further include Nv vertical blanks and Nh horizontal blanks as shown in FIG. 2. Vertical blanks and horizontal blanks are virtual pixel arrays that are inserted according to the operational needs of the image sensor over time and are assigned only clock counting without physical entities. For example, a horizontal blank is used to adjust the operating time corresponding to one row of a pixel array, and a vertical blank is used to adjust the time corresponding to one frame.

The process of acquiring the image signal through the photodiode PD by the unit pixel 100 according to the present exemplary embodiment includes a shuttering operation and a sampling process of reading a signal obtained by the shuttering.

One unit pixel constituting an image sensor of another implementation may include three or more sensing circuits, and a shuttering section for one image frame is divided into a plurality of sections corresponding to the number of sensing circuits. Lose. Shuttering is separately performed for each of a plurality of sections by each processing unit. Furthermore, the image sensor may simultaneously sample the output signal lines as many as the number of processing units in each column, or may sequentially sample the output signal lines.

Since the pixel 100 of FIG. 1 includes two processing units 110 and 130, the exposure accumulation time of one image frame may include a first exposure integration time T1 and a second exposure accumulation time. T2). The first exposure accumulation time T1 is the exposure accumulation time for the first sensing circuit 110, and the second exposure accumulation time T2 corresponds to the exposure accumulation time for the second sensing circuit 130. In order to sense a wide dynamic range of the image, it is preferable that the difference between the first exposure accumulation time T1 and the second exposure accumulation time T2 is set to be large.

The first sensing circuit 110 and the second sensing circuit 130 simultaneously output the first and second output voltage signals V1 and V2 in proportion to the number of electrons accumulated in the photodiode PD exposed to light. The output signal lines SL1 and the second output signal lines SL2 are output. The detection signals v1 and v2 simultaneously output from the pixel 100 are transferred to the analog-digital converters ADC1 (not shown) and ADC2 (not shown), respectively, and are converted into digital image signal values of the pixel 100.

The CMOS image sensor 100 of FIG. 1 may perform image acquisition using a global shuttering method or a rolling shuttering method.

Hereinafter, the operation of acquiring a detection signal of the image sensor 200 according to the present invention by double exposure will be described with reference to FIGS. 3 to 5. 3 and 4 are timing diagrams provided in the description of the rolling shuttering operation, and FIG. 5 is a timing diagram provided in the description of the global shuttering operation.

3 to 5 are examples of the case where the pixel 100 of FIG. 1 is implemented with an N-type transistor. Furthermore, hereinafter, the voltage when each signal tx1, tx2, rst1, rst2, ad1, and ad2 turns the transistor on is referred to as 'logical high' based on the N-type transistor, and is turned off. The voltage at (Turn Off) is called 'logic low'. Naturally, when the pixel 100 of FIG. 1 is implemented with a P-type transistor, the signal must be logic low for the transistor to be turned on.

First, an embodiment of a rolling shuttering method of operation will be described with reference to FIG. 3.

In the rolling shuttering method, the shuttering operation and the reading operation proceed sequentially one row at a time. For example, all operations (shuttering and sampling) of row i + 1 (row i + 1) are the same as all operations of row i (row i), but with the same time difference. )do.

Assume that the time at which the signal of the i th row Row i is output to the outside and read is t (i, read). At the time t (i, reset PD), as the transfer gate signal tx1 changes to high while the reset signal rst1 is high, an operation of removing charges accumulated in the photodiode PD (ie, Reset on the photodiode). Next, as the transfer gate signal tx1 becomes low at time t (i, read) -T1-T2, the photodiode PD is disconnected from the sensing circuit 110 and begins to accumulate electrons due to photoelectric conversion. .

Before the t (i, read) -T2 is reached, as the reset signal rst1 turns to logic low, the first reset transistor M13 of the first sensing circuit 110 is turned off to form the first floating diffusion. The area FD1 is floated, and the first transfer transistor M11 is turned on by the transfer gate signal tx1 to remove the photoconversion charge accumulated by the photodiode PD during the first exposure accumulation time T1. 1 is transferred to the floating diffusion region FD1. Thereafter, at t (i, read) -T2, the first transfer transistor M11 is turned off again to block the photodiode PD and the first floating diffusion region FD1 from each other. As a result, the photoconversion charge accumulated during the first exposure accumulation time T1 is stored in the first floating diffusion region FD1.

tx1 and tx2 remain low from the time t (i, read) -T2 to the time t (i, read) -d. Thereafter, the second transfer transistor M21 is turned on by turning tx2 high from t (i, read) -d to t (i, read), so that the charge accumulated in the photodiode PD is transferred to the second floating diffusion region. To (FD2). As a result, at the time t (i, read), the second floating diffusion region FD2 stores the photoconversion charge accumulated in the photodiode PD during the second exposure accumulation time T2. That is, the shuttering process of the second sensing circuit 130 according to the second exposure accumulation time T2 is completed at t (i, read).

In the figure, each of the reset transistors M13 and M23 is turned on for the exposure accumulation times T1 and T2 of the sensing circuits until the transfer transistors M11 and M21 are turned on. This is to remove the charge of each floating diffusion region FD1 and FD2 (that is, reset the floating diffusion region) before receiving charge from the photodiode PD.

In addition, by setting the voltage of the gate signal tx1 when the transfer transistor M11 of the first sensing circuit is turned off to be lower than the voltage of the gate signal tx2 when the transfer transistor M21 of the second sensing circuit is turned off in the above shuttering process. Even when the photodiode PD overflows during the second exposure accumulation time T2 after the first shuttering, the information stored in the first floating diffusion region FD1 may not be damaged.

First shutter by setting the voltage of the gate signal tx1 when the transfer transistor M11 of the first sensing circuit is turned off to be lower than the voltage of the gate signal tx2 when the transfer transistor M21 of the second sensing circuit is turned off in the above shuttering process. Even if the photodiode PD overflows during the second exposure cumulative time after the ring, the information stored in the first floating diffusion may not be damaged.

For example, when the second exposure accumulation time T2 is longer than the first exposure accumulation time T1, even if the photoconversion charge accumulated at the second exposure accumulation time is overflowed in the photodiode, the first sensing circuit 110 may be used. Distortion of the output signal can be prevented.

The rolling shuttering in each row of the image sensor 100 is characterized by the continuous shuttering operation and the reading (sampling) operation for reading the output signal in a series of operations. It is different from global shuttering, which is separate from the shuttering operation.

Hereinafter, the reading process of the signal will be described in detail. A double sampling process of the first sensing circuit is described below.

At t (i, read) -ta before reaching t (i, read), the first addressing transistor M17 of the first sensing circuit 110 is turned on by the addressing signal ad1 to turn on the first active transistor. The output terminal of M15 is connected to the first output signal line SL1. Since the reset signal rst1 is still in a logic low state, the voltage of the first floating diffusion region FD1 formed by the charge already received and transferred from the photodiode PD is amplified by the first active transistor M15. The amplified voltage V1 (a) is output to the first output signal line SL1 during the tb period. The operation ends before the time t (i, read) -ta at which the reset signal rst1 becomes a logic high state.

As the reset signal rst1 is switched to the logic high state at t (i, read), the first floating diffusion region FD1 is reset by the first reset transistor M13. The reset voltage of the first floating diffusion region FD1 is amplified by the first active transistor M15, and the amplified voltage V1 (b) is passed through the first active transistor M15 through the first active transistor M15 during the tc period. Output to SL1). While the voltages V1 (a) and V1 (b) are output through the double sampling process, the addressing signal ad1 maintains a logic high.

The analog-to-digital converter that receives the voltages V1 (a) and V1 (b) receives a difference value V1 (b) -V1 (a) between the voltages V1 (a) and V1 (b). The digital image signal at the position of the unit pixel 100 with respect to the first exposure accumulation time T1 is determined.

Meanwhile, the second sensing circuit 130 simultaneously removes its voltages V2 (a) and V2 (b) from the voltages V1 (a) and V1 (b) of the first sensing circuit 110. 2 can be output to the output signal line SL2.

A correlated double sampling process of the second sensing circuit 120 is described below.

The addressing signal ad2 changes to logic high together when the addressing signal ad1 changes from logic low to high, but the second exposure accumulation time T2 is not terminated, and the reset signal rst2 indicates logic high. Keep it. As a result, the second addressing transistor M27 of the second sensing circuit 130 is turned on to connect the output terminal of the second active transistor M25 to the second output signal line SL2 so that the second floating diffusion region ( The voltage V2 (a) of FD2 is output to the second output signal line SL2 for tb time. In this case, the voltage V2 (a) of the second floating diffusion region FD2 has a reset voltage from which the charges are removed, and the photodiode PD disconnected from the second floating diffusion region FD2 has a photoconversion charge. Continues to accumulate.

Thereafter, as the reset signal rst2 is changed from logic high to low at t (i, read) -ta + tb, the second reset transistor M23 is turned off to float the second floating diffusion FD2. The second transfer gate M21 is turned on to connect the photodiode PD and the second floating diffusion region FD2 until t (i, read), so that the photodiode PD is exposed during the second exposure accumulation time T2. The photoconversion charges accumulated in the transfer to the second floating diffusion FD2.

The voltage V2 (b) of the second floating diffusion region FD2 receiving the photoconversion charge is generated by the second active transistor M25 during the period t (i, read) to t (i, read) + tc. Amplified and output to the second output signal line SL2.

The analog-to-digital converter receiving the voltages V2 (a) and V2 (b) obtains the difference between the voltages V2 (a) and V2 (b) (V2 (a) -V2 (b)). The digital image information value of the position of the unit pixel 100 with respect to the second exposure accumulation time T2 is determined.

FIG. 4 is a timing diagram for explaining another embodiment of a rolling shuttering method.

The difference from the operating method of FIG. 3 is that there is a time interval ΔT between the exposure accumulation time T1 and the exposure accumulation time T2. That is, after completing the first exposure accumulation, the second transfer transistor M21 and the second reset transistor M23 are turned on during the second exposure accumulation time interval ΔT to reset the photodiode PD. Next, the second transfer transistor M21 is turned off to disconnect the photodiode PD to start the second exposure accumulation.

Except for the time interval ΔT, since it is similar to the operating method of FIG. 3, detailed descriptions thereof will be omitted.

Next, the operation of the global shuttering method will be described with reference to FIG. 5. According to the global shuttering method, the shuttering operation is simultaneously performed for the entire pixel array. The reading process after the shuttering operation is performed sequentially one row at a time.

5 shows the timing of control signals for an image sensor operating in a global shuttering scheme.

Assume that the time of reading the signals of the pixels is t (read). At the time t (reset PD), as the transfer gate signal tx1 changes to high while the reset signal rst1 for all pixels is high, an operation of removing charges accumulated in the photodiode PD ( That is, the reset for the photodiode is performed. Next, as the transfer gate signal tx1 turns low at the time t (i, read) -T1-T2-ΔT, the photodiode PD is cut off from the sensing circuit and begins to accumulate charges due to photoelectric conversion.

Immediately before reaching t (read) -T2-ΔT-d1, as the reset signal rst1 turns to logic low, the first reset transistor M13 of the first sensing circuit 110 is turned off to first floating. The diffusion region FD1 is floated, and the first transfer transistor M11 is turned on during the period d1 by the transfer gate signal tx1 and accumulated by the photodiode PD during the first exposure accumulation time T1. The photoconversion charge is transferred to the first floating diffusion region FD1. Thereafter, at t (read) -T 2 -ΔT, the first transfer transistor M11 is turned off again to block the photodiode PD and the first floating diffusion region FD1 from each other. As a result, the photoconversion charge accumulated during the first exposure accumulation time T1 is stored in the first floating diffusion region FD1.

A process of accumulating the photoconversion charge in the photodiode PD for the second exposure accumulation time T2 and then transferring the photoconversion charge to the second floating diffusion region FD2 will be described.

The transfer transistor M21 is turned on by keeping the transfer gate signal tx2 high from the time t (read) -T2-d3 to the time t (read) -T2. At this time, the photodiode PD is reset again. Then transfer transistor M21 is turned off and photodiode PD again begins to accumulate photoconversion charge. Immediately before the time t (read) -d2, the reset transistor M23 is turned off with the reset signal rst2 low to float the second floating diffusion region FD2. Subsequently, the transfer transistor M21 is turned on from t (read) -d2 to t (read) to transfer charges accumulated in the photodiode PD to the second floating diffusion region FD2. The transfer transistor M21 is turned off at t (read) again. As a result, the diffusion region FD2 stores the photoconversion charge accumulated in the photodiode PD during the second exposure accumulation time T2. As described above, the shuttering process according to the first exposure accumulation time T1 and the second exposure accumulation time T2 is completed at t (read). In the figure, a time interval ΔT is provided between the first exposure accumulation time T1 and the second exposure accumulation time T2. In another implementation, the first exposure accumulation time T1 and the second exposure accumulation time T2 may proceed immediately.

The shuttering operation as described above is simultaneously performed on all pixels including the i th row Row i and the i + 1 th row i + 1 row of the image sensor 200. That is, the photodiodes of all the pixels simultaneously accumulate signal electrons, and the accumulated photoconversion charges are simultaneously transferred to and stored in the floating diffusion, thereby achieving global shuttering.

First shutter by setting the voltage of the gate signal tx1 when the transfer transistor M11 of the first sensing circuit is turned off to be lower than the voltage of the gate signal tx2 when the transfer transistor M21 of the second sensing circuit is turned off in the above shuttering process. Even if the photodiode PD overflows during the second exposure cumulative time after the ring, the information stored in the first floating diffusion region FD1 may not be damaged.

For example, when the second exposure accumulation time T2 is longer than the first exposure accumulation time T1, even if the photoconversion charge accumulated at the second exposure accumulation time is overflowed in the photodiode, the first sensing circuit 110 may be used. Distortion of the output signal can be prevented.

Hereinafter, a reading process by double sampling in global shuttering will be described. In the figure, starting from t (read), which is the start time of a reading operation for an image frame, Nr rows are sequentially read one by one, and the output signal is read. However, the output signal can be read in parallel for all the pixels of each column in each row. The drawing shows that after a predetermined time elapses from the time t (read), a reading operation is performed on the i th row Row i and a reading operation is performed on the i th +1 row Row i + 1. .

The first addressing transistor M17 of the first sensing circuit 110 is turned on by the addressing signal ad1 to connect the output terminal of the first active transistor M15 to the first output signal line SL1. Accordingly, the voltage of the first floating diffusion region FD1 receiving the photoconversion charge is amplified by the first active transistor M15, and the amplified voltage V1 (a) is transferred to the first output signal line SL1. Is output.

Subsequently, as the reset signal rst1 returns to the logic high state, the first reset transistor M13 resets the first floating diffusion region FD1, and the voltage of the reset first floating diffusion region FD1 is reset. V1 (b) is also output to the first output signal line SL1 through the first active transistor M15.

While the voltages V1 (a) and V1 (b) are output through the double sampling process, the addressing signal ad1 maintains a logic high. In the analog-to-digital converter receiving the voltages V1 (a) and V1 (b), the difference value of the voltages V1 (a) and V1 (b) is applied by double sampling. V1 (b) is determined as the digital image signal value of the unit pixel 100 position with respect to the first exposure accumulation time T1.

The digital image signalization process by double sampling of the second sensing circuit 130 is simultaneously processed in parallel with the first sensing circuit 110. In other words, during sampling, the reset signal rst2 and the addressing signal ad2 have the same state change as the reset signal rst1 and the addressing signal ad1. Accordingly, in parallel with the sampling operation of the first sensing circuit 110, the second output signal line is double-sampled to the voltages V2 (a) and V2 (b) of the second floating diffusion region FD2. To (SL2). Therefore, there is an advantage of shortening the time for signal processing.

Similarly, the analog-to-digital converter applies double sampling, so that the difference values V2 (b) -V2 (a) of the voltages V2 (a) and V2 (b) are compared with respect to the second exposure accumulation time T2. The digital image signal value of the unit pixel 100 is determined.

The above reading process is simultaneously performed for all pixels belonging to each row. Therefore, as shown in FIG. 3, when the reading process of the row i is completed, the double sampling of the row i + 1 is performed immediately.

FIG. 6 is a unit pixel circuit diagram of a CMOS image sensor according to another exemplary embodiment, in which one output signal line SL is substituted for the first output signal line SL1 and the second output signal line SL2 of FIG. 1. It is an example provided.

Instead, a first switch SW1 operating in synchronization with the first addressing transistor M17 without phase difference is provided between the output signal line SL and the analog-to-digital converter ADC1 (not shown), and the second addressing transistor M27. ) Is provided between the output signal line SL and the analog-to-digital converter ADC2 (not shown).

In the example of FIG. 6, the area of the pixel array is reduced compared to the case in which two output signal lines are connected to the unit pixel as shown in FIG. 1. However, two detection signals v1 and v2 cannot be output from the unit pixel at the same time in parallel and must be processed with a slight time difference.

According to another embodiment, in the example of FIG. 6, one output signal line SL and one analog-to-digital converter may be included, and the first switch SW1 and the second switch SW2 may not be included. Is an example.

The two signals from the unit pixel 100 are not simultaneously operated by the first addressing transistor M17 and the second addressing transistor M27 and are sequentially connected to one analog-digital converter by dividing the time. This structure can reduce the pixel array area and the area of the signal processing circuit portion. However, there is a burden on the time signal processing speed that should be used for two signal processing coming from a pixel by dividing the time allotted to one row into two.

8 illustrates timing of control signals for driving the CMOS image sensor of FIG. 7. In FIG. 8, only the i column is shown. When the global shuttering is applied, the remaining columns receive control signals at the same timing as the i row. When the rolling shuttering is applied, the remaining columns and the i columns are the control signals having the same pattern sequentially formed. Licensed.

In the shuttering section, a shuttering operation is performed by a process similar to FIG. 5, and in a reading section, similar to FIG. 5, but control signals for the first sensing circuit 116 and control for the second sensing circuit 136. 5 is different from FIG. 5 because the signals are sequentially processed. That is, the control signals for the reading operation for the first sensing circuit 116 are activated from the time t (i, read1), and the control signals for the reading operation for the second sensing circuit 136 are t (i, read2). ) Will be activated from that point on. Since the reading operation by the control signals can be easily inferred from the description of FIG. 5, redundant description will be omitted.

9 is an example of a unit pixel 700 including four processing units 110 to 170. Each processor 110 to 170 stores signal electrons corresponding to four exposure accumulation times T1, T2, T3, and T4 in four floating diffusions FD1, FD2, FD3, and FD4, respectively, and corresponding voltage signals. Can be output externally. The pixel structure is a structure capable of both global shuttering and rolling shuttering.

10 illustrates an image sensor block for driving the image sensor according to the present embodiment in a column-parallel manner.

In the column-parallel CMOS image sensor block, an active pixel sensor array 11 including unit pixels according to the present exemplary embodiment, and values sensed by the unit pixels are converted into a digital image signal. A CDS / ADC 12, a data buffer 13, a ramp signal generator 14, a row driver 15 for controlling the operation of the unit pixels, and the row driver 15 ) And a timing control signal generator 16 for controlling the operation timing of the CDS / ADC 12.

The active pixel sensor array 11 may be formed of an array of unit pixels including eight transistors and one photodiode according to the present embodiment. That is, the unit pixels of any one of FIGS. 1, 6, 7, and 9 may be provided, or the pixel matrix of FIG. 2 may be provided.

The CDS / ADC 12 of the figure applies a single-slope ADC for a method in which all columns simultaneously perform an analog-to-digital conversion function in each row.

The CDS / ADC circuit 12 may convert the output signal of the pixel sensor array 11 into a digital signal by using a ramp signal and convert it into a digital signal, and include a plurality of switches, capacitors, and an inverter. Can be provided. The ramp signal used by the CDS / ADC circuit 12 is generated by the ramp signal generator 14 of FIG.

Hereinafter, an operation of the CMOS image sensor block for implementing the idea of the present invention will be described. Here, although the row driver 15 and the CDS / ADC 12 operate according to the timing control of the timing control signal generator 16, for convenience of description, the main driver of the row driver 15 is the row driver 15. ) And CDS / ADC 12.

First, an operation in the case where the active pixel sensor array 11 of the components of FIG. 10 is configured with the unit pixel 100 and the matrix structure of the embodiment illustrated in FIGS. 1 and 2 will be described.

The illustrated row driver 15 applies a control signal to the control signal bus CLS of FIG. 2, and the illustrated CDS / ADC circuit 12 detects the output signal line pairs SL1 and SL2 of FIG. 2. The signals v1 and v2 may be input, and the digital image signals determined by the CDS method may be stored in the data buffer 13.

Bayer image data stored in the data buffer 13 has a value corresponding to the detection signal v1 output to the first output signal line SL1 and the second output signal line SL2 for each pixel. A value corresponding to the detection signal v2 outputted as may be described. Hardware and / or software using the Bayer data image may select one of the values corresponding to the detection signal v1 and the values corresponding to the detection signal v2 to configure final image data, as necessary. have.

Next, an operation when the active pixel sensor array 11 of the components of FIG. 10 is configured as the unit pixel 106 of the embodiment shown in FIG. 7 will be described. Here, the sensing circuits 116 and 136 constituting the unit pixel of FIG. 7 preferably have different specifications. For example, the first sensing circuit 116 may have a size suitable for use in high sensitivity in a low light environment, and the second sensing circuit 136 may have a size suitable for securing low noise low noise images in a high light environment.

The row driver 15 of FIG. 10 applies the control signals tx1, tx2, rst1, rst2, ad1, and ad2 of FIG. 7, and the CDS / ADC circuit 12 of FIG. 10 outputs the output signal line of FIG. 7. From the SL, detection signals may be input and digital image signals determined by the CDS method may be stored in the data buffer 13.

The illustrated timing control signal generator 16 may select one of the two sensing circuits 116 and 136 of FIG. 7 in consideration of an environmental condition in which imaging using the CMOS image sensor is performed. In this case, control signals may be activated only for the selected sensing circuit.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

104: unit pixel
SL: Output signal line
SW1: first switch
SW2: second switch

Claims (6)

A matrix of unit pixels; And
Including an output signal line (SL) provided for each column of the matrix,
The unit pixel is,
Light receiving element PD;
First sensing circuits M11, M13, M15, and M17 for converting the amount of charge accumulated in the light receiving element during a first exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the output signal line;
Second sensing circuits M21, M23, M25, and M27 for converting the amount of charge accumulated in the light receiving element during a second exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical signal to the output signal line;
A first switch SW1 provided between the analog-to-digital converter ADC1 for the first sensing circuit and the output signal line SL; And
The second switch SW2 provided between the analog to digital converter ADC2 for the second sensing circuit and the output signal line SL.
CMOS image sensor comprising a. The method of claim 1,
The first sensing circuit or the second sensing circuit,
Floating diffusion region;
A transfer transistor for transferring charges accumulated in the light receiving element to the floating diffusion region;
A reset transistor for resetting the floating diffusion region;
An active transistor for detecting electrical characteristics of the floating diffusion region; And
An addressing transistor for outputting the detection signal of the active transistor to the output signal line
CMOS image sensor comprising a. A matrix of unit pixels;
Including a first output signal line and a second output signal line provided for each column of the matrix,
The unit pixel is,
Light receiving element;
A first sensing circuit converting the amount of charge accumulated in the light receiving element during a first exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical characteristic to the first output signal line; And
A second sensing circuit converting the amount of charge accumulated in the light receiving element during a second exposure accumulation time into an electrical characteristic that facilitates data processing and outputting the electrical characteristic to the second output signal line;
Including,
The first exposure accumulation time is earlier than the second exposure accumulation time,
In a first time interval before the end of the second exposure accumulation time, a signal based on the accumulated charge amount of the first sensing circuit is output to the first output signal line, and the second output signal line is output. 2 outputting the signal of the reset state of the sensing circuit is performed at the same time,
In a second time interval after the end of the second exposure accumulation time,
The CMOS image outputs a signal of a reset state of the first sensing circuit to the first output signal line and outputs a signal based on the accumulated charge amount of the second sensing circuit to the second output signal line. sensor. The method of claim 3, wherein
The first sensing circuit or the second sensing circuit,
Floating diffusion region;
A transfer transistor for transferring charge accumulated in the light receiving element to the floating diffusion region;
A reset transistor for resetting the floating diffusion region;
An active transistor for detecting electrical characteristics of the floating diffusion region; And
An addressing transistor for outputting the detection signal of the active transistor to the first output signal line or the second output signal line.
CMOS image sensor comprising a. The method of claim 3, wherein
The signal output from the first sensing circuit and the second sensing circuit,
And the CMOS image sensor is simultaneously transmitted to the first output signal line and the second output signal line. delete

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