CN109040633B - HDR image sensor with gain compensation, readout circuit and method - Google Patents
HDR image sensor with gain compensation, readout circuit and method Download PDFInfo
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- CN109040633B CN109040633B CN201811303591.4A CN201811303591A CN109040633B CN 109040633 B CN109040633 B CN 109040633B CN 201811303591 A CN201811303591 A CN 201811303591A CN 109040633 B CN109040633 B CN 109040633B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
Abstract
The invention provides an HDR image sensor with gain compensation, which comprises a pixel array, a control circuit and a readout circuit. The control circuit sequentially reads a low-conversion-gain reset signal, a high-conversion-gain image signal and a low-conversion-gain image signal which are output by the pixel array according to control; the readout circuit includes a selection switch, a low conversion gain analog-to-digital conversion circuit and a high conversion gain analog-to-digital conversion circuit. The selection switch controls and selects the pixel output of the half-row reading pixel array of the readout circuit and the switching of the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit; the low conversion gain analog-to-digital conversion circuit is used for quantizing the reset signal and the image signal which are output under the low conversion gain; the high conversion gain analog-to-digital conversion circuit is used for quantizing the reset signal and the image signal which are output under the high conversion gain. The invention also provides a HDR image sensor reading circuit with gain compensation and an implementation method.
Description
Technical Field
The invention relates to the technical field of CMOS image sensors, in particular to an image sensor with gain compensation and high dynamic range, a reading circuit and an implementation method.
Background
The dynamic range is a key factor of the imaging quality of the image sensor, the dynamic range is large, scene image information in a wider light intensity range can be output, and richer image details are presented. The dynamic range of the output of the image sensor is about 60-70 db in general, and the dynamic range required for capturing image information of highlight and shadow parts in general natural environment applications is about 100 db. In the design of an image sensor, there are several ways to improve the dynamic range, for example, further improving the full-well charge capacity of a pixel circuit, and obtaining a larger dynamic range; or a mode of reading multi-frame images for multi-frame synthesis is adopted to realize the High Dynamic Range (HDR) of the image sensor.
DCG (Dual Conversion gain) double Conversion gain is applied to the pixel circuit of the image sensor, and the Conversion gain is improved by a smaller integration capacitor under the condition of low illumination so as to improve the sensitivity; under the condition of high illumination, the storage charge is increased by a larger integration capacitor, and the conversion gain is reduced to improve the dynamic range. In the high dynamic range implementation mode adopting multi-frame synthesis, time difference exists in the multi-frame reading process, the trailing phenomenon can occur in the finally synthesized image, and the reading noise of the circuit is large. How to further increase the dynamic range of the image sensor and simultaneously reduce the noise of the pixel circuit is a major problem faced in current designs.
Based on the above problems, the present invention aims to provide a solution to efficiently achieve high dynamic range of an image sensor.
Disclosure of Invention
The present invention aims to provide an HDR image sensor with gain compensation, the image sensor comprising:
an array of pixels;
a control circuit connected to the pixel array, the control circuit controlling to sequentially read a reset signal of low conversion gain, a reset signal of high conversion gain, an image signal of high conversion gain, and an image signal of low conversion gain output from the pixel array;
the reading circuit comprises a selection switch, a low conversion gain analog-to-digital conversion circuit and a high conversion gain analog-to-digital conversion circuit; the low conversion gain analog-to-digital conversion circuit is used for quantizing a reset signal and an image signal which are output by the pixel array under the low conversion gain; the high conversion gain analog-to-digital conversion circuit is used for quantizing a reset signal and an image signal which are output by the pixel array under high conversion gain;
further, the selection switch is used for controlling and selecting the half row of the readout circuit to read the pixel output of the pixel array, and switching the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit;
furthermore, the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit respectively comprise a comparator, a counter and a memory;
further, a reset signal or an image signal output by a pixel of the pixel array at a low conversion gain and a low conversion gain ramp voltage are respectively coupled to two input ends of the low conversion gain analog-to-digital conversion circuit comparator through capacitors; the reset signal or the image signal and the high conversion gain ramp voltage output by the pixel of the pixel array under the high conversion gain are respectively coupled to two input ends of the high conversion gain analog-to-digital conversion circuit comparator through capacitors; the slopes of the low conversion gain ramp voltage and the high conversion gain ramp voltage are the same or different; when the slopes of the low conversion gain ramp voltage and the high conversion gain ramp voltage are different, the circuit gain can be further improved;
further, the low conversion gain ramp voltage is coupled to the input end of the low conversion gain analog-to-digital conversion circuit comparator through a variable capacitor; the high conversion gain ramp voltage is coupled to the input end of the high conversion gain analog-to-digital conversion circuit comparator through a variable capacitor; the circuit gain can be further improved by adjusting the variable capacitor;
further, the pixel array comprises a plurality of pixel units arranged in rows and columns, each pixel unit comprises a DCG transistor and a capacitor, and the DCG transistors and the capacitors realize high-gain and low-gain conversion of the pixel units according to control;
furthermore, the capacitor is a device capacitor or a parasitic capacitor, one electrode of the capacitor can be connected to a power supply when the capacitor is the device capacitor, and one electrode of the capacitor is grounded when the capacitor is the parasitic capacitor;
furthermore, each pixel unit comprises one or more paths of photosensitive pixels adopting a shared structure, each path of photosensitive pixel comprises a photodiode and a transmission transistor connected to the photodiode, and the transmission transistor is used for transferring electrons generated by incident light through photoelectric effect to a floating diffusion point; the multiple paths of photosensitive pixels adopting the shared structure can be shared by two paths of photosensitive pixels or four paths of photosensitive pixels;
furthermore, when each pixel unit comprises one or two paths of photosensitive pixels adopting a shared structure, the readout circuit respectively reads pixel outputs of two pixel units of the pixel array in half rows; when each pixel unit comprises four paths of photosensitive pixels adopting a shared structure, the four paths of photosensitive pixels adopting the shared structure are arranged in a 2 x 2 structure, the pixel outputs of the pixel units are respectively connected to an even column line and an odd column line, and the pixel outputs are read by the readout circuit in half rows;
further, each pixel unit comprises a reset transistor and a source follower transistor, the drain electrode of the reset transistor and the drain electrode of the source follower transistor are connected to the same fixed voltage source, and each pixel unit further comprises a row selection transistor; or the drain of the reset transistor is connected to a variable voltage source, the drain of the source follower transistor is connected to a fixed voltage source, and the source of the source follower transistor is connected to an output column line.
The present invention also provides a readout circuit of an HDR image sensor with gain compensation, the readout circuit comprising:
the selection switch, the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit; the selection switch is used for controlling and selecting the half row of the readout circuit to read the pixel output of the pixel array, and switching the pixel output of the pixel array to the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit; the readout circuit respectively quantizes a reset signal with low conversion gain, a reset signal with high conversion gain, an image signal with high conversion gain and an image signal with low conversion gain in sequence;
a low conversion gain reset signal and a low conversion gain pixel signal output by the pixel are respectively read to the low conversion gain analog-to-digital conversion circuit for quantization processing; the high conversion gain reset signal and the high conversion gain pixel signal output by the pixel are respectively read to the high conversion gain analog-to-digital conversion circuit for quantization processing;
furthermore, the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit respectively comprise a comparator, a counter and a memory;
further, a low conversion gain reset signal or an image signal and a low conversion gain ramp voltage output by the pixel are respectively coupled to two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit through capacitors; the high conversion gain reset signal or the image signal output by the pixel and the high conversion gain ramp voltage are respectively coupled to two input ends of a comparator of the high conversion gain analog-to-digital conversion circuit through capacitors; when the voltage of the low conversion gain ramp begins to fall, and the voltages at two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit are overlapped (overlapped uniformly), the comparator outputs 0, and the counter stops counting; the same is true for the high conversion gain analog-to-digital conversion circuit; sequentially realizing quantization processing on the low conversion gain reset signal, the high conversion gain pixel signal and the low conversion gain pixel signal;
further, the low conversion gain ramp voltage is coupled to the input end of the low conversion gain analog-to-digital conversion circuit comparator through a variable capacitor; the high conversion gain ramp voltage is coupled to the input end of the high conversion gain analog-to-digital conversion circuit comparator through a variable capacitor; by adjusting the variable capacitor, the circuit gain can be further improved;
further, the slopes of the low conversion gain ramp voltage and the high conversion gain ramp voltage may be the same or different, and when the slopes of the low conversion gain ramp voltage and the high conversion gain ramp voltage are different, the circuit gain may be further increased;
the invention also provides a method for implementing an image sensor with gain compensated HDR, the method comprising:
the pixel array provides a pixel output;
according to the control selection of the selection switch, the pixel output half-line reading is carried out on the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit for quantization processing;
sequentially quantizing the low conversion gain reset signal, the high conversion gain image signal and the low conversion gain image signal to obtain a digital image signal under low conversion gain and a digital image signal under high conversion gain;
further, a low conversion gain reset signal and a low conversion gain image signal output by the pixel are read to the low conversion gain analog-to-digital conversion circuit for quantization processing; reading a high conversion gain reset signal and a high conversion gain image signal output by the pixel to the high conversion gain analog-to-digital conversion circuit for quantization processing;
further, the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit respectively comprise a comparator, a counter and a memory, a low conversion gain reset signal or an image signal and a low conversion gain ramp voltage output by the pixel are respectively coupled to two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit through capacitors, and a high conversion gain reset signal or an image signal and a high conversion gain ramp voltage output by the pixel are respectively coupled to two input ends of the comparator of the high conversion gain analog-to-digital conversion circuit through capacitors;
further, the low conversion gain ramp voltage starts to fall, when the voltages at two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit are overlapped, the comparator outputs 0, and the counter stops counting; the same is true for the high conversion gain analog-to-digital conversion circuit; sequentially realizing quantization processing on the low conversion gain reset signal, the high conversion gain pixel signal and the low conversion gain pixel signal;
further, the low conversion gain ramp voltage is coupled to the input end of the low conversion gain analog-to-digital conversion circuit comparator through a variable capacitor; the high conversion gain ramp voltage is coupled to the input end of the high conversion gain analog-to-digital conversion circuit comparator through a variable capacitor; by adjusting the variable capacitor, the circuit gain can be further improved;
further, the slopes of the low conversion gain ramp voltage and the high conversion gain ramp voltage may be the same or different, and when the slopes of the low conversion gain ramp voltage and the high conversion gain ramp voltage are different, the circuit gain may be further improved.
The pixel array of the image sensor, the reading circuit and the implementation method adopts a DCG dual-conversion gain mode, and the low-conversion-gain and high-conversion-gain quantization circuits respectively quantize signals output under low conversion gain and signals output under high conversion gain so as to realize the high dynamic range of the image sensor. In the process of carrying out quantization processing on the pixel output, the slope of the low conversion gain ramp voltage and the slope of the high conversion gain ramp voltage of the readout circuit can be set to be different, so that the circuit gain can be further improved, and the dynamic range of the image sensor can be further increased; in addition, the low conversion gain ramp voltage and the high conversion gain ramp voltage are respectively coupled to the comparator through the variable capacitor in the reading circuit, and the circuit gain can be further improved by adjusting the variable capacitor. Meanwhile, the readout circuit provided by the invention does not need to sample and hold the pixel output to improve KT/C noise of the circuit, and meanwhile, the analog power consumption of the circuit is lower, so that the performance of the image sensor is further improved.
Drawings
FIG. 1 is a system block diagram of an image sensor;
FIG. 2 is a circuit diagram of a pixel unit for half-row reading of a pixel array according to a first embodiment of the present invention;
FIG. 3 is a circuit diagram of a pixel unit with a sharing structure according to a second embodiment of the present invention;
FIG. 4 is a diagram of another embodiment of a pixel cell circuit with a shared structure according to the present invention;
FIG. 5 is a circuit diagram of a pixel unit with a 2 × 2 structure and half-row reading according to a third embodiment of the present invention;
FIG. 6 is a schematic diagram of a readout circuit of an image sensor according to the present invention; and
fig. 7 is a timing diagram of the image sensor circuit according to the present invention.
Detailed Description
The invention will be described in detail with reference to the drawings attached hereto. Fig. 1 is a block diagram showing a basic configuration of an image sensor system, and as shown in fig. 1, an image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to a pixel array 101, and a functional logic unit 103 connected to the readout circuit 102 for logically controlling reading of the pixel circuit; the readout circuit 102 and the control circuit 104 are connected to a status register 105, and read control of the pixel array 101 is realized. The pixel array 101 includes a plurality of pixel cells in rows (R1, R2, R3 … Ry) and columns (C1, C2, C3 … Cx), and pixel signals output from the pixel array 101 are output to the readout circuit 102 via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out using the readout circuit 102 whose status register 105 specifies the readout mode, and then transferred to the functional logic unit 103. In particular applications, the readout circuit 102 may include analog-to-digital conversion (ADC) circuits, amplification circuits, and others. In some embodiments, the status register 105 may include a program selection system for determining whether the read system is read in a rolling shutter mode or a global shutter mode. The function logic unit 103 may store only image data or image data applied or processed by an image effect. In one application, readout circuitry 102 may read out a row of image data at a time along readout column lines (as shown in FIG. 1), or may read out the image data in a variety of other ways. The operation of the control circuit 104 may be determined by the current setting of the status register 105. For example, the control circuit 104 generates a shutter signal for controlling image acquisition. In some applications, the shutter signal may be a global exposure signal such that all pixels of the pixel array 101 acquire their image data simultaneously through a single acquisition window. In some other applications, the shutter signal may be a rolling exposure signal, and each pixel row is sequentially read through the capture window.
Fig. 2 is a circuit diagram of a first embodiment of a pixel unit for implementing half-row reading in a pixel array of an image sensor according to the present invention. The pixel array of the image sensor includes a plurality of pixel cells arranged in rows and columns in the structure shown in fig. 2, and the pixel circuit for half-row reading includes two portions of pixel cells 200a and 200b, the pixel outputs of which are respectively to even columns and odd columns. Taking the pixel unit 200a as an example, the photosensitive pixel of the pixel unit includes a photodiode PDa and a transfer transistor 203a, and the transfer transistor 203a transfers electrons generated by the photodiode PDa through a photoelectric effect to a floating diffusion point fd (a). The dual conversion gain control unit includes a DCG transistor 202a and a capacitor Ca, which are connected between the reset transistor 201a and the floating diffusion point FD, for implementing the pixel circuit to operate in the low conversion gain or the high conversion gain mode according to the control signal. The capacitor Ca may be a device capacitor or a parasitic capacitance of the connection point of the reset transistor 201a and the DCG transistor 202a to ground. In fig. 2, an example is given of a device capacitance, the other pole of Ca being connected to a voltage VC. In some embodiments, the Ca capacitor is a parasitic capacitance of the connection point of the reset transistor 201a and the DCG transistor 202a to ground, and the other electrode of the Ca capacitor is grounded. The amplified output of the pixel signal via the source follower transistor 204a is output to the even column line (PIXOUT _ a output) via the row select transistor 205 a. Similarly, the pixel signal of the pixel unit 200b is output to the odd column line (PIXOUT _ b output). In a second embodiment of the present invention, each pixel unit may be a photosensitive pixel with a shared structure, as shown in fig. 3, a pixel circuit for realizing half-row reading includes two pixel units 300a and 300b, and pixel outputs thereof are respectively supplied to an even column PIXOUT _ a and an odd column PIXOUT _ b. Taking the 300a pixel cell as an example, photodiode PDa0 and transfer transistor 303a constitute a shared structure of light-sensing pixels with photodiode PDa1 and transfer transistor 306a, shared and connected to floating diffusion point fd (a). The pixel unit adopting the sharing structure can reduce the number of transistors in the pixel circuit and can reduce the design area of a chip; understandably, the area of the photosensitive area can be increased under the condition that the design area of the pixel circuit is not changed, so that the light sensitivity of the pixel circuit is improved, and the performance of the pixel circuit is improved. Fig. 4 is another implementation of the pixel cell circuit of fig. 3. As shown in fig. 4, taking a 400a pixel cell as an example, the drain of the reset transistor 401a and the drain of the source follower transistor 404a are connected to different voltage sources, respectively. The drain of the reset transistor 401a is connected to a variable voltage source Vref and the drain of the source follower transistor 404a is connected to a fixed voltage source PIXVDD, the row select transistor 405a can be eliminated from the pixel circuit and the source output of the source follower transistor 404a is directed to the even column output PIXOUT _ a. The pixel unit circuit can save row selection transistors in the circuit to reduce the design of the pixel circuit; it can be understood that the design area of the light sensing region can be increased under the condition that the area of the pixel circuit is not changed, and the light sensitivity of the pixel circuit is further improved. The variable voltage Vref is combined with other control signals in the circuit to realize the signal output of the pixel circuit.
Fig. 5 is a circuit diagram of a pixel unit according to a third embodiment of the present invention, as shown in the figure, the pixel unit includes four photosensitive pixels adopting a shared structure: a photodiode PDa and a transfer transistor 503, a photodiode PDb and a transfer transistor 507, a photodiode PDc and a transfer transistor 506, and a photodiode PDd and a transfer transistor 508. Four-way photosensitive pixels are arranged in a 2 × 2 structure to achieve half-row reading of pixel outputs. For example, the photodiode PDb and the transfer transistor 507 convert an optical signal into an electric signal and transfer-output to the floating diffusion point FD, signal amplification via the source follower transistor 504 and selection output to the even column line by the row selection transistor 505; the photodiode PDa and the transfer transistor 503 convert an optical signal into an electric signal and transfer-output to the floating diffusion point FD, signal amplification via the source follower transistor 504 and selection output to the odd column line by the row selection transistor 505. The control circuit and the readout circuit of the image sensor perform read control and quantization processing on pixel outputs of even columns and odd columns, respectively.
Fig. 6 is a schematic diagram of a readout circuit of an image sensor according to the present invention, in which a selection switch selects an even column pixel output or an odd column pixel output to a quantization circuit according to control enable, and switches to a low gain analog-to-digital conversion circuit or a high gain analog-to-digital conversion circuit for quantization processing according to the selection. The selection switch shown in fig. 6 is an example, including but not limited to other forms of selection switches used to implement the function of controlling selection thereof. FIG. 7 is a timing diagram of an image sensor circuit according to the present invention, which includes two parts of a readout circuit for reading and quantizing pixel outputs of even columns and pixel outputs of odd columns, and in conjunction with the pixel circuit shown in FIG. 2, a part of pixel outputs of a pixel unit is set to be 200a to even columns, and the timing sequence corresponds to read-even; and 200b pixel units output partial pixels to odd columns at the time sequence corresponding to read-odd. The read _ even _ en and the read _ odd _ en are enabled by the control of the selector switch to selectively output pixels of even columns or odd columns to the quantization circuit for quantization, the quantization processes of the outputs of the two parts of pixels are the same, and the pixel output pixout _ a of a 200a pixel unit is taken as an embodiment, and the specific process is as follows:
at time t0, the row selection signal rowsel _ a is set to be at a high level, the transistor 205a is conducted, the low conversion gain and high conversion gain analog-to-digital conversion circuit selection switch lcg _ en is conducted, and the pixel output pixout _ a and the low conversion gain analog-to-digital conversion circuit are switched on;
at time t1, the low conversion gain zero clearing switch lcg _ cmp _ az and the high conversion gain zero clearing switch hcg _ cmp _ az are turned on, the input end Vinp of the comparator 501 and the first-stage output end Vop1 are in short connection, the input end Vinn and the first-stage output Von1 are in short connection, and zero clearing is started;
setting the reset signal rst to be low level at the time of t2 to obtain an image reset signal under low conversion gain;
when a low conversion gain zero clearing switch lcg _ cmp _ az is turned off at the time of t3, a ramp voltage lcg _ vramp starts to fall at the time of t4, a count enable lcg _ count _ en starts to count down, a ramp voltage lcg _ vramp and pixout _ a are coupled to Vinp and Vinn of the comparator 501 through capacitors, and Vinp and Vinn are overlapped, the comparator 501 outputs 0, counting is stopped, a reset signal under low conversion gain is obtained, quantization of the low conversion gain reset signal is finished at the time of t5, and the lcg _ vramp returns to a reference state;
at the time t6, the selection switch lcg _ en of the low conversion gain and high conversion gain analog-to-digital conversion circuit is turned off, at the time t7, the selection switch hcg _ en is turned on, and the pixel output pixout _ a and the high conversion gain analog-to-digital conversion circuit are turned on;
at time t7, the conversion gain control signal DCG is set to low level, the DCG transistor 202a is turned off, and a reset signal under high conversion gain is obtained;
when a high conversion gain zero clearing switch lcg _ cmp _ az is turned off at the time of t8, a hcg _ vramp ramp voltage starts to fall at the time of t9, a high conversion gain enable hcg _ count _ en starts to count down, hcg _ vramp ramp voltage and pixout _ a are coupled to Vinp and Vinn of the comparator 504 through capacitors, and Vinp and Vinn are overlapped, the comparator 504 outputs 0, counting is stopped, a reset signal under high conversion gain is obtained, quantization of the reset signal under high conversion gain is finished at the time of t10, and the hcg _ vramp ramp voltage starts to return to a reference state;
at the time point from t11 to t12, the control signal txa is set to be at a high level, the transmission transistor 203a is turned on to start transmitting the image signal, and the pixel output pixout _ a is coupled to the comparator Vinn through the capacitor to obtain the image signal under high conversion gain;
at time t13, hcg _ vramp ramp voltage starts to fall, high conversion gain count enable hcg _ count _ en starts to count up, hcg _ vramp ramp voltage and pixout _ a are capacitively coupled to Vinp and Vinn of the comparator 504, when the Vinp and Vinn are overlapped, the comparator outputs 0, counting is stopped, a difference value between an image signal under high conversion gain and a reset signal is obtained, namely, an image quantization value of correlated double sampling is obtained under high conversion gain, at time t14, the high conversion gain image signal quantization is finished, and hcg _ vramp ramp voltage starts to return to a reference state;
at time t15, the selection switch hcg _ en is turned off, at time t16, the selection switch lcg _ en is turned on, and the pixel output pixout _ a and the low conversion gain analog-to-digital conversion circuit are turned on;
at time t16, the control signal DCG is set to high level, the DCG transistor 202a is turned on, and the pixel array circuit is switched to the low conversion gain mode;
at the time from t17 to t18, the control signal txa is set to be high level, the transmission transistor 203a is turned on to start transmitting the image signal, and pixout _ a is coupled to the comparator Vinn through the capacitor to obtain the image signal under low conversion gain;
at time t19, lcg _ vramp ramp voltage starts to fall, low conversion gain count enable lcg _ count _ en starts to count up, lcg _ vramp ramp voltage and pixout _ a are capacitively coupled to Vinp and Vinn of the comparator 501, when the Vinp and Vinn are overlapped, the comparator 501 outputs 0, counting is stopped, a difference value between an image signal and a reset signal under low conversion gain is obtained, namely, an image quantization value of related double sampling is obtained under low conversion gain, quantization of the image signal is finished under low conversion gain at time t20, and lcg _ vramp ramp voltage returns to a reference state;
the quantization of the pixel circuits is finished, a digital image signal at a low conversion gain and a digital image signal at a high conversion gain are obtained, and then the values of the counters (502 and 505) of the respective analog-to-digital conversion circuits are written into the static memory SRAMs (503 and 506). Similarly, the reading and quantization process of the pixel output pixout _ b of the pixel unit 200b is the same as that of the pixel unit 200a, and is not repeated herein.
In the process of the embodiment, the pixel output of the pixel array is in a complete quantization period, the low conversion gain reset signal, the high conversion gain image signal and the low conversion gain image signal are sequentially read, and the readout circuit respectively performs quantization processing on the signals to realize high dynamic range output of the image sensor. In order to further improve the high dynamic range, the selection switch of the low conversion gain and high conversion gain analog-to-digital conversion circuit selects the read pixel to output to the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit for quantization according to control enabling, and the low conversion gain ramp voltage lcg _ vramp is coupled to the input end of the comparator of the low conversion gain analog-to-digital conversion circuit through a variable capacitor; the high conversion gain ramp voltage hcg _ vramp is coupled to the input of the comparator of the high conversion gain analog-to-digital conversion circuit through a variable capacitor, and the slopes of the low conversion gain ramp voltage lcg _ vramp and the high conversion gain ramp voltage hcg _ vramp can be set to be different, so as to further improve the gain of the circuit. By adjusting the variable capacitance, further circuit gain improvement can also be achieved. Meanwhile, in the process of quantization processing, the low conversion gain and high conversion gain analog-to-digital conversion circuit does not need to sample and hold the pixel output, KT/C noise in the circuit can be reduced, the analog power consumption in the circuit can be lower, and the performance of the image sensor can be improved.
The present embodiments and figures are presented for illustrative purposes and various equivalent modifications are possible in different forms without departing from the broader spirit and scope of the invention. Modifications may be made to the embodiments of the invention in light of the above detailed description. The terms used in the following claims should not be construed to be limited to the specific embodiments disclosed in the specification and the claims. Rather, the full scope of the claims is to be construed according to the established doctrines of claim interpretation. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (15)
1. An HDR image sensor with gain compensation, the image sensor comprising:
an array of pixels;
a control circuit connected to the pixel array, the control circuit controlling to sequentially read a reset signal of low conversion gain, a reset signal of high conversion gain, an image signal of high conversion gain, and an image signal of low conversion gain output from the pixel array;
the reading circuit comprises a selection switch, a low conversion gain analog-to-digital conversion circuit and a high conversion gain analog-to-digital conversion circuit; the low conversion gain analog-to-digital conversion circuit is used for quantizing a reset signal and an image signal which are output by the pixel array under the low conversion gain; the high conversion gain analog-to-digital conversion circuit is used for quantizing a reset signal and an image signal which are output by the pixel array under high conversion gain;
the selection switch is used for controlling and selecting the half-row reading of the pixel output of the pixel array by the readout circuit and switching the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit;
the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit respectively comprise a comparator, a counter and a memory, and a low conversion gain reset signal or an image signal output by the pixel array and a low conversion gain ramp voltage are respectively coupled to two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit through capacitors; and the high conversion gain reset signal or the image signal output by the pixel array and the high conversion gain ramp voltage are respectively coupled to two input ends of the high conversion gain analog-to-digital conversion circuit comparator through capacitors.
2. The HDR image sensor with gain compensation of claim 1, wherein the slopes of the low and high conversion gain ramp voltages are the same or different.
3. The HDR image sensor with gain compensation of claim 2, wherein the low conversion gain ramp voltage is coupled to the input of the low conversion gain analog-to-digital conversion circuit comparator through a variable capacitance; the high conversion gain ramp voltage is coupled to the input end of the high conversion gain analog-to-digital conversion circuit comparator through a variable capacitor.
4. The HDR image sensor with gain compensation of claim 1, wherein the pixel array comprises a plurality of pixel cells arranged in rows and columns, each of the pixel cells comprising one or more photosensitive pixels in a shared structure, each of the photosensitive pixels comprising a photodiode and a transfer transistor connected to the photodiode.
5. The HDR image sensor with gain compensation of claim 4, wherein the multiple photosensitive pixels with shared structure are two or four.
6. The HDR image sensor with gain compensation of claim 4, wherein each pixel unit comprises one or two photosensitive pixels with a shared structure, and the readout circuit reads pixel outputs of two pixel units of the pixel array half-row respectively.
7. The HDR image sensor with gain compensation of claim 5, wherein each of the pixel cells comprises four photosensitive pixels in a shared structure, the four photosensitive pixels in the shared structure being arranged in a 2 x 2 structure, and the readout circuit reads pixel outputs of the pixel cells in half rows.
8. The HDR image sensor with gain compensation of claim 4, wherein the pixel cell comprises a DCG transistor and a capacitor for achieving high gain and low gain conversion of the pixel cell according to a control, the capacitor being a device capacitor or a parasitic capacitor.
9. The HDR image sensor with gain compensation of claim 4 or 8, wherein the pixel cell comprises a reset transistor and a source follower transistor, a drain of the reset transistor and a drain of the source follower transistor being connected to the same fixed voltage source, the pixel cell comprising a row select transistor; or, the drain of the reset transistor is connected to a variable voltage source, the drain of the source follower transistor is connected to a fixed voltage source, and the source of the source follower transistor is connected to a column line.
10. An HDR image sensor readout circuit with gain compensation, the readout circuit comprising:
the selection switch, the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit; the selection switch is used for controlling and selecting the pixel output of the half-row reading pixel array of the readout circuit and switching the pixel output of the pixel array to the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit;
the readout circuit respectively carries out quantization processing on the reset signal with low conversion gain, the reset signal with high conversion gain, the image signal with high conversion gain and the image signal with low conversion gain in sequence;
wherein, the low conversion gain reset signal and the low conversion gain pixel signal output by the pixel are respectively read to the low conversion gain analog-to-digital conversion circuit for quantization processing; the high conversion gain reset signal and the high conversion gain pixel signal output by the pixel are respectively read to the high conversion gain analog-to-digital conversion circuit for quantization processing;
the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit respectively comprise a comparator, a counter and a memory, and a low conversion gain reset signal or an image signal output by the pixel and a low conversion gain ramp voltage are respectively coupled to two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit through capacitors; and the high conversion gain reset signal or the image signal output by the pixel and the high conversion gain ramp voltage are respectively coupled to two input ends of the high conversion gain analog-to-digital conversion circuit comparator through capacitors.
11. The HDR image sensor readout circuit with gain compensation of claim 10, wherein the low conversion gain ramp voltage is coupled to an input of the low conversion gain analog-to-digital conversion circuit comparator through a variable capacitance; the high conversion gain ramp voltage is coupled to the input end of the high conversion gain analog-to-digital conversion circuit comparator through a variable capacitor.
12. The HDR image sensor readout circuit with gain compensation of claim 10, wherein the slopes of the low and high conversion gain ramp voltages are the same or different.
13. An HDR image sensor implementation method with gain compensation, the method comprising:
the pixel array provides a pixel output;
according to the control selection of the selection switch, the pixel output half-line reading is carried out on the low conversion gain analog-to-digital conversion circuit or the high conversion gain analog-to-digital conversion circuit for quantization processing;
sequentially quantizing the low conversion gain reset signal, the high conversion gain image signal and the low conversion gain image signal to obtain a digital image signal under low conversion gain and a digital image signal under high conversion gain;
the low conversion gain reset signal and the low conversion gain image signal output by the pixel are respectively read to the low conversion gain analog-to-digital conversion circuit for quantization processing; reading a high conversion gain reset signal and a high conversion gain image signal output by the pixel to the high conversion gain analog-to-digital conversion circuit for quantization processing;
the low conversion gain analog-to-digital conversion circuit and the high conversion gain analog-to-digital conversion circuit respectively comprise a comparator, a counter and a memory, and a low conversion gain reset signal or an image signal output by the pixel and a low conversion gain ramp voltage are respectively coupled to two input ends of the comparator of the low conversion gain analog-to-digital conversion circuit through capacitors; and the high conversion gain reset signal or the image signal output by the pixel and the high conversion gain ramp voltage are respectively coupled to two input ends of the high conversion gain analog-to-digital conversion circuit comparator through capacitors.
14. The HDR image sensor implementation with gain compensation of claim 13, wherein the low conversion gain ramp voltage is coupled to the input of the low conversion gain analog-to-digital conversion circuit comparator through a variable capacitance; the high conversion gain ramp voltage is coupled to the input end of the high conversion gain analog-to-digital conversion circuit comparator through a variable capacitor.
15. The HDR image sensor implementation with gain compensation of claim 13, wherein the slopes of the low and high conversion gain ramp voltages are the same or different.
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| CN110233979B (en) * | 2019-06-06 | 2021-11-19 | 锐芯微电子股份有限公司 | Image sensor, reading circuit thereof and pixel structure |
| CN110351500B (en) * | 2019-07-09 | 2021-08-31 | 西安微电子技术研究所 | CMOS image sensor reading circuit compatible with two exposure modes |
| CN111901542B (en) * | 2020-08-07 | 2023-02-17 | 成都微光集电科技有限公司 | Image sensor |
| CN111988548B (en) * | 2020-08-25 | 2023-05-19 | 中国电子科技集团公司第二十四研究所 | Pixel-level ADC focal plane readout circuit and correction method thereof |
| CN113038042B (en) * | 2021-03-22 | 2023-10-13 | 豪威科技(上海)有限公司 | Dual conversion gain image sensor |
| CN115633265A (en) * | 2022-09-30 | 2023-01-20 | 维沃移动通信有限公司 | Photosensitive pixel structure, image sensor and electronic device |
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