CN210958544U - Global exposure image sensor - Google Patents
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- CN210958544U CN210958544U CN201921820113.0U CN201921820113U CN210958544U CN 210958544 U CN210958544 U CN 210958544U CN 201921820113 U CN201921820113 U CN 201921820113U CN 210958544 U CN210958544 U CN 210958544U
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Abstract
The utility model provides a global exposure image sensor, image sensor's sample hold unit includes reset signal sampling memory cell and the image signal sampling memory cell that parallel connection set up, comprises one or more control transistor and electric capacity respectively. The reset signal sampling storage unit is used for storing and controlling reset signals of the reading pixel circuit, and the image signal sampling storage unit is used for storing and controlling image signals of the reading pixel circuit. The reading circuit and the control circuit of the image sensor read, control and quantize the reset signal and the image signal output by the pixel array, realize the related double sampling of the reset signal and the image signal according to different design structures and reading modes of the sampling and holding unit, and obtain the effective value of the output image through calculation. The utility model provides a global exposure image sensor's implementation scheme compares among content and the prior art, can effectively simplify pixel circuit's chronogenesis operation, realizes littleer CDS computational error.
Description
Technical Field
The utility model relates to an image sensor technical field especially relates to a sample and hold unit adopts parallel design structure and reads the image sensor design that operation realized global exposure.
Background
The CMOS image sensor is widely applied to various fields, such as digital cameras, unmanned planes, video monitoring equipment, automatic driving and the like. A typical image sensor design has two exposure modes, a rolling shutter mode (rolling shutter) and a global shutter mode (global shutter). The pixels in the pixel array of the roll-to-roll exposed image sensor are exposed in a scan line by line, first line, second line … through to the last line. The rolling exposure mode is suitable for image acquisition of static objects or environments. When the image sensor in the rolling exposure mode collects a dynamic scene, because the exposure time periods of pixels in each row are different, the real object position when the pixels in the first row collect image signals may be greatly different from the real object position when the pixels in the last row collect image signals, for example, a fast rotating fan for photographing, a running car, and the like, and it is found that the collected image is distorted and distorted (a jelly effect). When the image sensor in the global exposure mode acquires an image, each pixel in the pixel array is exposed at the same time, and after exposure is finished, image signals acquired by the pixels are read one by one. According to the image sensor adopting the global exposure mode, each pixel in the pixel array is synchronously exposed to acquire an image signal, so that the influence caused by the jelly effect can be eliminated. Therefore, the image sensor adopting the global exposure mode is suitable for acquiring the image of the moving object.
The traditional global exposure pixel unit adopts a 5T structure pixel circuit, and the global exposure mode realized by the pixel circuit has some problems and disadvantages. For example, true Correlated Double Sampling (CDS) cannot be realized at the time of signal reading, and thus reset noise of a floating node (FD) cannot be eliminated, and readout noise thereof at the time of pixel output is large. In addition, due to the large leakage current at the floating node, in the signal reading process of the pixel structure, the storage of the signal charges of the pixel which is read later is not complete, so that the quality of an output image is influenced.
The technical scheme disclosed in the invention patent with the publication number of CN102447848B and the name of "CMOS image sensor global exposure pixel unit" is that a first switch and a first sample-and-hold capacitor in a sample-and-hold circuit are arranged in a serial connection structure with a second switch and a second sample-and-hold capacitor. The first sampling holding capacitor samples and saves the image signal, and the second sampling holding capacitor samples and saves the reset signal. The two-part sampling and holding circuit of the serial connection structure in the pixel circuit has complex reading operation time sequence and long shortest exposure time of the pixel circuit. Meanwhile, in the process of sampling the image signal and the reset signal, the process of sequentially sampling the signals is not completely symmetrical based on the serial connection structure of the image signal and the reset signal sampling and holding circuit, and the existing error is larger.
Based on the multiple problem that exists, the utility model provides a global exposure image sensor project organization of innovation and the mode of reading control to solve the multiple problem that global exposure image sensor exists among the prior art, satisfy the application demand.
Disclosure of Invention
An object of the utility model is to provide a global exposure image sensor with innovation pixel circuit structural design, global exposure image sensor's pixel array contains a plurality of pixel element, every that set up according to row and row pixel element includes:
a light sensing unit including a light sensing device, such as a photodiode, and a transfer transistor through which electrons accumulated by a photoelectric effect of the light sensing device are transferred to a floating node;
a reset circuit including a reset transistor, for resetting the node circuit by a reset control signal;
a first output unit including a first source follower transistor having a gate connected to the floating node and a source connected to the bias control transistor, and a bias control transistor controlled by a bias control signal; the first output unit outputs a reset signal voltage and an image signal voltage;
a second output unit including a second source follower transistor and a row select transistor; the row selection transistor is connected to a source output end of the second source follower transistor and is controlled to output to a column line through a row selection control signal;
a sample-and-hold unit connected between the first output unit and the second output unit, for sampling and storing a reset signal voltage and an image signal voltage;
the control circuit and the readout circuit are used for performing reading control and quantization processing on the output of the pixel array of the global exposure image sensor, wherein the quantization processing comprises analog-to-digital conversion and amplification processing;
optionally, the sample-and-hold unit includes a reset signal sample-and-store unit and an image signal sample-and-store unit, and the reset signal sample-and-store unit and the image signal sample-and-store unit are connected in parallel between the output end of the first output unit and the input end of the second output unit;
the reset signal sampling storage unit comprises a reset signal storage control transistor, a reset signal storage capacitor and a reset signal reading control transistor; the reset signal storage control transistor and the reset signal reading control transistor form serial connection, the reset signal storage capacitor is connected to the connection point of the reset signal storage control transistor and the reset signal reading control transistor, and the other end of the reset signal storage capacitor is grounded; the image signal sampling storage unit comprises an image signal storage control transistor, an image signal storage capacitor and an image signal reading control transistor; the image signal storage control transistor and the image signal reading control transistor form a serial connection, the image signal storage capacitor is connected to a connection point of the image signal storage control transistor and the image signal reading control transistor, and the other end of the image signal storage capacitor is grounded; the reset signal storage control transistor and the image signal storage control transistor are respectively connected to a source output end of a first source follower transistor of the first output unit; the reset signal reading control transistor and the image signal reading control transistor are respectively connected to a gate of a second source follower transistor of the second output unit;
the reset signal is controlled to be stored in the reset signal storage capacitor through the reset signal storage control transistor; an image signal is stored in the image signal storage capacitor through the image signal storage control transistor; the reset signal voltage is controlled to be read out through the reset signal reading control transistor, and the image signal voltage is controlled to be read out through the image signal reading control transistor;
the read-out circuit of the global exposure image sensor respectively carries out quantization processing on the read-out reset signal voltage and the image signal voltage to obtain a reset signal voltage value and an image signal voltage value, and the image signal voltage value is subtracted from the voltage value of the reset signal to obtain an effective output image signal value;
optionally, the sample-and-hold unit includes a reset signal sample-and-store unit, an image signal sample-and-store unit, and a read control transistor; the image signal sampling storage unit is connected with the reading control transistor in series and is connected between the first output unit and the second output unit in parallel with the reset signal sampling storage unit; the reset signal sampling storage unit comprises a reset signal storage control transistor and a reset signal storage capacitor, the reset signal storage control transistor is connected between the source output end of the first source follower transistor of the first output unit and the grid of the second source follower transistor of the second output unit, one end of the reset signal storage capacitor is connected to the output end of the reset signal storage control transistor, and the other end of the reset signal storage capacitor is grounded; the image signal sampling storage unit comprises an image signal storage control transistor and an image signal storage capacitor; the image signal storage control transistor is connected between the source output end of the first source follower transistor of the first output unit and the reading control transistor, one end of the image signal storage capacitor is connected to the connection point of the image signal storage control transistor and the reading control transistor, and the other end of the image signal storage capacitor is grounded; the other end of the reading control transistor is connected to the grid electrode of a second source electrode following transistor of the second output unit;
the reset signal is controlled to be stored in the reset signal storage capacitor through the reset signal storage control transistor; an image signal is controlled to be stored in the image signal storage capacitor through the image signal storage control transistor;
reading the reset signal voltage of the reset signal storage capacitor, and quantizing the reset signal voltage by a readout circuit of the global exposure image sensor to obtain a reset signal voltage value; averaging the reset signal voltage stored in the reset signal storage capacitor and the image signal voltage stored in the image signal storage capacitor by controlling the read control transistor, and performing quantization processing by a readout circuit of the global exposure image sensor to obtain an average signal voltage value; subtracting the average signal voltage value from the reset signal voltage value to obtain an effective output image signal value; in the above process, the reading control transistor is turned on, and after the stored reset signal voltage and the image signal voltage are averaged, the reading control transistor may be selectively turned off or kept in an on state;
as another implementation form in this alternative, the reset signal sampling storage unit and the read control transistor in the sampling and holding unit are connected in series, and are connected in parallel with the image signal sampling storage unit between the first output unit and the second output unit; the reset signal sampling storage unit comprises a reset signal storage control transistor and a reset signal storage capacitor; the reset signal storage control transistor is connected between the source output end of the first source follower transistor of the first output unit and the reading control transistor, one end of the reset signal storage capacitor is connected to the connection point of the reset signal storage control transistor and the reading control transistor, and the other end of the reset signal storage capacitor is grounded; the other end of the reading control transistor is connected to the grid electrode of a second source electrode following transistor of the second output unit; the image signal sampling storage unit comprises an image signal storage control transistor and an image signal storage capacitor, the image signal storage control transistor is connected between the source output end of the first source follower transistor of the first output unit and the grid of the second source follower transistor of the second output unit, one end of the image signal storage capacitor is connected to the output end of the image signal storage control transistor, and the other end of the image signal storage capacitor is grounded;
reading the image signal voltage of the image signal storage capacitor, and carrying out quantization processing on the image signal voltage by a reading circuit of the global exposure image sensor to obtain an image signal voltage value; averaging the reset signal voltage stored in the reset signal storage capacitor and the image signal voltage stored in the image signal storage capacitor by controlling the read control transistor, and performing quantization processing by a readout circuit of the global exposure image sensor to obtain an average signal voltage value; subtracting the image signal voltage value from the average signal voltage value to obtain an effective output image signal value; in the above process, the reading control transistor is turned on, and after the stored reset signal voltage and the image signal voltage are averaged, the reading control transistor may be selectively turned off or kept in an on state;
optionally, the sample-and-hold unit includes a reset signal sample-and-store unit and an image signal sample-and-store unit, and the reset signal sample-and-store unit includes a reset signal storage control transistor and a reset signal storage capacitor; the image signal sampling storage unit comprises an image signal storage control transistor and an image signal storage capacitor;
the reset signal storage control transistor is connected to the source output end of the first source follower transistor of the first output unit and the grid electrode of the second source follower transistor of the second output unit, one end of the reset signal storage capacitor is connected to the grid electrode of the second source follower transistor of the second output unit, and the other end of the reset signal storage capacitor is grounded; one end of the image signal storage control transistor is connected to the source output end of the first source follower transistor of the first output unit, the other end of the image signal storage control transistor is connected to the image signal storage capacitor, and the other end of the image signal storage capacitor is grounded;
the reset signal is controlled to be stored in the reset signal storage capacitor through the reset signal storage control transistor; an image signal is controlled to be stored in the image signal storage capacitor through the image signal storage control transistor; reading the reset signal voltage of the reset signal storage capacitor, and quantizing the reset signal voltage by a readout circuit of the global exposure image sensor to obtain a reset signal voltage value; averaging the stored reset signal voltage and the stored image signal voltage by controlling the reset signal storage control transistor and the image signal storage control transistor, and performing quantization processing by a reading circuit of the global exposure image sensor to obtain an average signal voltage value; subtracting the average signal voltage value from the reset signal voltage value to obtain an effective output image signal value; in the above reading process, the reset signal storage control transistor and the image signal storage control transistor are turned on, and after the stored reset signal voltage and the stored image signal voltage are averaged, the reset signal storage control transistor and the image signal storage control transistor can be selectively turned off or kept on;
as another implementation form in this alternative, one end of the reset signal storage control transistor in the sample-and-hold unit is connected to a source output end of the first source follower transistor of the first output unit, the other end of the reset signal storage control transistor is connected to the reset signal storage capacitor, and the other end of the reset signal storage capacitor is grounded; the image signal storage control transistor is connected to the source output end of the first source follower transistor of the first output unit and the grid electrode of the second source follower transistor of the second output unit, one end of the image signal storage capacitor is connected to the grid electrode of the second source follower transistor of the second output unit, and the other end of the image signal storage capacitor is grounded;
reading the image signal voltage of the image signal storage capacitor, and carrying out quantization processing on the image signal voltage by a reading circuit of the global exposure image sensor to obtain an image signal voltage value; averaging the stored reset signal voltage and the stored image signal voltage by controlling the reset signal storage control transistor and the image signal storage control transistor, and performing quantization processing by a reading circuit of the global exposure image sensor to obtain an average signal voltage value; subtracting the image signal voltage value from the average signal voltage value to obtain an effective output image signal value; in the above reading process, the reset signal storage control transistor and the image signal storage control transistor are turned on, and after the stored reset signal voltage and the stored image signal voltage are averaged, the reset signal storage control transistor and the image signal storage control transistor can be selectively turned off or kept on;
according to the present invention in its various aspects and inventive contents, the global exposure image sensor may further include:
optionally, the first output unit may be designed to include a first source follower transistor, and a source output terminal of the first source follower transistor is connected to the sample-and-hold unit; the drain electrode of the first source electrode following transistor is connected with a variable voltage source.
The utility model provides a technical invention scheme is applicable to global exposure image sensor design, global exposure image sensor's Sample hold unit adopts parallel structure to carry out storage and read control respectively to reset signal and image signal, realizes CDS (Correlated Double sampling) process. The utility model discloses the scheme is the realization scheme of serial connection mode for among the prior art sample hold unit, can effectively simplify the chronogenesis operation of circuit, can realize the less minimum exposure time of pixel to and pixel circuit's consumption is lower, still less to the impact of power and ground. Meanwhile, due to the design of a parallel connection mode, in the sampling process of the reset signal and the image signal, the matching degree of the signals is good, and smaller CDS calculation errors can be realized.
Drawings
FIG. 1 is a block diagram of the basic system structure of an image sensor;
FIG. 2 is a circuit diagram of a first embodiment of a globally exposed image sensor pixel of the present invention;
FIG. 3 is a timing diagram of a pixel circuit of a global exposure image sensor in a first embodiment;
FIG. 4 is a pixel circuit diagram of another embodiment of the first embodiment of the present invention;
FIG. 5 is a timing diagram of a pixel circuit of another embodiment of the first embodiment of the global exposure image sensor;
fig. 6 is a pixel circuit diagram of a second embodiment of the present invention;
FIG. 7 is a timing diagram of a globally exposed image sensor pixel circuit in a second embodiment;
FIG. 8 is a pixel circuit diagram of another embodiment of a second embodiment of a globally exposed image sensor of the present invention;
fig. 9 is a third embodiment of the present invention, a global exposure image sensor pixel circuit diagram;
FIG. 10 is a timing diagram of a globally exposed image sensor pixel circuit in a third embodiment; and
fig. 11 is a pixel circuit diagram of another application example of the global exposure image sensor according to the third embodiment of the present invention.
Detailed Description
In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the following description is combined with a plurality of drawings provided by the present invention to clearly and completely describe the technical solution in the embodiments of the present invention. Those skilled in the art will appreciate that the embodiments described herein are illustrative of some, but not exhaustive, of the embodiments that the present invention is capable of. Other a plurality of application embodiments that can realize the technical scheme of the utility model also belong to the protection of the utility model.
Fig. 1 is a block diagram of a basic structure of an image sensor system, and as shown in fig. 1, an image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to a pixel array 101, and a data processing/storage module 103 connected to the readout circuit 102 for performing operation processing such as data processing and storage on outputs of the pixel circuits; the state/timing control block 105 is connected to the readout circuit 102 and the control circuit 104, and realizes read control of the pixel array 101. The pixel array 101 includes a plurality of pixel cells in rows (R1, R2, R3 … Ry) and columns (C1, C2, C3 … Cx), and pixel signals output from the pixel array 101 are output to the readout circuit 102 via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out using the readout circuit 102 in which the state/timing control block 105 designates the readout mode, and then transferred to the data processing/storage block 103. In particular applications, the readout circuit 102 may include analog-to-digital conversion (ADC) circuits, amplification circuits, and others. In some embodiments, the state/timing control module 105 may include a programming selection system to determine whether the read is read via a global exposure mode or a rolling exposure mode. The data processing/storing module 103 may store only image data or image data applied or processed by an image effect. In one application, readout circuitry 102 may read out a row of image data at a time along readout column lines (as shown in FIG. 1), or may read out the image data in a variety of other ways. The operation of the control circuit 104 may be determined by the current settings of the state/timing control module 105. For example, the control circuit 104 generates a shutter signal for controlling image acquisition. In some applications, the shutter signal may be a global exposure signal such that all pixels of the pixel array 101 acquire their image data simultaneously through a single acquisition window.
Fig. 2 is a circuit diagram of a pixel circuit of a global exposure image sensor according to a first embodiment of the present invention, as shown in fig. 2, which is a plurality of pixel unit circuits included in a pixel array of the global exposure image sensor. The photo-sensing device photodiode PD transfers the electrons accumulated by the photoelectric effect to the floating node FD through the transfer transistor TX. The reset transistor RST resets the floating node FD via a reset control signal RST. The first source follower transistor SF1 and the Bias control transistor NB constitute a first output unit, the source output terminal of SF1 is connected to the Bias control transistor NB, and the Bias voltage signal Bias _ ctrl controls the conduction of the Bias control transistor NB. The second source follower transistor SF2 and the row select transistor RS constitute a second output unit, the output of RS being connected to the column line Pixout. The sampling and holding unit is arranged between the first output unit and the second output unit and comprises a reset signal sampling and storing unit consisting of a reset signal storage control transistor S _ rst, a reset signal storage capacitor Crst and a reset signal reading control transistor R _ rst, and an image signal sampling and storing unit consisting of an image signal storage control transistor S _ sig, an image signal storage capacitor Csig and an image signal reading control transistor R _ sig. The reset signal sampling storage unit and the image signal sampling storage unit form a parallel connection structure and are arranged between the first output unit and the second output unit. The design of the sampling storage unit adopts a parallel connection mode, so that the time sequence operation of the pixel circuit can be effectively simplified, the shortest exposure time of the pixel can be realized, the power consumption of the pixel circuit is lower, and the impact on a power supply and the ground is less. Meanwhile, in the parallel connection design structure, in the sampling process of the reset signal and the image signal, the matching degree in the signal sampling process is good, and smaller CDS calculation errors can be realized.
Fig. 3 is a timing diagram of a pixel circuit of a global exposure image sensor according to a first embodiment of the present invention, and a working timing sequence corresponding to the first embodiment is given below with reference to fig. 3, so as to explain in detail the contents of the invention scheme given in the first embodiment of the present invention:
t1: the Bias _ ctrl is enabled, the transistors RS, S _ rst, S _ sig, R _ rst and R _ sig are conducted at high level, and all internal nodes in the pixel circuit, sampling capacitors (Crst, Csig) and bit lines (bit lines) are cleared to eliminate the influence of the historical state of the previous operation;
t2: resetting the high level of the control signal rst, resetting the FD, and then resetting the control signal rst to be low;
t3: the high level of the transistor S _ rst is conducted, and the reset signal voltage is amplified by SF1 and then is sampled and stored in a reset signal storage capacitor Crst; TX sets a high level transistor TX to be turned on, electrons accumulated by the photodiode PD are read to a floating node FD, S _ sig is turned on at a high level, and an image signal voltage is amplified by SF1 and then stored in an image signal storage capacitor Csig;
t4: the row selection transistors RS in the pixel array are opened row by row, the voltages stored by the capacitors Crst and Csig are amplified and read by SF2, the reading circuits of the image sensor respectively perform quantization processing to obtain a reset signal voltage value Vrst and an image signal voltage value Vsig, and the effective value of an output image signal Vo is obtained as Vrst-Vsig by CDS subtraction.
As another application example of the first embodiment of the present invention, in the pixel circuit of the global exposure image sensor, the first output unit may be designed to include the first source follower transistor SF1, with the bias control transistor NB removed. The source output terminal of SF1 is connected to the sample-and-hold unit, the drain of SF1 is connected to a variable voltage source Vrsf, and reset signals of the pixel circuit and image signals are controlled by setting a low voltage or a high voltage by Vrsf to be read out from the first output unit. The circuit design of the sample-and-hold unit and the second output unit is the same as the pixel circuit shown in fig. 2 in this embodiment, as shown in fig. 4, and in conjunction with the timing diagram of the pixel circuit shown in fig. 5 in this application example, the specific implementation process of this application embodiment is as follows:
t1: vrsf is switched on to be lower in voltage, transistors RS, S _ rst, S _ sig, R _ rst and R _ sig are conducted at high level, and all internal nodes, sampling capacitors (Crst, Csig) and bit lines in a pixel circuit are subjected to zero clearing operation, so that the influence of the historical state of the previous operation is eliminated;
t2: vrsf turns on high voltage, resets control signal rst high level, resets floating node FD, and then resets control signal rst low;
t3: the high level of the transistor S _ rst is conducted, and the reset signal voltage is amplified by SF1 and then is sampled and stored in a reset signal storage capacitor Crst; TX sets a high level transistor TX to be turned on, electrons accumulated by the photodiode PD are read to a floating node FD, S _ sig is turned on at a high level, and an image signal voltage is amplified by SF1 and then stored in an image signal storage capacitor Csig;
t4: the row selection transistors RS in the pixel array are opened row by row, the voltages stored by the capacitors Crst and Csig are amplified and read through SF2, a reading circuit of the image sensor performs quantization processing to obtain a reset signal voltage value Vrst and an image signal voltage value Vsig, and effective value Vo of an output image signal is obtained by CDS subtraction calculation to obtain Vrst-Vsig.
Fig. 6 is a circuit diagram of a pixel of a global exposure image sensor according to a second embodiment of the present invention, and as shown in fig. 6, a sample-and-hold unit in a pixel unit of the image sensor includes a reset signal sample-and-store unit, an image signal sample-and-store unit, and a read control transistor, which are arranged in parallel. The reset signal sampling storage unit comprises a reset signal storage control transistor S _ rst and a reset signal storage capacitor Crst. The image signal acquisition and storage unit comprises an image signal storage control transistor S _ sig and an image signal storage capacitor Csig. The reading control transistor R _ avg is connected to the image signal acquisition and storage unit in series and used for controlling the signal reading and averaging of the reset signal sampling and storage unit and the image signal sampling and storage unit. The following describes in detail the implementation process of the second embodiment of the present invention with reference to the working timing sequence of the pixel circuit in the second embodiment shown in fig. 7:
t1: the Bias _ ctrl is enabled, the transistors RS, S _ rst, S _ sig and R _ avg are conducted at high levels, and all internal nodes in the pixel circuit, sampling capacitors (Crst, Csig) and bit lines (bit lines) are subjected to zero clearing operation, so that the influence of the historical state of the previous operation is eliminated;
t2: resetting the high level of the control signal rst, resetting the FD, and then resetting the control signal rst to be low;
t3: the high level of the transistor S _ rst is conducted, and the reset signal voltage is amplified by SF1 and then is sampled and stored in a reset signal storage capacitor Crst; TX sets a high level transistor TX to be turned on, electrons accumulated by the photodiode PD are read to a floating node FD, S _ sig is turned on at a high level, and an image signal voltage is amplified by SF1 and then stored in an image signal storage capacitor Csig;
t4: line-by-line operation 1: opening a row selection transistor RS in a pixel array, amplifying and reading a reset signal voltage stored by a capacitor Crst through SF2, and performing quantization processing on a reading circuit of the image sensor to obtain a reset signal voltage value Vrst;
t5: line-by-line operation 2: the read control transistor R _ avg is turned on, the image signal voltage Vsig stored in the capacitor Csig and the reset signal voltage Vrst stored in the Crst are averaged to obtain (Vsig + Vrst)/2, and the resultant is amplified and output by SF2, the readout circuit of the image sensor performs quantization processing to obtain the average value of the signals (Vsig + Vrst)/2, the average value is subtracted from the reset signal voltage value Vrst read out in T4 to obtain Vrst- (Vsig + Vrst)/2 as (Vrst-Vsig)/2, CDS is implemented, and the effective value of the output image signal is obtained as Vo as (Vrst-Vsig)/2.
In the above-described embodiment, during the period T5, after the read control transistor R _ avg is turned on, the image signal voltage Vsig stored in the capacitor Csig and the reset signal voltage Vrst stored in the Crst are averaged, the read control transistor R _ avg may be selectively turned off or the transistor R _ avg may be kept on, as shown by R _ avg (1) and R _ avg (2) in fig. 7. When the mode of closing the R _ avg is selected, the injection of the switch charge is well counteracted in the mode, and the fixed mode noise can be effectively reduced. When the transistor R _ avg is kept to be opened, the mode reduces the switching turnover of the transistor once, and can effectively reduce random noise. Both design methods and applications are within the scope of the present invention.
As another application example of the second embodiment of the present invention, in the pixel circuit of the global exposure image sensor, the first output unit may be designed to include the first source follower transistor SF1, with the bias control transistor NB removed. The source output terminal of SF1 is connected to the sample-and-hold unit, the drain of SF1 is connected to a variable voltage source Vrsf, and reset signals of the pixel circuit and image signals are controlled by setting a low voltage or a high voltage by Vrsf to be read out from the first output unit. The circuit diagram of this application example is shown in fig. 8. In the specific implementation process of this application, except that the Vrsf voltage high/low conversion control is different, the implementation processes in fig. 6 and 7 of the second embodiment may be referred to in other implementation processes, and are not further described herein. The pixel circuit design and implementation provided in this application embodiment are also within the scope of the present invention.
The utility model discloses a plurality of pixel circuit designs that propose in the second embodiment, as another implementation, but read control transistor R _ avg in the sample hold unit serial connection to reset signal sample memory cell, with image signal acquisition memory cell parallel connection between first output unit and second output unit. The specific design connection mode is as follows: the reset signal storage control transistor S _ rst is connected to the output end of the first output unit, and the other end of the reset signal storage control transistor S _ rst is connected to the read control transistor R _ avg in series; the reset signal storage capacitor Crst is connected to a connection point of the reset signal storage control transistor S _ rst and the read control transistor R _ avg, and the other end thereof is grounded. The image signal storage control transistor S _ sig is connected between the first output unit and the second output unit, and one end of the image signal storage capacitor Csig is connected to the output end of the image signal storage control transistor S _ sig, and the other end thereof is grounded. In the implementation process of the pixel circuit of this design, the operation timing and implementation process are similar to the steps described above, and the differences are in the period T4 and the period T5:
t4: opening a row selection transistor RS in the pixel array, amplifying and reading an image signal voltage stored by a capacitor Csig through SF2, and performing quantization processing by a reading circuit of the image sensor to obtain an image signal voltage value Vsig;
t5: the read control transistor R _ avg is turned on, the image signal voltage Vsig stored in the capacitor Csig and the reset signal voltage Vrst stored in the Crst are averaged to obtain (Vsig + Vrst)/2, the (Vsig + Vrst)/2 is amplified and output by SF2, the average value of the signal voltages obtained by quantization processing performed by the readout circuit of the image sensor is (Vsig + Vrst)/2, the (Vsig + Vrst)/2-Vsig is obtained by subtraction from the image signal voltage value Vsig read out in T4, CDS is realized, and the effective value of the output image signal is obtained as Vo-Vrst-Vsig/2.
Fig. 9 is a third embodiment of the present invention, showing a pixel circuit diagram of a global exposure image sensor, in which, as shown in fig. 9, a sample-and-hold unit in a pixel unit of the image sensor includes a reset signal sampling storage unit and an image signal sampling storage unit which are connected in parallel. The reset signal sampling storage unit comprises a reset signal storage control transistor S _ rst and a reset signal storage capacitor Crst and is connected between the first output unit and the second output unit. The image signal acquisition and storage unit comprises an image signal storage control transistor S _ sig and an image signal storage capacitor Csig, the image signal storage control transistor S _ sig is connected to the first output unit and is connected with the image signal storage capacitor Csig in series, and the other end of the image signal storage capacitor Csig is grounded. The following describes the operation timing sequence of the pixel circuit in the third embodiment with reference to fig. 10 in detail, the contents of the invention proposed in this embodiment:
t1: the Bias _ ctrl is enabled, the transistors RS, S _ rst and S _ sig are conducted at high levels, and clear operation is carried out on all internal nodes in the pixel circuit, sampling capacitors (Crst, Csig) and bit lines (bit lines) so as to eliminate the influence of the historical state of the previous operation;
t2: resetting the high level of the control signal rst, resetting the FD, and then resetting the control signal rst to be low;
t3: the high level of the transistor S _ rst is conducted, and the reset signal voltage is amplified by SF1 and then is sampled and stored in a reset signal storage capacitor Crst; TX sets a high level transistor TX to be turned on, electrons accumulated by the photodiode PD are read to a floating node FD, S _ sig is turned on at a high level, and an image signal voltage is amplified by SF1 and then stored in an image signal storage capacitor Csig;
t4: line-by-line operation 1: opening a row selection transistor RS in a pixel array, amplifying and reading a reset signal voltage stored by a capacitor Crst through SF2, and performing quantization processing on a reading circuit of the image sensor to obtain a reset signal voltage value Vrst;
t5: line-by-line operation 2: the transistors S _ rst and S _ sig are turned on, the image signal voltage Vsig stored in the capacitor Csig and the reset signal voltage Vrst stored in the Crst are averaged to obtain (Vsig + Vrst)/2, the (Vsig + Vrst)/2 is amplified and output by SF2, the readout circuit of the image sensor performs quantization processing to obtain the average value of the signal voltages (Vsig + Vrst)/2, the difference is subtracted from the reset signal voltage value Vrst read out in T4 to obtain (Vrst-Vsig)/2, CDS is implemented, and the effective value of the output image signal is obtained as Vo ═ Vrst-Vsig)/2.
In the invention scheme of the third embodiment, after the period T5, the transistors S _ rst and S _ sig are turned on, and the image signal voltage Vsig stored in the capacitor Csig and the reset signal voltage Vrst stored in the capacitor Csig are averaged, the transistors S _ rst and S _ sig may be selectively turned off or the transistors S _ rst and S _ sig may be kept on, as shown in S _ rst (1) and S _ sig (1), and S _ rst (2) and S _ sig (2) in fig. 10. When the mode of closing S _ rst and S _ sig is selected, the charge injection cancellation is better in the switching mode, and the noise of the fixed mode can be effectively reduced. When the transistors S _ rst and S _ sig are kept turned on, the mode reduces the switching turnover of the transistors once, and can effectively reduce random noise. Both designs and applications are within the scope of the present embodiment as defined and protected.
As another application example of the third embodiment of the present invention, in the pixel circuit of the global exposure image sensor, the first output unit may be designed to include the first source follower transistor SF1, with the bias control transistor NB removed. The source output terminal of SF1 is connected to the sample-and-hold unit, the drain of SF1 is connected to a variable voltage source Vrsf, and reset signals of the pixel circuit and image signals are controlled by setting a low voltage or a high voltage by Vrsf to be read out from the first output unit. A circuit diagram of this application embodiment is shown in fig. 11. In the specific implementation process of this application, except that the Vrsf voltage high/low conversion control is different, the implementation process may refer to the implementation processes in fig. 9 and 10 of the third embodiment, and will not be further described herein. The pixel circuit design and implementation presented in this application embodiment are also within the scope of the present disclosure.
The utility model discloses a plurality of pixel circuit designs that propose in the third embodiment, as another implementation, its sample hold unit can design as: the reset signal storage control transistor S _ rst is connected to the output end of the first output unit, the other end of the reset signal storage control transistor S _ rst is connected to the reset signal storage capacitor Crst, and the other end of the reset signal storage capacitor Crst is grounded. The image signal storage control transistor S _ sig is connected between the first output unit and the second output unit, one end of the image signal storage capacitor Csig is connected to the output end of the image signal storage control transistor S _ sig, and the other end is grounded. In the specific implementation process of the pixel circuit of this design, the working timing and implementation process thereof are slightly different from those in fig. 9 and 11 of this embodiment, and are mainly embodied in the reading of the image signal and the calculation of the difference after averaging the reset signal and the image signal, that is, the reading and calculation processes in the time periods T4 and T5:
t4: opening a row selection transistor RS in the pixel array, amplifying and reading an image signal voltage stored by a capacitor Csig through SF2, and performing quantization processing by a reading circuit of the image sensor to obtain an image signal voltage value Vsig;
t5: the transistors S _ rst and S _ sig are turned on, the image signal voltage Vsig stored in the capacitor Csig and the reset signal voltage Vrst stored in the Crst are averaged to obtain (Vsig + Vrst)/2, the (Vsig + Vrst)/2 is amplified and output by SF2, the readout circuit of the image sensor performs quantization processing to obtain the average value of the signal voltages (Vsig + Vrst)/2, the (Vsig + Vrst)/2-Vsig is obtained by subtraction from the image signal voltage value Vsig read out in T4, CDS is realized, and the effective value of the output image signal Vo is (Vrst-Vsig)/2.
The utility model discloses a global exposure image sensor design that the invention scheme that a plurality of concrete embodiments and extend record in the application embodiment provided adopts the sample hold unit of multiple parallel connection mode and different read control, realizes the relevant two sampling process to pixel circuit's reset signal and image signal. The design mode can effectively simplify the time sequence operation of the circuit, realize the smaller shortest exposure time of the pixel circuit, lower the power consumption of the pixel circuit and less impact on a power supply and the ground. Adopt the utility model provides a parallel connection mode design, reset signal and image signal's sampling process among the pixel circuit, the matching degree of signal is good, and the calculation error of CDS can be littleer, further improves global exposure image sensor's performance.
The various embodiments and figures of the present invention are presented for illustrative purposes and equivalent modifications of different forms are possible without departing from the broader spirit and scope of the invention. The embodiments of the present invention can be modified according to the above detailed description, and the modifications are considered to fall within the scope of the present invention. The terms used in the following claims should not be construed to be limited to the specific embodiments disclosed in the specification and the claims. Rather, the full scope of the claims is to be construed according to the established doctrines of claim interpretation. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (29)
1. A globally exposed image sensor, wherein a pixel cell in a pixel array of the globally exposed image sensor comprises:
a first output unit outputting a reset signal voltage and an image signal voltage;
a second output unit including a second source follower transistor and a row select transistor;
a sample-and-hold unit connected between the first output unit and the second output unit, the sample-and-hold unit including a reset signal sample-and-store unit and an image signal sample-and-store unit connected in parallel;
a control circuit and a readout circuit for performing read control and quantization processing on the output of the pixel array;
the second output unit outputs the stored reset signal voltage and the image signal voltage, respectively; the effective value of the image signal output by the global exposure image sensor is the difference value of the reset signal voltage and the image signal voltage after the respective quantization processing.
2. The global exposure image sensor according to claim 1, wherein the reset signal sampling storage unit includes a reset signal storage control transistor, a reset signal storage capacitance, and a reset signal read control transistor; the reset signal storage control transistor is connected to the output end of the first output unit; the reset signal storage control transistor and the reset signal reading control transistor are connected in series; the reset signal storage capacitor is connected to a connection point of the reset signal storage control transistor and the reset signal reading control transistor, and the other end of the reset signal storage capacitor is grounded.
3. The global exposure image sensor according to claim 1, wherein the image signal sampling storage unit includes an image signal storage control transistor, an image signal storage capacitor, and an image signal reading control transistor; the image signal storage control transistor is connected to an output end of the first output unit; the image signal storage control transistor and the image signal reading control transistor are connected in series; the image signal storage capacitor is connected to a connection point of the image signal storage control transistor and the image signal reading control transistor, and the other end of the image signal storage capacitor is grounded.
4. The global exposure image sensor according to claim 1, wherein the first output unit includes a first source follower transistor and a bias control transistor connected between a source of the first source follower transistor and a ground line.
5. The global exposure image sensor of claim 1, wherein the first output unit comprises a first source follower transistor, a drain of which is connected to a variable voltage source.
6. A globally exposed image sensor, wherein a pixel cell in a pixel array of the globally exposed image sensor comprises:
a first output unit outputting a reset signal voltage and an image signal voltage;
a second output unit including a second source follower transistor and a row select transistor;
a sample-and-hold unit including a reset signal sample-and-store unit, an image signal sample-and-store unit, and
a read control transistor; the image signal sampling storage unit is connected with the reading control transistor in series and is connected between the first output unit and the second output unit in parallel with the reset signal sampling storage unit;
a control circuit and a readout circuit for performing read control and quantization processing on the output of the pixel array;
the second output unit outputs the stored reset signal voltage, and an average value of the reset signal voltage and the image signal voltage, respectively; the effective value of the image signal output by the global exposure image sensor is the difference value of the reset signal voltage, the reset signal voltage and the average value of the image signal voltage after the respective quantization processing.
7. The global exposure image sensor according to claim 6, wherein the reset signal sampling storage unit includes a reset signal storage control transistor and a reset signal storage capacitor, the reset signal storage control transistor being connected between the first output unit and the second output unit; and one end of the reset signal storage capacitor is connected to the input end of the second output unit, and the other end of the reset signal storage capacitor is grounded.
8. The global exposure image sensor according to claim 6, wherein the image signal sampling storage unit includes an image signal storage control transistor having one end connected to the first output unit and the other end connected to the read control transistor, and an image signal storage capacitor having one end connected to a connection point of the image signal storage control transistor and the read control transistor and the other end grounded.
9. The global exposure image sensor according to claim 7 or 8, wherein the read control transistor is turned on, and after the reset signal voltage stored in the reset signal sampling storage unit and the image signal voltage stored in the image signal sampling storage unit are averaged, the read control transistor is turned off or kept on.
10. The global exposure image sensor according to claim 6, wherein the first output unit includes a first source follower transistor and a bias control transistor connected between a source of the first source follower transistor and a ground line.
11. The global exposure image sensor of claim 6, wherein the first output unit comprises a first source follower transistor, a drain of which is connected to a variable voltage source.
12. A globally exposed image sensor, wherein a pixel cell in a pixel array of the globally exposed image sensor comprises:
a first output unit outputting a reset signal voltage and an image signal voltage;
a second output unit including a second source follower transistor and a row select transistor;
a sample-and-hold unit including a reset signal sample-and-store unit, an image signal sample-and-store unit, and
a read control transistor; the reset signal sampling storage unit is connected with the reading control transistor in series and is connected between the first output unit and the second output unit in parallel with the image signal sampling storage unit;
a control circuit and a readout circuit for performing read control and quantization processing on the output of the pixel array;
the second output unit outputs the stored image signal voltage, and an average value of the reset signal voltage and the image signal voltage, respectively; the effective value of the image signal output by the global exposure image sensor is the difference value between the reset signal voltage and the image signal voltage average value after the respective quantization processing and the image signal voltage.
13. The global exposure image sensor according to claim 12, wherein the reset signal sampling storage unit includes a reset signal storage control transistor having one end connected to the first output unit and the other end connected to the read control transistor, and a reset signal storage capacitor having one end connected to a connection point of the reset signal storage control transistor and the read control transistor and the other end grounded.
14. The global exposure image sensor according to claim 12, wherein the image signal sampling storage unit includes an image signal storage control transistor and an image signal storage capacitor, the image signal storage control transistor being connected between the first output unit and the second output unit; one end of the image signal storage capacitor is connected to the input end of the second output unit, and the other end of the image signal storage capacitor is grounded.
15. The global exposure image sensor according to claim 13 or 14, wherein the read control transistor is turned on, and after the reset signal voltage stored in the reset signal sampling storage unit and the image signal voltage stored in the image signal sampling storage unit are averaged, the read control transistor is turned off or kept on.
16. The global exposure image sensor of claim 12, wherein the first output unit includes a first source follower transistor and a bias control transistor connected between a source of the first source follower transistor and ground.
17. The global exposure image sensor of claim 12, wherein the first output unit comprises a first source follower transistor, a drain of the first source follower transistor being connected to a variable voltage source.
18. A globally exposed image sensor, wherein a pixel cell in a pixel array of the globally exposed image sensor comprises:
a first output unit outputting a reset signal voltage and an image signal voltage;
a second output unit including a second source follower transistor and a row select transistor;
a sample-and-hold unit including a reset signal sample-and-store unit and an image signal sample-and-store unit, the reset signal sample-and-store unit being connected between the first output unit and the second output unit, the image signal sample-and-store unit being connected between the first output unit and ground;
a control circuit and a readout circuit for performing read control and quantization processing on the output of the pixel array;
the second output unit outputs the stored reset signal voltage, and an average value of the reset signal voltage and the image signal voltage, respectively; the effective value of the image signal output by the global exposure image sensor is the difference value of the reset signal voltage, the reset signal voltage and the average value of the image signal voltage after the respective quantization processing.
19. The global exposure image sensor according to claim 18, wherein the reset signal sampling storage unit includes a reset signal storage control transistor and a reset signal storage capacitor, the reset signal storage control transistor being connected between the first output unit and the second output unit; and one end of the reset signal storage capacitor is connected to the input end of the second output unit, and the other end of the reset signal storage capacitor is grounded.
20. The global exposure image sensor according to claim 19, wherein the image signal sampling storage unit includes an image signal storage control transistor and an image signal storage capacitor, the image signal storage control transistor has one end connected to the first output unit output terminal and the other end connected to the image signal storage capacitor, and the other end of the image signal storage capacitor is grounded.
21. The global exposure image sensor according to claim 20, wherein the reset signal storage control transistor and the image signal storage control transistor are turned on, and after the reset signal voltage stored in the reset signal sampling storage unit and the image signal voltage stored in the image signal sampling storage unit are averaged, the reset signal storage control transistor and the image signal storage control transistor are turned off or kept on.
22. The global exposure image sensor of claim 18, wherein the first output unit includes a first source follower transistor and a bias control transistor connected between a source of the first source follower transistor and ground.
23. The global exposure image sensor of claim 18, wherein the first output unit comprises a first source follower transistor, a drain of the first source follower transistor being connected to a variable voltage source.
24. A globally exposed image sensor, wherein a pixel cell in a pixel array of the globally exposed image sensor comprises:
a first output unit outputting a reset signal voltage and an image signal voltage;
a second output unit including a second source follower transistor and a row select transistor;
a sample-and-hold unit including a reset signal sample-and-store unit and an image signal sample-and-store unit, the reset signal sample-and-store unit being connected between the first output unit and ground, the image signal sample-and-store unit being connected between the first output unit and the second output unit;
a control circuit and a readout circuit for performing read control and quantization processing on the output of the pixel array; the second output unit outputs the stored image signal voltage, and an average value of the reset signal voltage and the image signal voltage, respectively; the effective value of the image signal output by the global exposure image sensor is the difference value between the reset signal voltage and the image signal voltage average value after the respective quantization processing and the image signal voltage.
25. The global exposure image sensor according to claim 24, wherein the reset signal sampling storage unit includes a reset signal storage control transistor and a reset signal storage capacitor, the reset signal storage control transistor has one end connected to the first output unit output terminal and the other end connected to the reset signal storage capacitor, and the other end of the reset signal storage capacitor is grounded.
26. The global exposure image sensor according to claim 25, wherein the image signal sampling storage unit includes an image signal storage control transistor and an image signal storage capacitor, the image signal storage control transistor being connected between the first output unit and the second output unit; one end of the image signal storage capacitor is connected to the input end of the second output unit, and the other end of the image signal storage capacitor is grounded.
27. The global exposure image sensor according to claim 26, wherein the reset signal storage control transistor and the image signal storage control transistor are turned on, and after the reset signal voltage stored in the reset signal sampling storage unit and the image signal voltage stored in the image signal sampling storage unit are averaged, the reset signal storage control transistor and the image signal storage control transistor are turned off or kept on.
28. The global exposure image sensor of claim 24, wherein the first output unit includes a first source follower transistor and a bias control transistor connected between a source of the first source follower transistor and ground.
29. The global exposure image sensor of claim 24, wherein the first output unit comprises a first source follower transistor, a drain of the first source follower transistor being connected to a variable voltage source.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110611782A (en) * | 2019-10-28 | 2019-12-24 | 思特威(上海)电子科技有限公司 | Global exposure image sensor |
| CN114286028A (en) * | 2021-12-31 | 2022-04-05 | 上海集成电路装备材料产业创新中心有限公司 | Image sensor and timing control method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110611782A (en) * | 2019-10-28 | 2019-12-24 | 思特威(上海)电子科技有限公司 | Global exposure image sensor |
| CN110611782B (en) * | 2019-10-28 | 2024-06-18 | 思特威(上海)电子科技股份有限公司 | Global exposure image sensor |
| CN114286028A (en) * | 2021-12-31 | 2022-04-05 | 上海集成电路装备材料产业创新中心有限公司 | Image sensor and timing control method thereof |
| CN114286028B (en) * | 2021-12-31 | 2023-07-25 | 上海集成电路装备材料产业创新中心有限公司 | Image sensor and time sequence control method thereof |
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