WO2024050718A1

WO2024050718A1 - Logical circuit and operation method in digital correlated double sampling

Info

Publication number: WO2024050718A1
Application number: PCT/CN2022/117556
Authority: WO
Inventors: Takao Ishii; Yu SHA
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-09-07
Filing date: 2022-09-07
Publication date: 2024-03-14

Abstract

A logic circuit (34) comprises a first logic circuit, a second logic circuit and a selector. The first logic circuit is configured to output a first operation result. The second logic circuit is configured to output a second operation result. The first operation result is a result of an exclusive-OR operation to input bits. The second operation result is a result of an exclusive-OR operation to input bits including the first operation result. In a code conversion mode, the selector outputs the second operation result, the input bits to the first logic circuit includes a bit in gray code representation and a bit in binary code representation of a second number-to-be-added, and the input bits to the second logic circuit further includes a bit in gray code representation of the second number-to-be-added. In an addition mode, the selector outputs a carry bit in an addition of a first number-to-be-added and the second number-to-be-added, the input bits to the first logic circuit includes a bit of the first number-to-be-added and a carry bit of a digit lower than the carry bit, and the input bits to the second logic circuit includes a bit of the second number-to-be added.

Description

LOGICAL CIRCUIT AND OPERATION METHOD IN DIGITAL CORRELATED DOUBLE SAMPLING

TECHNICAL FIELD

Embodiments disclosed herein relate to a logical circuit and an operation method in a digital correlated double sampling (CDS) , or more generally, in a correlated multiple sampling (CMS) .

BACKGROUND ART

It is required to design mobile terminals such as smartphones and tablets, to have low power consumption because of their requirements for long time operations. The low power consumption also helps to suppress the generation of thermal radiation, which may cause performance degradation such as noise, dark current, or the like.

Since most of the mobile terminals include one or more image sensors, the image sensor, particularly an analog-to-digital converter (ADC) also should operate with low power consumption.

Figure 1 illustrates a partial configuration of an image sensor 10. For example, the image sensor 10 may be a CMOS image sensor. In the image sensor 10, sensor elements are arranged in an array, each of which converts a certain physical quantity into an electric signal, and the output signals of the sensor elements are used for a sensing. The image sensor 10 may be used for any sensor, e.g., a finger print sensor.

In Figure 1, a plurality of pixels 11, a row decode circuit 12, a read-out circuit 13, a horizontal scanner 18, a ramp waveform generator (RAMP) 16, and a clock supplier (CLK) 17 are depicted. Figure 1 illustrates elements which relate to the following description. However, in actuality, other elements may exist. The read-out circuits 13 are provided for every column, each of the read-out circuits 13 including a comparator 14 and a counter &latch circuit 15. The ramp waveform generator 16 and the clock supplier 17 are shared among a plurality of read-out circuits 13.

Each of the plurality of pixels 11 has the same configuration and the same functions. A pixel 11 located in the n-th row and the m-th column is used as a representative example to describe operations. The pixel 11 depicted in Figure 1 includes a photodiode (PD) of which an anode is connected to a low power supply V _SS (for example, V _SS may be GND) ; a transfer transistor Tr1 connected between a cathode of the PD and a floating diffusion layer (FD) ; and a reset transistor Tr2 connected between the floating diffusion layer (FD) and a high power supply V _DD. Although only one PD is depicted, a plurality of PDs and Tr1s may be connected to the floating diffusion layer (FD) . The pixel 11 further includes an amplification transistor Tr3 forming a source follower in which a gate receiving an input voltage is connected to the floating diffusion layer; and a selection transistor Tr4 which controls a connection between Tr3 and the output signal line (the data line D _m in Figure 1) . A current source CS is connected to the output signal line D _m, and supplies a source follower bias current.

The row decode circuit 12 controls selections of the pixels 11 and operations of the pixels 11. Basically, the pixels 11 are selected by driving (activating or deactivating) a selection signal SEL _n and a transfer signal TG _n, x. In an example depicted in Figure 1, operations of some signals, such as a reset signal RST _n, the transfer signal TG _n, x, and the selection signal SEL _n are controlled by means of the vertical scanner. The level shifter converts the levels of these kinds of signals to appropriate levels for the pixel 11. The selection signal SEL _n and the transfer signal TG _n, x may be referred to as a scan line. Since the scan line is connected to the plurality of pixels 11, the plurality of pixels may be designated at once by designating one scan line.

The read-out circuits 13 may read analog data from the pixels 11 through the plurality of data lines (... D _m, D _m+1, ... ) , convert it to digital data, then send the converted data to the horizontal scanner 18. More specifically, the comparator 14 receives the analog voltage signal of the pixel 11 and a ramp waveform signal, which gradually decreases in a predetermined ratio, and the comparator 14 compares them. The counter &latch circuit 15 stores a level (digital value) corresponding to a timing at which the ramp waveform signal and the analog voltage signal cross. The stored level will be provided to the horizontal scanner 18 at an appropriated timing. Thus, the read-out circuit 13 may function as an analog-to-digital converter (ADC) . The comparator 14 depicted in Figure 1 includes a differential amplifier.

The plurality of read-out circuits (ADCs) 13 depicted in Figure 1 may operate in parallel. Each of the read-out circuit 13 operates in a time division multiplexed manner with respect to the k pixels. “k” indicates the number of pixels connected in parallel to one read-out circuit 13. In the example in Figure 1, the following operations are repeated k times: reading the analog signal from one pixel 11, then outputting the digital signal corresponding to the analog signal (i.e., analog-to-digital conversion) . The number of pixels (specifically, the number of rows and the number of columns) may be any suitable positive integer. For example, the number of rows and the number of columns may be hundreds, thousands, or the like.

The analog signal being read from the pixel 11 may include some noise. For example, it may include error components such as feedthrough due to the switching of the reset transistor Tr2, kTC noise of the diffusion capacitance, or the like. In terms of appropriately eliminating such noise effect, it is desirable to perform a correlated double sampling (CDS) .

Figure 2 shows an explanation diagram to describe the correlated double sampling (CDS) . In Figure 2, the selection signal SEL _n, an AZ switch signal AZ_SW of the comparator 14, an input signal INN of a negative side input port of the comparator 14, an input signal INP of a positive side input port of the comparator 14, an output signal OUT of the comparator 14, and a counter value, in an example of measuring a signal level of a pixel 11, are depicted.

With reference to Figure 1 and Figure 2, operations are described. First, two AZ switches AZ_SW change from an open state, through a closed state, to the open state, then the inputs (INP, INN) of the comparator 14 are reset to a predetermined voltage level (Auto Zero) . Preferably, the predetermined voltage level is a high voltage level (hereinafter referred to as “a high voltage level” ) . In this situation, the floating layer FD, which is the input to the pixel source follower, is pre-charged to a known level (e.g., V _DD) by toggling the reset transistor Tr2. The term “toggling” refers to an operation of OFF-ON-OFF, which may be referred to as “switching” .

After the AZ_SW is returned to the open state (OFF) , the voltage provided to the input port INP of the comparator 14 changes from the high voltage level, depending on the variation of the ramp waveform from the level of the AZ_SW closed. i.e., the variation of the output level of the ramp waveform generator from the voltage level in the “Auto Zero” period. Similar to the INP, the voltage provided to the INN also changes from the high voltage level, depending on the variation of the analog input level at the AZ_SW closed state, i.e., the variation of the FD level or the source follower output. During a period in which Tr1 and Tr2 are in OFF state, Tr4 is turned ON in pixel 11, the analog signal corresponding to the level of the floating diffusion layer (FD) is provided to the input port INN of the comparator 14. This level of the floating diffusion layer (FD) at this situation may be referred to as a reference level.

Next, the ramp waveform signal provided to the input port INP of the comparator 14, generally, gradually decreases from a high level to a low level over time. The changing step width is determined by a resolution of the analog-to-digital conversion. It is possible to determine the reference voltage level by measuring a timing when the analog voltage signal level and the ramp voltage signal level become same. At this timing, the output of the comparator 14 changes, e.g., from Low to High. As described above, this reference voltage level may include error components such as kTC noise of the diffusion capacitance, feedthrough that may occur when the AZ_SW is returned to the open state, or the like, .

Next, the charge stored in the photodiode (PD) in the pixel 11 is converted to the input voltage of the comparator 14. Specifically, the photo electrons stored in the photodiode (PD) depending on an amount of light are transferred to the floating diffusion layer (FD) by toggling (or switching) the transfer transistor Tr1 of the pixel 11, and the analog voltage signal having a magnitude corresponding to the amount of photo electrons is generated according to a proportionality coefficient, which is product of inverse of the capacitance of the floating diffusion layer (FD) , and the source follower gain. The analog voltage signal is provided to the input port INN of the comparator 14. This voltage is generated by adding <the voltage corresponding to the amount of the photo electrons from the pixel 11> to <the reference voltage level>. More exactly speaking, the former is set to be a negative number, the latter is set to be a positive number, they are added, then the difference of them is measured. The analog voltage signal of the photodiode (PD) is largely and transiently fluctuated until it stabilizes immediately after the input. This is because there are capacitive coupling of Tr1, Tr3 and Tr4 accompanying the photon electron transfer. As long as there is no risk of confusion, “a reference (signal) level” may also be referred to as “a known (signal) level” while the analog voltage signal level of the photodiode (PD) may be referred to as “an unknown (signal) level” .

As shown in Figure 2, when an electron is used as a signal carrier, a voltage corresponding to an amount of photo electrons, usually, falls below the reference voltage. Thus, when photo electrons stored in the photodiode (PD) are at a maximum level, a “MAX” level may be obtained, and while it is at a minimum level, a “MIN” level may be obtained. Thus, in actuality, a single waveform will be drawn between the MAX level line and the MIN level line. It should be noted that a characteristic of the photodiode (PD) , a characteristic of the floating diffusion layer (FD) , a maximum output range of the source follower, or the like are designed such that the ramp waveform can cover a detectable maximum amount of charge.

In this example, the reference level corresponds to a higher limit value of the ADC’s acceptable voltage, and it is assumed that the input voltage within the acceptable range is equal to or less than the reference level. However, this is not essential for the embodiments. For example, in case where a polarity of the signal charge is different (e.g., holes) , magnitude relations of the voltages are all reversed. Such cases are also included in the scope of this application.

The ramp waveform signal provided to the input port INP of the comparator 14, generally, gradually decreases from the high level to the low level over time. The changing step width is determined by a resolution of the analog-to-digital conversion. The changing range of the ramp signal (the range between the high level and the low level) may or may not be same as the range used in the reference level measurement. In any case, it is determined such that the reference level and the unknown signal level (the voltage at the input port INN) are within their respective ranges of the ramp signal. It is possible to determine the pixel voltage corresponding to the state of the photodiode (PD) by measuring a timing when the analog voltage signal level and the ramp voltage signal level become the same.

Basically, only an AD conversion corresponding to the unknown signal level may be needed. Because it can be said the CDS result is based on analog operation. However, cancelling the error component caused when opening the Auto Zero switches is needed. Thus, generally, the error component is often cancelled by measuring the reference level (Reset ADC) , measuring the analog signal voltage level of the photodiode (PD) , and calculating the difference of them. More specifically speaking, the reference level is represented as a negative number, the unknown signal level is represented as a positive number. The reference level of the negative number may be determined by counting down step-by-step according to the ramp waveform. The difference of the unknown signal level to the reference level may be obtained by counting up step-by-step according to the ramp waveform from the latest count down value. In the example of Figure 2, the correlated double sampling (CDS) , based on digital computation, is completed by sampling the reference level once, and sampling the unknown signal level once. It is named a digital correlated double sampling (digital CDS) . The correlated multiple sampling (CMS) may be performed by repetitively performing the AD conversion (more than two sampling) , i.e., applying the multi-sampling to the reference/unknown level. For example, with regard to one pixel, the reference level may be sampled four times and the unknown signal level may be sampled four times. For convenience, hereinafter, the digital CDS is mentioned simply as CDS.

When the reference level and the unknown signal level are represented as a digital value, straightforwardly, one of the simple ways is to represent them as a binary code. Not only the binary code, but also a gray code may additionally be used. In such a case, initially, a measurement result of the reference level and/or the unknown signal level is represented as a gray code, then it is converted to a binary code for subsequent digital signal process. By using the gray code as well, instead of only the binary code, it is possible to expect to a reduction in an effective frequency, a reduction in power consumption, suppressed bit error, or the like. It is also possible to easily share a gray code counter among a plurality of columns, thereby reducing power consumption more than ever before.

SUMMARY OF THE INVENTION

However, when converting the gray code to the binary code and performing a full addition, the conventional approach is not necessarily efficient. According to one aspect of the present embodiments, it is possible to improve efficiency when converting the gray code to the binary code and performing the full addition in the correlated double sampling.

According to an aspect of the embodiments, a logic circuit (34) configured to operate in a mode of operations including a code conversion mode and an addition mode is provided. The logic circuit includes:

a first logic circuit (LC1) outputting a first operation result, the first operation result being a result of an exclusive-OR operation to input bits;

a second logic circuit (LC2) outputting a second operation result (B _n/X _n) , the second operation result (B _n/X _n) being a result of an exclusive-OR operation to input bits including the first operation result; and

a selector (SEL) operating according to the mode of operation;

(i) wherein in the code conversion mode, the selector (SEL) outputs the second operation result (B _n) , the input bits to the first logic circuit (LC1) includes a bit (G _n+1) in gray code representation and a bit (B _n+2) in binary code representation of a second number-to-be-added, and the input bits to the second logic circuit (LC2) further includes a bit (G _n) in gray code representation of the second number-to-be-added; and

(ii) wherein in the addition mode, the selector (SEL) outputs a carry bit (C _n) in an addition of a first number-to-be-added (A) and the second number-to-be-added (B) , the input bits to the first logic circuit (LC1) includes a bit (A _n) of the first number-to-be-added and a carry bit (C _n-1) of a digit lower than the carry bit (C _n) , and the input bits to the second logic circuit (LC2) includes a bit (B _n) of the second number-to-be-added.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic diagram illustrating a partial configuration of an image sensor 10.

Figure 2 is an explanation diagram to describe the correlated double sampling (CDS) .

Figure 3A is a schematic diagram illustrating a partial configuration of an image sensor 300.

Figure 3B illustrates an exemplary pulse generation circuit 315.

Figure 3C illustrates a timing diagram of waveforms of signals in the pulse generation circuit 315.

Figure 4 is an explanation diagram to describe gray codes.

Figure 5 illustrates a conversion &addition core circuit 34 included in an arithmetic logic operation circuit (ALU) 33 depicted in Figure 3A.

Figure 6 illustrates a configuration when the conversion &addition core circuit 34 operates in the conversion mode.

Figure 7 illustrates a configuration when the conversion &addition core circuit 34 operates in the addition mode.

Figure 8 illustrates a sampling unit including the conversion &addition core circuit 34 and latch circuits.

Figure 9 illustrates a schematic flow chart to describe operations according to one embodiment.

Figure 10 illustrates a timing chart for the purpose of describing operations.

Figure 11 illustrates exemplary data movement in the conversion mode.

Figure 12 illustrates exemplary data movement in the addition mode.

Figure 13 illustrates one example of the exemplary conversion &addition core circuit 34, which performs 4 bit conversion and 2 bit addition.

Figure 14 illustrates another example of the exemplary conversion &addition core circuit 34, which performs 4 bit conversion and 2 bit addition.

Figure 15 illustrates one example of the sampling unit when the exemplary conversion &addition core circuit 34 performs 4 bit conversion and 2 bit addition.

Figure 16 illustrates another example of the sampling unit when the exemplary conversion &addition core circuit 34 performs 4 bit conversion and 2 bit addition.

Figure 17 illustrates an exemplary operation of the correlated double sampling (CDS) .

Figure 18 illustrates an exemplary operation of the correlated multiple sampling (CMS) .

Figure 19 illustrates an exemplary operation of the correlated multiple sampling (CMS) .

Figure 20 illustrates an exemplary operation of the correlated double sampling (CDS) .

Figure 21 illustrates one example of an electronic apparatus.

Mode for Carrying Out the Invention

Hereinafter, the embodiments will be described with reference to accompanying drawings in the context of following sections. Through the drawings, the same reference number or the reference symbol is assigned to the same element.

1. System overview

2. Gray code

3. Reconfigurable logic circuit

3.1 Conversion &addition core circuit

3.2 Conversion mode (G2B)

3.3 Addition mode (CDS)

4. Operations

5. Variations

5.1 Multiple bit

5.2 CMS

5.3 Sun black correction

6. Electronic apparatus

Sections in the following description are not essential for the embodiments. Descriptions in two or more sections may be combined, and descriptions in one section may be applied to descriptions in another section (unless contradicted) , as appropriate.

1. System overview

Figure 3A is a schematic diagram illustrating a partial configuration of an image sensor 300. For example, the image sensor 300 may be a CMOS image sensor. In the image sensor 300, sensor elements are arranged in an array, each of which converts a certain physical quantity into an electric signal, and the output signals of the sensor elements are used for a sensing. The image sensor 300 may be used for any sensor, e.g., a finger print sensors.

In Figure 3A, a plurality of pixels 311, a row decode circuit 312, a read-out circuit 313, a horizontal scanner 318, a ramp waveform generator (RAMP) 316, and a clock supplier (CLK) 317, a gray code counter 319, and a controller 320 are depicted. Figure 3A illustrates elements which relate to the following description. However, in actuality, other elements may exist. The read-out circuits 313 are provided for every column, each of which includes a comparator 314, a pulse generation circuit 315, a gray code (GC) latch circuit 32, a S-latch circuit 36, and a I/F-latch circuit 37. The ramp waveform generator (RAMP) 316, the clock supplier (CLK) 317, and the gray code counter 319 are shared among a plurality of read-out circuits 313. An arithmetic logic operation circuit (ALU) 33, which performs a code conversion and an addition operation, may be provided for every read-out circuit 313 (for every column) , or may be shared among a plurality of columns. In the example depicted in Figure 3A, the arithmetic logic operation circuit (ALU) 33 is shared between two columns. The arithmetic logic operation circuit (ALU) 33 includes a conversion &addition core circuit 34 and a T-latch circuit 35.

The controller 320 controls operations of the respective components depicted in Figure 3A. For ease of illustration, connection lines between the controller 320 and the other components are not depicted.

Each of the plurality of pixels 311 has the same configuration and the same functions. A pixel 311 located in the n-th row and the m-th column is used as a representative example to describe operations. The pixel 311 depicted in Figure 3A includes a photodiode (PD) which an anode is connected to a low power supply V _SS (for example, V _SS may be GND) ; a transfer transistor Tr1 connected between a cathode of the PD and a floating diffusion layer (FD) ; and a reset transistor Tr2 connected between the floating diffusion layer (FD) and a high power supply V _DD. Although only one PD is depicted in one pixel 311, a plurality of PDs and Tr1s may be connected to the floating diffusion layer (FD) . The pixel 311 further includes an amplification transistor Tr3 forming a source follower in which a gate receiving an input voltage is connected to the floating diffusion layer (FD) ; a selection transistor Tr4 which controls a connection between Tr3 and the output signal line (the data line D _m in Figure 3A) . A current source CS is connected to the output signal line D _m, and supplies a source follower bias current.

The row decode circuit 312 controls selections of the pixels 311 and operations of the pixels 311. Basically, the pixels 311 are selected by driving (activating or deactivating) a selection signal SEL _n and a transfer signal TG _n, x. In an example depicted in Figure 3A, operations of some signals, such as a reset signal RST _n, the transfer signal TG _n, x, and the selection signal SEL _n are controlled by means of the vertical scanner. The level shifter converts the levels of these kinds of signals to appropriate levels for the pixel 311. The selection signal SEL _n and the transfer signal TG _n, x may be referred to as a scan line. Since the scan line is connected to the plurality of pixels 311, the plurality of pixels may be designated at once by designating one scan line.

The read-out circuits 313 may read analog data from the pixels 311 through the plurality of data lines (... D _m, D _m+1, ... ) , convert it to digital data, then send the converted data to the horizontal scanner 318. Thus, the read-out circuit 313 may function as an analog-to-digital converter (ADC) . The comparator 314 depicted in Figure 3A includes a differential amplifier. For example, the pulse generation circuit 315 may be configured as depicted in Figure 3B, and generates a pulse at a moment when a polarity of an output of the comparator 314 is changed, as depicted in Figure 3C. The gray code (GC) latch circuit 32 receives the output pulse as an input, and stores the gray code corresponding to the count value at that time.

The horizontal scanner 318 receives digital data from the read-out circuit 313, and transfers the digital data to a processing block in a later stage (not shown) . The processing block may be an internal image processing processor, an interface circuit, or the like.

The plurality of read-out circuits (ADCs) 313 depicted in Figure 3A may operate in parallel. Each of the read-out circuit 313 operates in a time division multiplexed manner with respect to the k pixels. “k” indicates the number of pixels connected in parallel to one read-out circuit 313. In the example in Figure 3A, following operations are repeated k times: reading the analog signal from one pixel 311, then outputting the digital signal corresponding to the analog signal (i.e., analog-to-digital conversion) . The number of pixels (specifically, the number of rows and the number of columns) may be any suitable positive integer. For example, the number of rows and the number of columns may be hundreds, thousands, or the like.

2. Gray code

As described above, in order to reduce error component effect included in the reference level (the voltage level of the floating diffusion layer (FD) ) and the unknown signal level (the signal level of the photodiode (PD) ) of the pixel 311, the correlated double sampling (CDS) or the correlated multiple sampling (CMS) is performed. When representing the reference level and the unknown signal level as their digital values, not only the binary code, but also the gray code may additionally be used. In such a case, initially, a measurement result of the reference level and/or the unknown signal level is represented as a gray code, and then it is converted to a binary code for subsequent digital signal process. By using the gray code as well, instead of only the binary code, it is possible to expect that some technical effect, e.g., to improve precision, to reduce power consumption, or the like, will be provided.

Figure 4 is an explanation diagram to describe gray codes. Generally, 5-bit gray codes are depicted in a left side, corresponding decimal code are depicted in a right side, and 5-bit binary codes are depicted therebetween. The gray code has a property that only one bit differs when incrementing or decrementing by one. For example, when a certain quantity changes from 7 to 8 in the decimal code, a corresponding binary code changes from

00111 to

01000.

In this case, until the change from (7) ₁₀ to (8) ₁₀ is completed, 4 bits need to be changed. Thus, if a yet-to-be-completed value is used in error, some large error may occur. In contrast, the gray code changes from

00100 to

01100.

Until the change from (7) ₁₀ to (8) ₁₀ is completed, only 1 bit changes. Thus, even if the yet-to-be-completed value is used in error, large error is unlikely to occur. This is because the number of error bits is at most 1.

In addition, a most significant bit (MSB) of the gray code and the binary code may correspond to a sign of positive/negative. Specifically, considering a situation that a certain negative number (-14) ₁₀ is obtained based on a certain positive number (+14) ₁₀. Such a negative number equals to the 2’s complement of the certain positive number. This 2’s complement may easily be obtained as follows: The MSB (i.e., sign) of the gray code of the positive number is changed from 0 to 1 (e.g., (01001) _G -> (11001) _G) , and one is added to the binary code corresponding to the sign-changed gray code ( (00001) _B +(10001) _B = (10010) _B) . It is noted that the binary code (10001) _B corresponding to the sign-changed gray code equals the 1’s complement of the binary code corresponding to the certain positive number (+14) ₁₀. It is also noted that the 2’s complement can be obtained by adding one to the 1’s complement. (If the 1’s complement of the binary code is directly calculated, all bits of the binary code have to be reversed. ) Thus, when performing an addition operation, a negative addition, i.e., subtraction can be performed by setting the MSB of the number-to-be-added to the positive value (MSB = 1) , and setting a carry bit to be one in the LSB bit addition.

The following formula is valid between the gray code (G _N-1 G _N-2 ... G _n ... G ₀) and the binary code (B _N-1 B _N-2 ... B _n ... B ₀) :

G _n xor B _n+1 = B _n

Thus, it is possible to convert the gray code to the binary code by means of the following operations:

B _N-1 = G _N-1

B _N-2 = G _N-2 xor B _N-1 = G _N-2 xor G _N-1

...

B _n= G _n xor B _n+1 = G _n xor G _n+1 xor... G _N-1

...

B ₀= G ₀ xor B ₁ = G ₀ xor G ₁ xor... G _N-1

B _N-1 is the most significant bit (MSB) of the binary code in this example, and B _N-1 equals the most significant bit (MSB) of the gray code, i.e., G _N-1. Thus, based on B _N-1 (MSB) , it is possible to sequentially derive the binary bits until B ₀ (LSB) .

The value currently converted to the binary code is added to the certain value that was converted before. In this embodiment, the value that was converted before is, typically, the known level (the reference level) while the value that is currently converted to the binary code is the unknown signal level. The addition operation, such as (first number-to-be-added) + (second number-to-be-added) = (addition result) , has to be sequentially calculated from the LSB. Thus, when calculating (A _N-1 A _N-2 ... A _n ... A ₀) + (B _N-1 B _N-2 ... B _n ... B ₀) = (X _N-1 X _N-2 ... X _n ... X ₀) , it needs to start from X ₀. Thus, the addition is performed in a reverse order to the code conversion. In the conventional approach, typically, following calculations are performed step-by-step.

G2B_Step 0: B _N-1 = G _N-1

G2B_Step 1: B _N-2 = G _N-2 xor B _N-1 = G _N-2 xor G _N-1

...

G2B_Step N-1-n: B _n= G _n xor B _n+1 = G _n xor G _n+1 xor... G _N-1

...

G2B_Step N-1: B ₀= G ₀ xor B ₁ = G ₀ xor G ₁ xor... G _N-1; X ₀, C = A ₀ + B ₀

Add_Step 0: B ₁= G ₀ xor B ₀ ; X ₁, C = A ₁ + B ₁

...

Add_Step N-1-n: B _n= G _n-1 xor B _n-1 ; X _n, C = A _n + B _n

...

Add_Step N-1: B _N-1= G _N-2 xor B _N-2 ; X _N-1, C = A _N-1 + B _N-1

When calculating the underlined parts, the following formula is used: B _n= G _n-1 xor B _n-1 “, C” in the addition operation represents a carry bit to carry a digit. Generally, (G2B_Step 0) to (G2B_step N-1) correspond to the process to convert the gray code (G _N- ₁G _N-2... G _n... G ₀) to the binary code (B _N-1B _N-2... B _n... B ₀) . The steps from the second half of (G2B_Step N-1) to (Add_Step N-1) correspond to the operations including newly calculating the bit (B _n) of the second number-to-be-added required for the addition, adding the bit (A _n) of the first number-to-be-added and the bit (B _n) of the second number-to-be-added, thereby obtaining the operation result (X _n) . In the conventional approach, the process from (G2B_Step 0) to (G2B_Step N-1) and the process from (Add_Step 0) to (Add_Step N-1) are independently performed.

However, with regard to the underlined parts in the processes from (Add_Step 0) to (Add_Step N-1) , similar operations were performed in the processes from (G2B_Step 0) to (G2B_Step N-1) . The present embodiment improves the operation efficiency at least based on this knowledge.

3. Reconfigurable logic circuit

3.1 Conversion &addition core circuit

Figure 5 illustrates a conversion &addition core circuit (CDS/G2B) 34 included in an arithmetic logic operation circuit (ALU) 33 depicted in Figure 3A.

The conversion &addition core circuit (CDS/G2B) 34 includes a first half-adder circuit (LC1) including a first exclusive-OR circuit (XOR1) performing an exclusive-OR operation to input bits; and a first logical-AND circuit (AND1) performing a logical-AND operation to the input bits.

The conversion &addition core circuit (CDS/G2B) 34 includes a second half-adder circuit (LC2) including a second exclusive-OR circuit (XOR2) performing an exclusive-OR operation to input bits including another input bit and the output of the first exclusive-OR circuit (XOR1) ; and a second logical-AND circuit (AND2) performing a logical-AND operation to the input bits of the second exclusive-OR circuit (XOR2) .

The conversion &addition core circuit 34 includes a logical-OR circuit (OR) performing a logical-OR operation to the output of the first logical-AND circuit (AND1) and the output of the second logical-AND circuit (AND2) ; and a selector (SEL) selecting the output of the second exclusive-OR operation circuit (XOR2) or the output of the logical-OR circuit (OR) , according to the mode of operation. The mode of operations includes a code conversion mode (G2B) and an addition mode (CDS) . The conversion &addition core circuit 34 can switch circuit configurations according to the mode of operations.

3.2 Conversion mode (G2B)

The first exclusive-OR circuit (XOR1) in the first half-adder circuit (LC1) outputs a first operation result (B _n+1) , the first operation result (B _n+1) being a result of an exclusive-OR operation to the input bits including a bit (G _n+1) in gray code representation and a bit (B _n+2) in binary code representation of a second number-to-be-added.

Next, the second exclusive-OR circuit (XOR2) in the second half-adder circuit (LC2) outputs a second operation result (B _n) , the second operation result (B _n) being a result of an exclusive-OR operation to the input bits including the first operation result (B _n+1) and a bit (G _n) in gray code representation of the second number-to-be-added.

The selector (SEL) selects and outputs the output of the second exclusive-OR circuit (XOR2) . In contrast to the conventional approach, such derived bits in the binary code representation are stored in the T-latch 35 in this embodiment.

As an example, a situation in which that the gray code corresponding to the second number-to-be-added is (G ₅G ₄G ₃G ₂G ₁G ₀) , and this gray code is converted to the binary code, is considered. The gray code of the second number-to-be-added is stored in the GC-latch 32. The MSB of the gray code is G ₅ (MSB = G ₅) while the LSB is G ₀ (LSB = G ₀) .

In the initial operation step of this embodiment, the first exclusive-OR circuit (XOR1) outputs a first operation result (B ₅) , the first operation result (B ₅) being a result of an exclusive-OR operation to the input bits (G ₅ and 0) . With regard to this “0” , alternatively, a reset latch output for a carry bit may be used. Thus, the MSB of the gray code and the MSB of the binary code are equal, B ₅ = G ₅. In addition, in order to obtain a negative number, G ₅ may be assigned to a sign, and it may be possible to perform an exclusive-OR operation to G ₅ and 1 (With regard to this “1” , a set latch output for a carry bit may be used. ) . In this case, the fixed input bit may be stored as the code bit.

The second exclusive-OR circuit (XOR2) outputs a second operation result (B ₄) being a result of an exclusive-OR operation to G ₄ and the first operation result (B ₅) . The selector (SEL) selects and outputs the output (B ₄) of the second exclusive-OR circuit (XOR2) .

In this case, the output (B ₄) is stored, e.g., in a latch circuit, as a carry bit. The input bits (G5, G4) of the first and second exclusive-OR circuits (XOR1, XOR2) are updated to next input bits (G ₃, G ₂) . The first exclusive-OR circuit (XOR1) outputs a first operation result (B ₃) , the first operation result (B ₃) being a result of an exclusive-OR operation to the input bits (G ₃ and B ₄) . B ₄ is obtained from the selector (SEL) .

The second exclusive-OR circuit (XOR2) outputs a second operation result (B ₂) being a result of an exclusive-OR operation to G ₂ and the first operation result (B ₃) . The selector (SEL) selects and outputs the output (B ₂) of the second exclusive-OR circuit (XOR2) .

Next, the first exclusive-OR circuit (XOR1) outputs a first operation result (B ₁) , the first operation result (B ₁) being a result of an exclusive-OR operation to the input bits (G ₁ and B ₂) . B ₂ is obtained from the selector (SEL) . The second exclusive-OR circuit (XOR2) outputs a second operation result (B ₀) being a result of an exclusive-OR operation to G ₀ and the first operation result (B ₁) .

In this way, the binary code (B ₅B ₄B ₃B ₂B ₁B ₀) is obtained. This binary code (B ₅B ₄B ₃B ₂B ₁B ₀) corresponds to the gray code (G ₅G ₄G ₃G ₂G ₁G ₀) of the second number-to-be-added. As described above, the negative code of this binary code may be easily obtained by changing the sign of the gray code and adding one to the binary code corresponding to the sine-changed gray code. In contrast to the conventional approach, such derived binary bits (B ₅B ₄B ₃B ₂B ₁B ₀) are stored in the T-latch 35 in this embodiment.

3.3 Addition mode (CDS)

Figure 7 illustrates a configuration when the conversion &addition core circuit 34 operates in the addition mode. Before the operation of the addition mode starts, the bits (A ₁ , ..., A _n) of the binary code representation of the first number-to-be-added are stored in the S-latch circuit 36. The bits (B ₁ , ..., B _n) of the binary code representation of the second number-to-be-added are stored in the T-latch circuit 35.

In the addition mode, the first exclusive-OR circuit (XOR1) of the first adder circuit (LC1) outputs an operation result, the operation result being a result of an exclusive-OR operation to the input bits including a bit (A _n) of the first number-to-be-added and a carry bit (C _n-1) of a digit lower than the carry bit (C _n) . The first logical-AND circuit (AND1) of the first half-adder circuit (LC1) outputs an operation result, the operation result being a result of a logical-AND operation to the input bits including the bit (A _n) of the first number-to-be-added and the carry bit (C _n-1) of the digit lower than the carry bit.

The exclusive-OR circuit (XOR2) of the second half-adder circuit (LC2) outputs an operation result, the operation result being a result (X _n) of an exclusive-OR operation to the input bits including another input bit (B _n) and the output of the first exclusive-OR circuit (XOR1) . The second logical-AND circuit (AND2) of the second half-adder circuit (LC2) outputs an operation result, the operation result being a result of a logical-AND operation to the input bits including another input bit (B _n) and the output of the first exclusive-OR circuit (XOR1) .

The logical-OR circuit (OR) performs a logical-OR operation to the inputs including the output of the first logical-AND circuit (AND1) and the output of the second logical-AND circuit (AND2) . The selector (SEL) selects and outputs the output of the logical-OR circuit (OR) as the carry bit (C _n) .

As an example, considering 6-bit addition as follows:

(A ₅ A ₄ A ₃ A ₂ A ₁ A ₀) + (B ₅ B ₄ B ₃ B ₂ B ₁ B ₀) = (X ₅ X ₄ X ₃ X ₂ X ₁ X ₀)

Before the operation of the addition mode starts, the first number-to-be-added (A ₀ , ..., A ₅) is stored in the S-latch circuit 36 while the second number-to-be-added (B ₀ , ..., B ₅) is stored in the T-latch circuit 35.

The first exclusive-OR circuit (XOR1) outputs an operation result, the operation result being a result of an exclusive-OR operation to the input bits including the bit (A ₀) of the first number-to-be-added and the carry bit (C _-1=0) of the lower digit. The first logical-AND circuit (AND1) outputs an operation result, the operation result being a result (0) of a logical-AND operation to the input bits including A ₀ and C _-1. In addition, if the second number-to-be-added (B ₅B ₄B ₃B ₂B ₁B ₀) is obtained by the code conversion process including the sign reverse process described above, the lower digit carry bit may be set to 1 (C _-1=1) , in order to deal with the sign reverse process.

The second exclusive-OR circuit (XOR2) outputs an operation result, the operation result being a result (X ₀) of an exclusive-OR operation to the input bits including another input bit (B ₀) and the output of the first exclusive-OR circuit (XOR1) . The second logical-AND circuit (AND2) outputs an operation result, the operation result being a result of a logical-AND operation to the input bits including B ₀ and the output of the first exclusive-OR circuit (XOR1) .

The logical-OR circuit (OR) performs a logical-OR operation to the inputs including the output of the first logical-AND circuit (AND1) and the output of the second logical-AND circuit (AND2) . The selector (SEL) selects and outputs the output of the logical-OR circuit (OR) as the carry bit (C ₀) . In this way, the addition result (X ₀) of A ₀ and B ₀, and the carry bit C ₀ are obtained. A ₀ in the first number-to-be-added (A ₅A ₄A ₃A ₂A ₁A ₀) stored in the S-latch circuit 36 is replaced by X ₀.

With regard to the first bit to the fifth bit, operations similar to that of the zero-th bit are repeated. After the operation for the fifth bit ends, the first number-to-be-added (A ₅A ₄A ₃A ₂A ₁A ₀) stored in the S-latch circuit 36 have been replaced by the addition result (X ₅X ₄X ₃X ₂X ₁X ₀) . In addition, by using the 2’s complement, the positive number and the negative number can be used. The MSB corresponds to the sign code.

4. Operations

Next, more specific operations are described with regard to the read-out circuit 313 in Figure 3A. In the read-out circuit 313 used for this explanation, the components following the pulse generation circuit 315 are configured as depicted in Figure 8. It is assumed that the gray code and the binary code to be operated are 6 bit codes. The conversion &addition core circuit 34 converts two bits at once in the conversion mode, and performs 1 bit addition in the addition mode. Thus, the conversion &addition core circuit 34 performs the code conversion and the full addition in a time division multiplexed manner.

Figure 9 illustrates a schematic flow chart to describe operations according to one embodiment. Figure 10 illustrates a timing chart for the purpose of describing operations. In Figure 10, a time line is indicated in the bottommost line. For ease of illustration, the timing labels after 10 are indicated for every 5 units. As shown in Figure 9 and the top row in Figure 10, the operation periods according to the embodiment include, generally, a level measurement period (ADC) (step 902) , a code conversion period (G2B) (step 904) , and an addition period (CDS) (step 906) .

The operations in the level measurement period (ADC) (step 902) are described. This level measurement period corresponds to the operations to measure the unknown level. The operations to measure the known level (reference level) were completed. The waveform indicated by RSTCNTB in Figure 10 represents the state of the reset transistor for the photodiode (PD) . During the period in which the RSTCNTB is OFF, the floating diffusion layer (FD) is in the floating state. In this period, the electric charge in the photodiode (PD) is transferred to the floating diffusion layer (FD) , and the unknown signal level is measured.

The waveform indicated by CMPIN in Figure 10 represents the output of the pulse generation circuit 315 (Figure 3A) . The output pulse is occurred at the timing when the gradually decreasing ramp waveform matches the level to be measured. This timing is represented as “GC” in Figure 10. Respective bits of the gray code (G ₅G ₄G ₃G ₂G ₁G ₀) corresponding to the timing “GC” are stored in 6 latches (GCLAT ₀ -GCLAT ₅) of the gray code latch (GCLAT) 32 (Figure 8) . This is indicated in Figure 10 in that the data stored in GCLAT changes from “xxxxxx” to “G<5: 0>” at the timing “GC” .

On the other hand, the first number-to-be-added (A ₅A ₄A ₃A ₂A ₁A ₀) has already been stored in the S-latch 36. This is indicated in Figure 10 in that the data stored in SLAT is maintained as “A<5: 0>” until the timing “11” . As an example, this first number-to-be-added is the binary code indicating the reference level for measuring the photodiode (PD) .

The waveform indicated by G2B/CDS in Figure 10 represents the mode of operations of the conversion &addition core circuit 34. In Figure 10, the low level corresponds to the conversion mode, the high level corresponds to the addition mode, this waveform changes from the low level to the high level. However, such a waveform is not limited as long as both modes can be distinguished.

The waveform indicated by OCLK in Figure 10 represents a clock to control the operations to transfer the output of the conversion &addition core circuit 34 to the S-latch circuit 36.

The waveform indicated by CCLK in Figure 10 represents a clock to control the operations of the conversion &addition core circuit 34.

The waveform indicated by RSTCB in Figure 10 represents a reset signal to reset the carry bit. The carry bit is indicated as “CARRY” in Figure 10 (bottommost item) . The carry bit is reset immediately before the start of the code conversion mode, and immediately before the start of the addition mode. Thus, the carry bit is reset to be “0” at the timings indicated by “1” and “8” .

Next, the operations in the code conversion period (G2B) (step 904) are described. During the period from the timing “1” to the timing “8” , the conversion &addition core circuit 34 operates in the conversion mode (G2B) .

The waveform indicated by S54 in Figure 10 represents a selection signal to connect or disconnect between the outputs of the gray code latch circuit 32 (GCLAT ₅, GCLAT ₄) and the inputs of the conversion &addition core circuit 34. The waveform indicated by CK54 represents a clock to control the operations of the T-latch circuit (TLAT ₅, TLAT ₄) .

During the period from the timing “1” to “3” in which S54 is in the high level, the data (G ₅, G ₄) stored in the GCLAT ₅ and GCLAT ₄ is used as input bits to the conversion &addition core circuit 34. Since the code conversion is sequentially performed from the most significant bit (MSB) , G ₅ is selected first. In the code conversion mode, the conversion &addition core circuit 34 converts the input gray code representation bits (G ₅, G ₄) to the corresponding binary code representation bits (B ₅, B ₄) . This operation results (B ₅, B ₄) are stored in the T-latch circuit (TLAT ₅, TLAT ₄) (Figure 11) . This is indicated in Figure 10 in that the data stored in TLAT changes from “xxxxxx” to “B<5: 4>, xxxx” at the timing “2” . Since B ₄ is used for the subsequent operation, it is stored as a carry bit. This is indicated in Figure 10 in that the carry bit (CARRY) changes from “0” to “B<4>” .

Similar operations are performed for the subsequent lower gray code bits (G ₃G ₂G ₁G ₀) . The waveform indicated by S32 in Figure 10 represents a selection signal to connect or disconnect between the outputs of the gray code latch circuit 32 (GCLAT ₃, GCLAT ₂) and the inputs of the conversion &addition core circuit 34. The waveform indicated by CK32 represents a clock to control the operations of the T-latch circuit (TLAT ₃, TLAT ₂) .

During the period from the timing “3” to “5” in which S32 is in the high level, the data (G ₃, G ₂) stored in the GCLAT ₃ and GCLAT ₂ is used as input bits to the conversion &addition core circuit 34. The conversion &addition core circuit 34 converts the input gray code representation bits (G ₃, G ₂) to the corresponding binary code representation bits (B ₃, B ₂) . This operation results (B ₃, B ₂) are stored in the T-latch circuit (TLAT ₃, TLAT ₂) . This is indicated in Figure 10 in that the data stored in TLAT changes from “B<5: 4>, xxxx” to “B<5: 2>, xx” at the timing “4” . Since B ₂ is used for the subsequent operation, it is stored as a carry bit. This is indicated in Figure 10 in that the carry bit (CARRY) changes from “B<4>” to “B<2>” .

The waveform indicated by S10 in Figure 10 represents a selection signal to connect or disconnect between the outputs of the gray code latch circuit 32 (GCLAT ₁, GCLAT ₀) and the inputs of the conversion &addition core circuit 34. The waveform indicated by CK10 represents a clock to control the operations of the T-latch circuit (TLAT ₁, TLAT ₀) .

During the period from the timing “5” to “7” in which S10 is in the high level, the data (G ₁, G ₀) stored in the GCLAT ₁ and GCLAT ₀ is used as input bits to the conversion &addition core circuit 34. The conversion &addition core circuit 34 converts the input gray code representation bits (G ₁, G ₀) to the corresponding binary code representation bits (B ₁, B ₀) . This operation results (B ₁, B ₀) are stored in the T-latch circuit (TLAT ₁, TLAT ₀) . This is indicated in Figure 10 in that the data stored in TLAT changes from “B<5: 2>, xx” to “B<5: 0>” at the timing “6” . B ₀ is stored as a carry bit. This is indicated in Figure 10 in that the carry bit (CARRY) changes from “B<2>” to “B<0>” .

Next, the operations in the addition period (CDS) (step 906) are described. During the period starting from the timing “8” , the conversion &addition core circuit 34 operates in the addition mode (CDS) . In this example, 6 bit addition is performed as follows:

(A ₅A ₄A ₃A ₂A ₁A ₀) + (B ₅B ₄B ₃B ₂B ₁B ₀) = (X ₅X ₄X ₃X ₂X ₁X ₀)

Before the operation of the addition mode starts, the first number-to-be-added (A ₀ , ..., A ₅) is stored in the S-latch circuit 36 (SLAT ₀, ..., SLAT ₅) . The second number-to-be-added (B ₁ , ..., B ₅) is stored in the T-latch circuit 35 (TLAT ₀ , ..., TLAT ₅) .

The waveform indicated by S0 in Figure 10 represents a selection signal to connect or disconnect between the outputs of the T-latch circuit (TLAT ₀) and the S-latch circuit (SLAT ₀) , and the inputs of the conversion &addition core circuit 34. The waveform indicated by CK0 represents a clock to control the operations of the S-latch circuit (SLAT ₀) .

During the period from the timing “8” to “11” in which S0 is in the high level, the data (B ₀, A ₀) stored in the TLAT ₀ and SLAT ₀ is used as input bits to the conversion &addition core circuit 34. Since the addition operation is sequentially performed from the least significant bit (LSB) , the LSBs (A ₀, B ₀) are selected first. In the addition mode, the conversion &addition core circuit 34 performs the addition operation based on the input bits (B ₀, A ₀) and outputs the addition result (X ₀) . Specifically, during the period from the timing “11” to “12” in which the OCLK is in the high level, the operation result (X ₀) is stored in the S-latch circuit (SLAT ₀) (Figure 12) . This is indicated in Figure 10 in that the data stored in SLAT changes from “A<5: 0>” to “A<5: 1>, X<0>” at the timing “11” . In addition, a carry bit is stored accordingly. This is indicated in Figure 10 in that the carry bit (CARRY) indicates “Cout<0>” in the period from the timing “10” to “13” .

Similar operations are performed for the subsequent upper bits. The waveform indicated by S1 in Figure 10 represents a selection signal to connect or disconnect between the outputs of the T-latch circuit (TLAT ₁) and the S-latch circuit (SLAT ₁) , and the inputs of the conversion &addition core circuit 34. The waveform indicated by CK1 represents a clock to control the operations of the S-latch circuit (SLAT ₁) .

During the period from the timing “11” to “14” in which S1 is in the high level, the data (B ₁, A ₁) stored in the TLAT ₁ and SLAT ₁ is used as input bits to the conversion &addition core circuit 34. The conversion &addition core circuit 34 performs the addition operation based on the input bits (B ₁, A ₁) and outputs the addition result (X ₁) . Specifically, during the period from the timing “14” to “15” in which the OCLK is in the high level, the operation result (X ₁) is stored in the S-latch circuit (SLAT ₁) . This is indicated in Figure 10 in that the data stored in SLAT changes from “A<5: 1>, X<0>” to “A<5: 2>, X<1: 0>” at the timing “14” . In addition, a carry bit is stored accordingly. This is indicated in Figure 10 in that the carry bit (CARRY) indicates “Cout<1>” in the period from the timing “13” to “16” .

The waveforms indicated by S2 -S5 in Figure 10 represent selection signals to connect or disconnect between the outputs of the T-latch circuit (TLAT _2-5) and the S-latch circuit (SLAT _2-5) , and the inputs of the conversion &addition core circuit 34, respectively. The waveforms indicated by CK2 –CK5 represent a clock to control the operations of the S-latch circuit (SLAT _2-5) , respectively.

During the period in which S2 –S5 are in the high level, the data (B _2-5, A _2-5) stored in the TLAT _2-5 and SLAT _2-5 is used as input bits to the conversion &addition core circuit 34, respectively. The conversion &addition core circuit 34 performs the addition operation based on the input bits (B _2-5, A _2-5) and outputs the addition result (X _2-5) . Specifically, during the period in which the OCLK is in the high level, the operation results (X _2-5) are stored in the S-latch circuit (SLAT _2-5) . This is indicated in Figure 10 in that the data stored in SLAT changes to “A<5: 3>, X<2: 0>” , “A<5: 4>, X<3: 0>” , “A<5>, X<4: 0>” , and “X<5: 0>” . In addition, a carry bit is stored accordingly. This is indicated in Figure 10 in that the carry bit (CARRY) changes to “Cout<2>” , “Cout<3>” , “Cout<4>” , and “Cout<5>” .

The addition result X<5: 0> stored in the S-latch circuit (SLAT ₀ -SLAT ₅) depicted in Figure 8 will be stored in the I/F latch circuit 37 (I/FLAT ₀ -I/FLAT ₅) according to the horizontal synchronization clock HCLK, then transferred to the horizontal scanner 318 (Figure 3A) .

According to this embodiment, the conversion &addition core circuit 34, the T-latch circuit 35, and the S-latch circuit 36 cooperate with each other, it is possible to efficiently perform the code conversion and the full addition in the correlated double sampling (CDS) . Since the conversion &addition core circuit 34 can be shared for both the code conversion and the full addition, it does not need to separately provide a code conversion circuit and a full addition circuit. Thus, it is possible to save operational resources. Particularly, it is possible to reduce power consumption and space in the operation circuit.

5. Variations

5.1 Multiple bit

In the examples in Figure 5 and Figure 8, the conversion &addition core circuit 34 converts 2 bits at once in the conversion mode, and performs 1 bit addition in the addition mode. If the number to be operated includes 6 bits, this conversion &addition core circuit 34 is used in a time division multiplexed manner. However, this is only for the example for the purpose of explanation. It is possible to operate more bits at once, and/or another repeat count may also be used.

Figure 13 illustrates one example of the exemplary conversion &addition core circuit 34, which performs 4 bit conversion and 2 bit addition at a time. In the conversion mode, the 4 bit gray code (G ₃G ₂G ₁G ₀) is converted to the 4 bit binary code (B ₃B ₂B ₁B ₀) . The selector selects “0” in case of the conversion mode.

In the addition mode, the two bits (A ₁A ₀) of the first number-to-be-added and the two bits (B ₁B ₀) of the second number-to-be-added are added, and the operation result (X ₁X ₀) is outputted. The selector selects “1” in case of the addition mode. The latch circuit LATC is for storing a carry bit. The operations of the conversion and the addition are similar to that of previous sections. Repetitive descriptions will be omitted.

Figure 14 illustrates another example of the exemplary conversion &addition core circuit 34, which performs 4 bit conversion and 2 bit addition at a time. The conversion &addition core circuit 34 in Figure 14 may be configured and operated similar to that depicted in Figure 13. Both the conversion &addition core circuits 34 depicted in Figure 13 and Figure 14 include the latch circuit LAT _C while the conversion &addition core circuit 34 depicted in Figure 14 further includes the latch circuit LAT _B. The latch circuit LATB can store the most-recently obtained operation result. After the 4 bit gray code (G ₃G ₂G ₁G ₀) is converted to the 4 bit binary code (B ₃B ₂B ₁B ₀) , the LSB (B ₀) may be stored in the latch circuit LAT _B. The operations of the conversion and the addition are similar to that of previous sections. Repetitive descriptions will be omitted.

Figure 15 illustrates one example of the sampling unit when the conversion &addition core circuit 34 performs 4 bit conversion and 2 bit addition. In the example in Figure 15, the gray code and the binary code to be operated include 12 bits. Thus, the conversion &addition core circuit 34 performs the code conversion and the full addition in a time division multiplexed manner. Specifically, the code conversion for all 12 bits is performed by repeating the 4 bit code conversion 3-times, and the full addition for all 12 bits is performed by repeating the 2 bit addition 6-times, as follows:

( code conversion: first time)

T-latch 35: _ __ __ __ _B ₈ B ₉ B ₁₀ B ₁₁

( code conversion: second time)

T-latch 35: _ __ _B ₄ B ₅ B ₆ B ₇ B ₈ B ₉ B ₁₀ B ₁₁

( code conversion: third time)

T-latch 35: B ₀ B ₁ B ₂ B ₃ B ₄ B ₅ B ₆ B ₇ B ₈ B ₉ B ₁₀ B ₁₁

( addition: first time)

S-latch 36: X ₀ X ₁ A ₂ A ₃ A ₄ A ₅ A ₆ A ₇ A ₈ A ₉ A ₁₀ A ₁₁

( addition: second time)

S-latch 36: X ₀ X ₁ X ₂ X ₃ A ₄ A ₅ A ₆ A ₇ A ₈ A ₉ A ₁₀ A ₁₁

( addition: third time)

S-latch 36: X ₀ X ₁ X ₂ X ₃ X ₄ X ₅ A ₆ A ₇ A ₈ A ₉ A ₁₀ A ₁₁

( addition: fourth time)

S-latch 36: X ₀ X ₁ X ₂ X ₃ X ₄ X ₅ X ₆ X ₇ A ₈ A ₉ A ₁₀ A ₁₁

( addition: fifth time)

S-latch 36: X ₀ X ₁ X ₂ X ₃ X ₄ X ₅ X ₆ X ₇ X ₈ X ₉ A ₁₀ A ₁₁

( addition: sixth time)

S-latch 36: X ₀ X ₁ X ₂ X ₃ X ₄ X ₅ X ₆ X ₇ X ₈ X ₉ X ₁₀ X ₁₁

Figure 16 illustrates another example of the sampling unit when the exemplary conversion &addition core circuit 34 performs 4 bit conversion and 2 bit addition. In the example in Figure 16, the gray code and the binary code to be operated also include 12 bits. Figure 16 differs from Figure 15 in that the T-latch circuit 35 includes only 4 elements in Figure 16 while the T-latch circuit includes 12 elements in Figure 15. Thus, initially, the binary code bit required for the addition is obtained, they are used for the addition, after that, the binary code bit required to the next addition is obtained, they are used for the next addition. Specifically, the 4 bit code conversion is repeated 7-times in total and the 2 bit full addition is repeated 6-times in total.

( code conversion: first time)

Carry latch for G2B : 0 xor G ₀ xor G ₁ xor G ₂

S-latch 36: A ₀ A ₁ A ₂ A ₃ A ₄ A ₅ A ₆ A ₇ A ₈ A ₉ A ₁₀ A ₁₁

( code conversion: second time)

Carry latch for G2B : (0 xor G ₀ xor G ₁ xor G ₂) xor G ₃ xor G ₄ xor G ₅ xor G ₆

( code conversion: third time)

Carry latch for G2B : ( (0 xor G ₀ xor G ₁ xor G ₂) xor G ₃ xor G ₄ xor G ₅ xor G ₆) xor G ₇ xor G ₈ xor G ₉ xor G ₁₀

( code conversion: fourth time)

Carry latch for G2B : ( ( (0 xor G ₀ xor G ₁ xor G ₂) xor G ₃ xor G ₄ xor G ₅ xor G ₆) xor G ₇ xor G ₈ xor G ₉ xor G ₁₀) xor xor G ₁₁ xor 0 xor 0 xor 0 = B ₀

( code conversion: fifth time)

Carry latch for G2B: B ₃

Carry latch for CDS: 0

T-latch 35: B ₀ B ₁ B ₂ B ₃

( addition: first time)

Carry latch for GDS: C ₁

T-latch 35: B ₀ B ₁ B ₂ B ₃

( addition: second time)

Carry latch for CDS: C ₃

T-latch 35: B ₀ B ₁ B ₂ B ₃

( code conversion: sixth time)

Carry latch for G2B: B ₇

T-latch 35: B ₄ B ₅ B ₆ B ₇

( addition: third time)

Carry latch for CDS: C ₅

T-latch 35: B ₄ B ₅ B ₆ B ₇

( addition: fourth time)

Carry latch for CDS: C ₇

T-latch 35: B ₄ B ₅ B ₆ B ₇

( code conversion: seventh time)

Carry latch for G2B: B ₁₁

T-latch 35: B ₈ B ₉ B ₁₀ B ₁₁

( addition: fifth time)

Carry latch for CDS: C ₉

T-latch 35: B ₈ B ₉ B ₁₀ B ₁₁

( addition: sixth time)

Carry latch for CDS: C ₁₁

T-latch 35: B ₈ B ₉ B ₁₀ B ₁₁

It is noted that B ₀ = G ₁₁ xor ... xor G ₁ xor G ₀, and Z xor 0 = Z (for any bit Z) . C _i is a carry bit occurred when additing A _i and B _i (for i = 0, ..., 11) .

5.2. CMS

As depicted with reference to Figure 2, it is possible to perform the correlated double sampling (CDS) in order to eliminate error effect such as feedthrough due to the switching of the reset transistor Tr2, kTC noise of the diffusion capacitance, or the like.

Figure 17 illustrates an exemplary operation of the correlated double sampling (CDS) . Initially, in the reference level sampling period, a timing, at which the ramp waveform signal (RAMP) decreasing in a constant ratio equals the voltage level of the floating diffusion layer (FD) , is determined. The voltage level corresponding to this timing is determined as the reference signal. In the example depicted in Figure 17, the reference level sampling is performed by providing a pulse (CMP) from the comparator at the point “S ₁” . The gray code (GC) of the magnitude corresponding to this point “S ₁” is stored in the gray code latch circuit. Thus, the data stored in the GC latch changes from the undetermined state “X” to a certain value “-r1” . The most significant bit of the reference level may be set to 1, which means a negative number (Figure 4) .

Next, in the signal level sampling period, the analog voltage signal of the photodiode (PD) is provided to the comparator, and the signal level is measured. A timing, at which the ramp waveform signal (RAMP) decreasing in a constant ratio equals the signal voltage level, is determined. The voltage level corresponding to this timing is determined as the signal level. In the example depicted in Figure 17, the signal level sampling is performed by providing a pulse (CMP) from the comparator at the point “S ₂” . The gray code (GC) of the magnitude corresponding to this point “S ₂” is stored in the gray code latch circuit. Thus, the data stored in the GC latch changes from the previous value “-r” to the current value “s” . The most significant bit of the reference level may be set to 0, which means a positive number (Figure 4) .

The difference (-r+s) of the signal level to the reference level may be obtained by setting the reference level to the negative number, setting the signal level (subsequently measured) to the positive number, and adding them. Specifically, the obtained value is represented by (-r+s) . This value is stored in the S-latch circuit 36. This is indicated in Figure 17 in that the data indicated in “Calc. Latch” rises from the level “-r” to the level “-r+s” .

As depicted in Figure 17, the correlated double sampling (CDS) may be performed by sampling the reference level once, and sampling the unknown signal level once. The correlated multiple sampling (CMS) may be performed by sampling the voltage level two or more times. It is possible to reduce the noise using the correlated multiple sampling (CMS) , but the analog-to-digital conversion rate may decrease. It should be noted that the noise reduction effect by the correlated multiple sampling (CMS) is particularly effective on the small signals. Thus, it is possible to counter with the ADC rate decrease by applying the CMS only to the small signals.

Figure 18 illustrates an exemplary operation of the partial correlated multiple sampling (CMS) . In the example depicted in Figure 18, the reference level is sampled 4-times at the points S ₁, S ₂, S ₃, S ₄, the resultant values -r1, -r2, -r3, -r4 are obtained, and they are added and stored. Thus, immediately before the unknown signal is measured, the data indicated in “Calc. Latch” equals the level “-r1-r2-r3-r4=- (r1+r2+r3+r4) ” . The unknown signal level is sampled 4-times at the points S ₅, S ₆, S ₇, S ₈, the resultant values +s1, +s2, +s3, +s4 are obtained, and they are added and stored. Thus, immediately after the unknown signal is completed, the data indicated in “Calc. Latch” equals the level “-r1-r2-r3-r4+s1+s2+s3+s4” . It is possible to improve precision in the level measurement by repetitively sampling the voltage level.

In the example depicted in Figure 18, it is possible to evenly sample the reference level and the un-know signal level (with same sampling number of times) . However, the situation depicted in Figure 19 may occur. In this case, an amount of electric charge stored in the photodiode (PD) is very high, and there is a large difference between the reference level and the unknown signal level (the situation is very bright) . In the example depicted in Figure 19, only one of four samplings has succeeded for the unknown signal level (only S ₈) . In this case, one un-know signal level (s4) may be added to the reference level (including 4 sampling values) to obtain “-r1-r2-r3-r4+s4” . However, this value is not an appropriate measurement for the difference between the reference level and the unknown signal level.

In order to deal with this problem, according to the embodiment, a failed sampling number of times is counted, the unknown signal level for the failed sampling is forced to be “0” , the unknown signal level for the succeeded sampling is multiplied by a multiplier. The multiplier equals “the failed sampling number of times” plus 1. This multiplier is indicated as “Increment i” in Figure 19. Thus, the resultant difference value becomes

“-r1-r2-r3-r4+0+0+0+4* (s4) ” .

In this way, it is possible to evenly scale the known level measurement and the unknown level measurement. Since the appropriately scaled value is added to the 4 reference levels, the appropriate difference value may be obtained.

5.3 Sun black correction

The correlated double sampling (CDS) is advantageous because it can reduce noise component. However, the CDS may cause a sun black (sun spot) phenomenon. In normal operation, when the image sensor receives strong light, the corresponding pixels indicate bright values. In case of the sun black phenomenon, even if the image sensor receives very strong light, the corresponding pixel level is set to “a low value” , and thus the pixel disadvantageously appears as black.

When the correlation double sampling (CDS) is performed, as described with reference to the pixel 311 in Figure 3A, initially, when the transfer transistor Tr1 and the reset transistor Tr2 are in the OFF state, the selection transistor Tr4 is turned ON, and the voltage level of the floating diffusion layer (FD) is measured as the reference level. However, when the sensor receives abnormally strong light, the electrical charge of the photodiode (PD) may flow into the floating diffusion layer (FD) even if Tr1 is in the OFF state. In this case, the voltage level of the floating diffusion layer (FD) moves toward the lower limit of the output voltage range, the voltage level becomes actually comparable to the unknown signal level. Even if the difference between the unknown signal level and the voltage level of the floating diffusion layer (FD) in such a situation is measured, only 0 level (0-0=0) is obtained, and the appropriate difference value is not obtained. Thus, the sun black phenomenon occurs.

In order to deal with this phenomenon, the image sensor according to this embodiment may use a clamp circuit to detect that the voltage level of the floating diffusion layer (FD) or the pixel source follower is in the nearly lower limit of the output voltage range, and to clamp the column voltage to a predetermined voltage, thereby detecting and correcting the sun black phenomenon.

Specifically, when the voltage level of the output signal line (e.g., D _m) is in the nearly lower limit of the output voltage range due to the sun black phenomenon, the clamp circuit detects this situation and pulls-up the output signal line voltage to the predetermined voltage, then the Auto Zero operation is performed (the AZ switch is closed) . After the Auto Zero operation, the clamp circuit is turned off. Then, the voltage level of the pixel side input port INN of the comparator 314 moves toward the lower limit of the INP operation voltage range (as depicted in Figure 20) . In this situation, a normal reference level can not be obtained because the comparator 314 does not output any normal output pulse, thus the images sensor can detect that the sun black phenomenon has occurred.

In this situation, the reference level is forcibly set to the clamp voltage level in this embodiment. When entering the unknown signal level sampling, a predetermined gray code is forcibly set in the gray code latch circuit 32. The predetermined gray code may be a code corresponding to a Full Code of the ADC. In other words, although no sampling is successful for the reference level or the un-know signal level in the correlated double sampling (CDS) , the read-out circuit 313 can output the Full Code after the CDS period, thereby correcting the sun black in the image (it is possible to forcibly set the strongly bright situation) .

6. Electronic Apparatus

The embodiments described herein may be applied to a variety of devices including mobile devices and stationary devices. An exemplary electronic apparatus according to the embodiment will be described with reference to Figure 21. An electronic apparatus may be a device that provides a user with an image capture function and/or data connectivity, a handheld device with a wireless connection function, or another processing device connected to a wireless modem (for example, a digital camera, a single-lens reflex camera, or a smartphone) . Alternatively, the electronic apparatus may be another intelligent device with an image capture function and a display function (for example, a wearable device, a tablet computer, a PDA (Personal Digital Assistant, personal digital assistant) , a drone, or an aerial photographer) .

Figure 21 is a schematic diagram of an optional hardware structure of the electronic apparatus 100 which is the exemplary electronic apparatus. Referring to Figure 10, the electronic apparatus 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a imaging device 101, an audio circuit 160, a speaker 161, a microphone 162, an earphone jack 163, a processor 170, an external interface 180, and a power supply 190.

The radio frequency (RF) unit 110 may be configured to send and receive information or send and receive a signal in a call process. Generally, an RF unit includes but is not limited to an antenna, an amplifier, a transceiver, a coupler, a low noise amplifier (LNA) , a duplexer, and the like. In addition, the radio frequency unit 110 may communicate with a network device and another device through wireless communication. Any communications standard or protocol may be used for the wireless communication.

The memory 120 may be configured to store instructions and data. The memory 120 may mainly include an instruction storage area and a data storage area. The instruction storage area may store software such as an operating system, an application, and instructions. The data storage area may store an image which is obtained by the imaging device 101, audio data which is input or output by the audio circuit 160, an image displayed by the display unit 140, data used for an operation process performed by the processor 170, and other various transient or permanent data.

The input unit 130 may be configured to receive input digit or character information in the electronic apparatus 100. Specifically, the input unit 130 may include a touchscreen 131 and other input devices 132. The touchscreen 131 may collect a touch operation of the user on or near the touchscreen, and drive a corresponding connection apparatus according to a preset program. The touchscreen 131 may detect a touch action of the user on the touchscreen, convert the touch action into a touch signal, send the touch signal to the processor 170, and receive and execute a command sent by the processor 170. Another input device 132 may include but is not limited to one or more of a physical keyboard, a function key (such as a volume control key or a power on/off key) , a trackball, a mouse, a joystick, and the like.

The display unit 140 may be configured to display information input by the user, information provided for the user, various menus of the electronic apparatus 100, or the like. In the embodiments, the display unit 140 is configured to display an image obtained by using the imaging device 101, where the image may include a preview image in some shooting modes, an image that is captured, an image that is processed by using a specific algorithm after shooting, or the like.

The imaging device 101 is configured to collect a still image or moving images and may be enabled through triggering by an application program instruction, to implement a shooting function or a video camera function. The imaging device 101 may include components such as an imaging lens, a light filter, and an image sensor. Particularly, the imaging device 101 according to the embodiment is an image sensor such as a CMOS image sensor. The image sensor may include the analog to digital converter depicted with reference to Figures 1, 3A, or the like. Light emitted or reflected by an object to be shot enters the imaging lens and is aggregated on the image sensor by passing through the light filter. The imaging lens is mainly configured to aggregate light emitted or reflected by an object to be shot, in a shooting field of view, and perform imaging. The light filter is mainly configured to filter out an extra light wave (for example, a light wave other than visible light, such as infrared light) from light. The image sensor is mainly configured to perform optical-to-electrical conversion on a received optical signal, convert the optical signal and the light intensity change into an electrical signal, and input the electrical signal to the processor 170 for subsequent processing.

The audio circuit 160, the speaker 161, the microphone 162, and an earphone jack 163 may provide an audio interface between the user and the electronic apparatus 100. The audio circuit 160 may transmit, to the speaker 161, an electrical signal converted from received audio data, and the speaker 161 converts the electrical signal into a sound signal for output. Conversely, the microphone 162 is configured to collect a sound signal, and may convert the collected sound signal into an electrical signal. The audio circuit may also include an earphone jack 163, configured to provide a connection interface between the audio circuit and an earphone.

The processor 170 is a control center of the electronic apparatus 100, and is connected to various parts of the electronic apparatus 100 through various interfaces and signal lines. The processor 170 performs various functions of the electronic apparatus 100, executes the instruction stored in the memory 120, and invokes the data stored in the memory 120, thereby processing the data. In some embodiments, the processor and the memory may be implemented on a single chip. In some embodiments, the processor and the memory may be separately implemented on independent chips.

The electronic apparatus 100 further includes the external interface 180. The external interface 180 may be a standard micro-USB interface or a multi-pin connector. The external interface may be configured to connect the electronic apparatus 100 to another apparatus for communication, or may be configured to connect to a charger to charge the electronic apparatus 100.

The electronic apparatus 100 further includes the power supply 190 (such as a battery) that supplies power to each component. Preferably, the power supply may be logically connected to the processor 170, so as to implement functions such as a charging function, a discharging function, and power consumption management by using the power supply management system.

Persons skilled in the art may understand that Figure 21 is merely an example of the electronic apparatus, and does not constitute any limitation on the embodiments. The electronic apparatus may include more or fewer components than those shown in the figure, or combine some components, or have different components.

The division into parts of elements in this specification are merely for logical function division, which prioritizes convenience of explanation. It is to be understood that some or all of the divided elements may be integrated, in actual implementation, into one physical entity, or may be physically separated. For example, each of the foregoing elements may be a separate processing element, or may be integrated on a chip of an electronic apparatus. Alternatively, described processing elements may be stored in a storage element of a controller in a form of program code, and invoke and execute various functions, as appropriate. In addition, the processing elements may be integrated or may be implemented independently. The processing element may be an integrated circuit chip and has a signal processing capability. In an implementation process, steps in the foregoing methods or the foregoing elements can be implemented by using a hardware integrated logical circuit in the processing element, or by using instructions in a form of software.

Persons skilled in the art will understand that the embodiments of the present invention may be provided as a method, a device, a storage medium, or a computer program. Therefore, the present invention may use a form of hardware only embodiments, or embodiments with a combination of software and hardware.

The method, the device, the storage medium, and the computer program which relate to the embodiments of the present invention are described with reference to the flowcharts and/or block diagrams. It is to be understood that computer program instructions may be used to implement each process and/or each block in the flowcharts and/or the block diagrams. These computer program instructions may be provided for a general-purpose computer, a dedicated computer, an embedded processor, or a processor of any other programmable data processing device, so that the executed instructions generate the functions described with reference to the embodiments.

These computer program instructions may be stored in an appropriate storage medium, or may be transmitted on a transmission medium. These computer program instructions may be loaded onto a computer or another programmable data processing device, so that a series of operations are performed by the computer, thereby generating the functions described with reference to the embodiments.

Although the embodiments of the present invention are described, persons skilled in the art can make changes and modifications to these embodiments. Therefore, the following claims are intended to be construed to encompass the embodiments and all changes and modifications thereto, within the scope of the present invention.

LIST OF REFERENCE SYMBOLS

10, 300 Image sensor

11, 311 Pixel

12, 312 Row decode circuit

13, 313 Read-out circuit

14, 314 Comparator

320 Processor

RELATED-ART DOCUMENTS

Patent Document 1: International Patent Publication No. WO2018/123609

Patent Document 2: United State Patent No. 9380246

Patent Document 3: International Patent Publication No. WO2018/123609

Patent Document 4: Japanese Patent Publication No. 2011-60046

Patent Document 5: Japanese Patent Publication No. 2005-57612

Claims

A logic circuit (34) configured to operate in a mode of operations including a code conversion mode and an addition mode, the logic circuit comprising:

a first logic circuit (LC1) outputting a first operation result, the first operation result being a result of an exclusive-OR operation to input bits;

a second logic circuit (LC2) outputting a second operation result (B _n/X _n) , the second operation result (B _n/X _n) being a result of an exclusive-OR operation to input bits including the first operation result; and

a selector (SEL) operating according to the mode of operation;

(i) wherein in the code conversion mode, the selector (SEL) outputs the second operation result (B _n) , the input bits to the first logic circuit (LC1) includes a bit (G _n+1) in gray code representation and a bit (B _n+2) in binary code representation of a second number-to-be-added, and the input bits to the second logic circuit (LC2) further includes a bit (G _n) in gray code representation of the second number-to-be-added; and

(ii) wherein in the addition mode, the selector (SEL) outputs a carry bit (C _n) in an addition of a first number-to-be-added (A) and the second number-to-be-added (B) , the input bits to the first logic circuit (LC1) includes a bit (A _n) of the first number-to-be-added and a carry bit (C _n-1) of a digit lower than the carry bit (C _n) , and the input bits to the second logic circuit (LC2) includes a bit (B _n) of the second number-to-be-added.
A cascaded logic circuit including a plurality of logic circuits in cascaded connection, each of which comprises the logic circuit (34) according to claim 1, the second operation result of the logic circuit in a first stage or a carry bit output from the logic circuit in the first stage is selectively connected as a carry bit to the logic circuit in a second stage, according to a mode setting of the code conversion mode or the addition mode.
The cascaded logic circuit according to claim 2, further including a first latch circuit storing (i) the lowest output bit among the bits converted at a time in the code conversion mode, or (ii) a carry bit in an operation of the highest bit among the operations performed at a time in the addition mode, according to the mode of operation, wherein an output of the first latch is provided to the logic circuit in the first stage as a carry bit input.
The cascaded logic circuit according to claim 3, wherein the first latch circuit respectively stores (i) the lowest output bit in the code conversion mode, and (ii) the carry bit in the operation of the highest bit in the addition mode, as two kinds of data, wherein one of the two kinds of data is provided to the logic circuit in the first stage as the carry bit input, according to the mode of operations.
An arithmetic logic operation circuit (ALU) comprising:

the logic circuit (34) according to claim 1; and

a second latch circuit (35) storing the output of the selector (SEL) .
The arithmetic logic operation circuit (ALU) according to claim 5, wherein the second latch circuit (35) obtains and stores bits in the binary code representation of the second number-to-be-added (B) through the code conversion mode, before starting the addition mode.
The arithmetic logic operation circuit (ALU) according to claim 6, in the code conversion mode, further having

a function in which a most significant bit (MSB) is selectively set to a fixed value 1, so as to obtain a 1’s complement in the binary code representation, in the code conversion mode; and

a function in which the carry bit in an operation of a least significant bit (LSB) is set to 1, so as to obtain a 2’s complement for addition, in the addition mode.
A gray code sampling unit comprising:

a fourth latch circuit (32) storing a gray code;

the arithmetic logic operation circuit (ALU, 33) according to claim 6 that converts the gray code obtained from the fourth latch circuit (32) into a binary code; and

a third latch circuit (36) that has stored the first number-to-be-added (A) before the beginning of the addition mode, and stores an addition result (X) of the first number-to-be-added (A) and the second number-to-be-added (B) at the end of the addition mode.
The gray code sampling unit according to claim 8, wherein when the bits in the binary code representation of the first number-to-be-added are stored in the third latch (36) , following operations are repetitively performed:

in the code conversion mode, providing the bits in the gray code representation of the second number-to-be-added (B) to the first logic circuit (LC1) and the second logic circuit (LC2) , and

at the end of the addition mode, storing the addition result (X _n) of the first number-to-be-added (A _n) and the second number-to-be-added (B _n) , in the third latch circuit (36) ;

wherein the addition result stored in the third latch circuit (36) corresponds to a result of Correlated Double Sampling (CDS) or Correlated Multiple Sampling (CMS) .
The gray code sampling unit according to claim 9, wherein if a gray code was not sampled within a predetermined sampling period in multiple sampling operations for an unknown level in the CMS, then in the code conversion mode, a gray code bit corresponding to a 0-level is inputted to the first logic circuit, and the second number-to-be-added that is weighted by the number of occurrences of the 0-level input event is used for the addition.
The gray code sampling unit according to claim 9, wherein if a gray code was not sampled within a predetermined sampling period in a sampling operation for the reference level in the CDS or CMS, then in the code conversion mode, predetermined gray code bits are input to the first logic circuit.
A single slope analog-to-digital (AD) conversion circuit comprising the gray code sampling unit according to claim 8, wherein the signal slope AD conversion circuit obtains a digital output from a gray code counter.
The single slope analog-to-digital (AD) conversion circuit according to claim 12, wherein if a signal level does not have a magnitude within a predetermined level range in multiple sampling operations for an unknown level in the CMS, then in the code conversion mode, a gray code bit corresponding to a 0-level is inputted to the first logic circuit, and the second number-to-be-added that is weighted by the number of occurrences of the 0-level input event is used for the addition.
The single slope analog-to-digital (AD) conversion circuit according to claim 12, wherein if a reference level used to measure a signal level does not have a magnitude within a predetermined level range in a sampling operation for the reference level in the CDS or CMS, then in the code conversion mode, predetermined gray code bits are input to the first logic circuit.
A parallel AD conversion circuit comprising a plurality of AD converters in parallel, each of which comprises the single slope analog-digital (AD) conversion circuits according to claim 12, wherein the plurality of AD converters share the gray code counter.
A CMOS image sensor comprising the parallel AD conversion circuit according to claim 15.
An operation method in a logic circuit configured to operate in a mode of operations including a code conversion mode and an addition mode, the method including:

in the code conversion mode,

by a first logic circuit, outputting a first operation result (B _n+1) , the first operation result (B _n+1) being a result of an exclusive-OR operation to input bits including a bit (G _n+1) in gray code representation and a bit (B _n+2) in binary code representation of a second number-to-be-added,

by a second logic circuit, outputting a second operation result (B _n) , the second operation result (B _n) being a result of an exclusive-OR operation to input bits including the first operation result and a bit (G _n) in gray code representation of the second number-to-be-added; and

in the addition mode,

by the first logic circuit, outputting a third operation result, the third operation result being a result of an exclusive-OR operation to input bits including a bit (A _n) of the first number-to-be-added and a carry bit (C _n-1) of a digit lower than the carry bit (C _n) ,

by the second logic circuit, outputting a fourth operation result (X _n) , the fourth operation result (X _n) being a result of an exclusive-OR operation to input bits including the third operation result and a bit (B _n) of the second number-to-be-added.