CN114982222A

CN114982222A - Image reading circuit, image sensor and terminal equipment

Info

Publication number: CN114982222A
Application number: CN202080090751.0A
Authority: CN
Inventors: 郑胜群; 叶天翔; 潘撼; 唐样洋
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-01-08
Filing date: 2020-01-08
Publication date: 2022-08-30
Also published as: WO2021138838A1

Abstract

The embodiment of the application provides an image reading circuit, an image sensor and a terminal device. Wherein the image reading circuit includes: the photoelectric conversion circuit comprises a photoelectric sensor and a reset circuit, wherein the photoelectric sensor is used for receiving photons and outputting photoelectrons, and the reset circuit is used for outputting a reset voltage; the photoelectric conversion circuit is also used for collecting pixel voltage, the pixel voltage is the sum of a first voltage and a reset voltage, the first voltage is generated by photoelectrons, and the first voltage is positively correlated with the illumination intensity; the judging circuit is used for determining a first sampling frequency according to the pixel voltage, wherein the first sampling frequency is in negative correlation with the pixel voltage; and the correlated multi-sampling circuit is used for performing correlated multi-sampling on the pixel voltage and the reset voltage according to the first sampling times so as to determine the first voltage. The quality of an output image is improved, and the dynamic range of pixels is improved.

Description

Image reading circuit, image sensor and terminal equipment

Technical Field

The present application relates to the field of electronic circuit technology, and in particular, to an image reading circuit, an image sensor, and a terminal device.

Background

An image sensor is a sensor that converts an optical image into an electrical signal, and is widely used in terminal devices such as digital cameras and smart phones. Currently, a common image sensor is a CMOS Image Sensor (CIS) manufactured by a CMOS process. An image sensor (CIS) includes a circuit called an image reading circuit, which mainly includes two parts: a light-sensing portion and a non-light-sensing portion (the non-light-sensing portion is also referred to as a data reading portion). The light sensing portion is composed of a pixel array, and a basic unit included in the pixel array is called a pixel (or called a photoelectric conversion circuit), and each pixel includes a photosensor and other circuits. The photosensors in the pixels convert received photons (phototons) into photoelectrons (photoelectrons) using the photoelectric effect. Other circuits (except the photosensor) in the pixel convert and store the photoelectrons to obtain corresponding electric signals. The data readout section (including the column readout circuit) quantizes and processes the electric signal.

The process of receiving photons by the photosensor is called exposure (exposure), and in order to eliminate the influence of photoelectrons generated by each exposure on the result of the next exposure, the image reading circuit performs a reset operation after each exposure is completed. Currently, Correlated Multiple Sampling (CMS) is generally used to eliminate reset noise generated by a reset operation and random noise generated by a circuit itself.

A reset circuit is included in the photoelectric conversion circuit, and a voltage applied to the photoelectric conversion circuit when the reset circuit performs a reset operation is referred to as a reset voltage. Since the photoelectric conversion circuit needs to receive the photoelectrons after the reset operation, the image reading circuit collects voltages, including the reset voltage and the voltage generated by the photoelectrons, according to the received photoelectrons, and the collected voltages are referred to as pixel voltages. The specific operations of correlated multisampling are: the pixel voltage and the reset voltage are sampled a plurality of times. Therefore, the voltage value actually generated by the received photoelectrons can be obtained by subtracting the pixel voltage sampled for a plurality of times from the reset voltage sampled for a plurality of times and dividing the subtraction by the number of times of sampling, wherein the number of times of sampling is also called as M, and M is a positive integer. For the effective voltage (reset voltage and voltage generated by photoelectrons), which is stable in the time domain, the result of multiple sampling is equivalent to multiplying the effective voltage by M times. For random noise, the random noise is random in the time domain and has positive or negative values, and the random noise accumulated by multiple sampling is equivalent to a mean filtering result in the time domain, so that the noise is effectively suppressed after multiple sampling. By subtracting the pixel voltage and the reset voltage, the reset noise can be effectively eliminated.

At the end of the image reading circuit, analog signals such as voltage need to be converted into digital signals (e.g., digital codes) by an analog-to-digital converter (ADC) for subsequent processing of components. However, in the current related multi-sampling technique, the number of sampling times (M value) is fixed. Because the light intensity is in direct proportion to the pixel voltage, in a scene with extremely high light intensity, the voltage value of the pixel voltage acquired by the image reading circuit is also high, and when the sampling times are large, the result of multiplying the pixel voltage by M often exceeds the quantization range of the ADC after related multi-sampling. A new error is generated during the ADC analog-to-digital conversion process, which in turn affects the quality of the output image.

Disclosure of Invention

The embodiment of the application provides an image reading circuit, an image sensor and a terminal device in a first aspect, so that the quality of an output image is improved, and the dynamic range of pixels is improved.

In view of this, the embodiment of the present application proposes the following technical solutions:

in a first aspect, an embodiment of the present application provides an image reading circuit, including: a photoelectric conversion circuit, a determination circuit (determination circuit) and a correlated multi-sampling circuit (CMS circuit). The photoelectric conversion circuit comprises a photoelectric sensor and a reset circuit, the photoelectric sensor converts received photons into photoelectrons by utilizing a photoelectric effect, the reset circuit is used for outputting reset voltage, optionally, the reset circuit can be realized by a reset circuit (reset circuit) formed by one or more components, or can be realized by one or more reset triodes or reset transistors, and the limitation is not made here; the photoelectric conversion circuit is used for collecting pixel voltage and respectively outputting the pixel voltage to the judging circuit and the related multi-sampling circuit, and particularly, the photoelectric conversion circuit further collects photoelectrons output by the photoelectric sensor on the basis of electrons corresponding to reset voltage to finish the collection of the pixel voltage; the judging circuit is used for determining a first sampling time according to the pixel voltage, wherein the first sampling time is inversely related to the pixel voltage. Specifically, when the pixel voltage acquired by the photoelectric conversion circuit is larger, the first sampling frequency determined by the judgment circuit according to the pixel voltage is smaller. When the pixel voltage acquired by the photoelectric conversion circuit is smaller, the first sampling frequency determined by the judgment circuit according to the pixel voltage is larger; the correlated multi-sampling circuit is used for performing correlated multi-sampling on the pixel voltage and the reset voltage according to the first sampling times to determine a first voltage, wherein the first voltage is a voltage generated by photoelectrons, and the first voltage is positively correlated with the illumination intensity.

In the embodiment of the application, the image reading circuit determines the sampling times of the correlated multi-sampling according to the pixel voltage, and then, the image reading circuit performs the correlated multi-sampling on the pixel voltage and the reset voltage according to the determined sampling times to determine a first voltage, which is a voltage generated by photoelectrons. The photoelectric conversion circuit further collects photoelectrons output by the photoelectric sensor on the basis of electrons corresponding to the reset voltage to complete the collection of pixel voltage, so that the pixel voltage is positively correlated with the illumination intensity, namely the greater the illumination intensity is, the greater the pixel voltage is; the smaller the illumination intensity, the smaller the pixel voltage. Under the scene that the light intensity is extremely large, the image reading circuit determines lower sampling times according to the collected higher pixel voltage, avoids the phenomenon that the pixel voltage is multiplied by the sampling times and then exceeds the quantization range of the ADC, and improves the quality of an output image. In a scene (dark light environment) with extremely low light intensity, the image reading circuit determines higher sampling times according to smaller pixel voltage, reduces noise of an output image in the dark light environment, improves the quality of the output image and improves the dynamic range of pixels.

With reference to the first aspect, in one possible implementation of the first aspect, the photoelectric conversion circuit may further include: the pixel circuit comprises a first transistor, a second transistor, a first capacitor and a second capacitor, wherein the first transistor is electrically connected with the photoelectric sensor, the first transistor is electrically connected with the second capacitor, the first transistor is electrically connected with the reset circuit, the first transistor is used for switching on or off a connection path between the photoelectric sensor and the second capacitor, the first transistor is also used for controlling the switching on or off of the connection path between the reset circuit and the second capacitor, and the second capacitor is used for collecting the pixel voltage; the second transistor is electrically connected with the first transistor, the second transistor is electrically connected with the first capacitor, the second transistor and the first transistor are jointly used for controlling the connection or disconnection of a connection channel between the reset circuit and the first capacitor, and the first capacitor is used for collecting the reset voltage; the correlated multi-sampling circuit is electrically connected with the second transistor, and the second transistor is used for controlling the connection or disconnection of a connection path between the correlated multi-sampling circuit and the first capacitor; the correlated multi-sampling circuit is electrically connected with the second capacitor.

In the embodiment of the present application, with the above-mentioned photoelectric conversion circuit, the first capacitor collects the reset voltage under the common control of the first transistor and the second transistor, and the second capacitor collects the pixel voltage under the control of the first transistor, so that the photoelectric conversion circuit can output the pixel voltage to the judgment circuit (and the related multi-sampling circuit) first, so that the judgment circuit determines the first sampling times according to the pixel voltage, wherein the pixel voltage is positively correlated with the illumination intensity, and the first sampling times is negatively correlated with the pixel voltage.

With reference to the first aspect, in a possible implementation of the first aspect, the determining circuit specifically includes a first voltage comparator (voltage comparator), a threshold voltage generating circuit (threshold voltage generator), and a multi-sampling time selection circuit (multi-sampling time selection), the first voltage comparator is electrically connected to the threshold voltage generating circuit, and the threshold voltage generating circuit is configured to generate a first threshold voltage; the first voltage comparator is electrically connected with the second capacitor and used for comparing the first threshold voltage with the pixel voltage to generate a first voltage comparison result; the first voltage comparator is electrically connected with the multi-sampling frequency selection circuit, and the multi-sampling frequency selection circuit determines the first sampling frequency according to the first voltage comparison result.

Specifically, the first voltage comparator compares the first threshold voltage with the pixel voltage from the photoelectric conversion circuit to determine a first voltage comparison result. For example, the first threshold voltage generated by the threshold voltage generating circuit includes 0.25 volts (V), 0.5V, and 0.8V. The pixel voltage from the photoelectric conversion circuit 101 is 0.45V. The first voltage comparator first compares 0.25V (first threshold voltage) with 0.45V (pixel voltage), and outputs a voltage comparison result of 1 (i.e., the pixel voltage is greater than the first threshold voltage). Then, 0.5V (first threshold voltage) is compared with 0.45V (pixel voltage), and the output voltage comparison result is 0 (i.e., the pixel voltage is less than the first threshold voltage). The voltage comparison results are collectively referred to as first voltage comparison results. The first voltage comparator is preset with a plurality of voltage intervals for determining the voltage intervals corresponding to the pixel voltages, and each voltage interval is preset with a corresponding sampling frequency. The first voltage comparator determines a voltage interval in which the pixel voltage is located according to the first voltage comparison result. The preset voltage intervals in the first voltage comparator are respectively as follows: the first voltage interval is 0V-0.25V; the second voltage interval is 0.25V-0.5V; the third voltage interval is 0.5V-0.8V; the fourth voltage interval is 0.8V-1.5V. Therefore, the first voltage comparator determines that the pixel voltage is in the second voltage interval. The first voltage comparator outputs the first voltage comparison result to the multi-sampling-number selection circuit.

In the embodiment of the application, the judgment circuit determines the voltage interval where the pixel voltage output by the photoelectric conversion circuit is located through the matched use of the first voltage comparator, the threshold voltage generation circuit and the multi-sampling frequency selection circuit, and further determines the first sampling frequency corresponding to the pixel voltage. The realization flexibility of the scheme is improved.

With reference to the first aspect, in a possible implementation of the first aspect, the determining circuit may further include a second voltage comparator, the second voltage comparator is electrically connected to the threshold voltage generating circuit, and the second voltage comparator is electrically connected to the multiple sampling number selecting circuit; the second voltage comparator is used for determining a second voltage comparison result according to a second threshold voltage and the pixel voltage, and the second threshold voltage is generated by the threshold voltage generation circuit; the multi-sampling-time selection circuit is specifically used for: determining a voltage interval of the pixel voltage according to the first voltage comparison result and the second voltage comparison result; and determining the first sampling times according to the voltage interval. Specifically, the number of the first voltage comparators and the second voltage comparators is not limited herein.

In the embodiment of the application, by arranging the first voltage comparator and the second voltage comparator in the judging circuit, the judging circuit can simultaneously compare the pixel voltage domain with a plurality of threshold voltages (a first threshold voltage and a second threshold voltage), and the speed of determining the voltage comparison result (the first voltage comparison result and the second voltage comparison result) of the pixel voltage is greatly increased, so that the speed of reading the pixel image can be effectively improved.

With reference to the first aspect, in a possible implementation of the first aspect, the image reading circuit may further include a first analog-to-digital converter (ADC), which generally refers to an electronic component that converts an analog signal (voltage) into a digital signal (digital code), and a pixel processor, and the ADC is configured to convert the electrical signal (voltage) into the digital code (digital code). The digital code is a binary code used by a computer, such as "0101001", to indicate the magnitude of the signal. The related multi-sampling circuit is electrically connected with the judging circuit, the related multi-sampling circuit is electrically connected with the first analog-to-digital converter, the related multi-sampling circuit is electrically connected with the photoelectric conversion circuit, the first analog-to-digital converter is electrically connected with the pixel processor, and the pixel processor is electrically connected with the judging circuit; the correlated multi-sampling circuit is used for performing correlated multi-sampling on the pixel voltage and the reset voltage to obtain a second voltage, wherein the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after correlated multi-sampling, and the second voltage is the product of the first voltage and the first sampling times; the first analog-to-digital converter is used for converting the second voltage into a second digital code; the pixel processor is used for determining a first digital code according to the second digital code and the first sampling times, and the first digital code is a digital code of the first voltage.

Specifically, firstly, a related multi-sampling circuit performs related multi-sampling on a pixel voltage and a reset voltage according to a control time sequence to obtain a second voltage, wherein the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after the related multi-sampling, the control time sequence is determined by a judging circuit according to a first sampling frequency, and the second voltage is the product of the first voltage and the first sampling frequency; secondly, the first analog-to-digital converter converts the second voltage into a second digital code; thirdly, since the pixel processor is electrically connected to the multi-sampling number selection circuit, the pixel processor determines a first digital code according to the first sampling number from the multi-sampling number selection circuit and a second digital code from the first analog-to-digital converter, the first digital code being a digital code of the first voltage. Optionally, the pixel processor may further perform post-processing such as filtering on the first digital code (digital signal).

In the embodiment of the present application, the voltage output by the correlated multi-sampling circuit is processed by the first analog-to-digital converter for further processing by the pixel processor and other elements.

With reference to the first aspect, in a possible implementation of the first aspect, the image reading circuit further includes a first analog-to-digital converter and a pixel processor, the correlated multi-sampling circuit is electrically connected to the determination circuit, the correlated multi-sampling circuit is electrically connected to the photoelectric conversion circuit, the correlated multi-sampling circuit is electrically connected to the first analog-to-digital converter, the first analog-to-digital converter is electrically connected to the pixel processor, and the pixel processor is electrically connected to the determination circuit; the correlated multi-sampling circuit is also used for acquiring the pixel voltage after the pixel voltage is subjected to correlated multi-sampling for the first sampling times to obtain a first pixel voltage; the first analog-to-digital converter is used for converting the first pixel voltage into a third digital code; the correlated multi-sampling circuit is also used for acquiring the reset voltage after correlated multi-sampling of the first sampling times to obtain a first reset voltage; the first analog-to-digital converter is also used for converting a first reset voltage into a fourth digital code, wherein the first reset voltage is the accumulated sum of the reset voltage after the reset voltage is subjected to the correlated multi-sampling by the correlated multi-sampling circuit for the first sampling times; the pixel processor is used for determining a second digital code according to the third digital code and the fourth digital code, wherein the second digital code is a digital code corresponding to a second voltage, and the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after related multi-sampling; the pixel processor is further configured to determine a first digital code according to the second digital code and the first sampling number, where the first digital code is a digital code of the first voltage.

Specifically, first, the correlated multi-sampling circuit outputs a first pixel voltage to the first analog-to-digital converter after the pixel voltage is subjected to correlated multi-sampling for a first sampling number of times, where the first pixel voltage is an accumulated sum of pixel voltages of the correlated multi-sampling circuit after the pixel voltage is subjected to correlated multi-sampling for the first sampling number of times. The first analog-to-digital converter converts the first pixel voltage into a third digital code; and secondly, the related multi-sampling circuit carries out reset operation so as to eliminate electrons remained by related multi-sampling on the pixel voltage in the previous time. Then, the correlated multi-sampling circuit outputs a first reset voltage to the first analog-to-digital converter after the reset voltage is subjected to correlated multi-sampling for a first sampling number of times, and the first reset voltage is the accumulated sum of the reset voltages of the correlated multi-sampling circuit after the reset voltage is subjected to correlated multi-sampling for the first sampling number of times. The first analog-to-digital converter is used for converting the first reset voltage into a fourth digital code; thirdly, the pixel processor determines a second digital code according to the third digital code and the fourth digital code, wherein the second digital code is a digital code corresponding to a second voltage, and the second voltage is the accumulated sum of the voltage values of the pixel voltage and the reset voltage after relevant multi-sampling; and the pixel processor determines a first digital code according to the second digital code and the first sampling times, wherein the first digital code is a digital code of the first voltage.

In the embodiment of the application, the first analog-to-digital converter respectively quantizes the accumulated sum of the pixel voltage and the accumulated sum of the reset voltage into digital codes and then performs subtraction operation. Through the operation on the digital domain, the system error generated by the analog-to-digital converter is eliminated, thereby improving the fixed pattern error (FPN) of the image reading circuit.

With reference to the first aspect, in one possible implementation of the first aspect, the photoelectric conversion circuit may further include a first source follower; the first source follower is electrically connected with the photoelectric sensor, the first source follower is electrically connected with the reset circuit, the first source follower is electrically connected with the first transistor, and the first source follower is used for isolating current between the photoelectric sensor and the first transistor, and between the reset circuit and the first transistor.

In the embodiment of the present application, the first source follower isolates the current between the photosensor and the first transistor, and between the reset circuit and the first transistor, so as to improve Conversion Gain (CG), and further improve signal to noise ratio (SNR) of the image sensor using the image reading circuit.

With reference to the first aspect, in a possible implementation of the first aspect, the determining circuit may further include: the circuit comprises an S6 switch, an AZ1 switch, a C3 capacitor and a C4 capacitor, wherein two ends of the C3 capacitor are respectively and electrically connected with an S5 switch and a first voltage comparator, the other end of the S5 switch is electrically connected with a photoelectric conversion circuit, one end of the S6 switch is electrically connected with a threshold voltage generating circuit, the other end of the S6 switch is electrically connected with one end of the C4 capacitor, and the other end of the C4 capacitor is electrically connected with the first voltage comparator. The positive phase input end and the negative phase input end of the first voltage comparator are respectively electrically connected with an AZ1 switch, and the other end of the AZ1 switch is used for connecting a reference voltage Vcom 2.

In the embodiment of the application, the first voltage comparator eliminates errors by using a voltage difference value obtained by automatic zero-adjusting measurement so as to improve the accuracy of the first voltage comparator. A capacitor is arranged between the first voltage comparator and the threshold voltage generation circuit and between the first voltage comparator and the photoelectric conversion circuit, and the first voltage comparator can determine the voltage value interval of the pixel voltage under the condition of using lower first threshold voltage and power supply voltage while protecting the first voltage comparator, so that the power consumption of the image reading circuit is reduced.

With reference to the first aspect, in one possible implementation of the first aspect, the photoelectric conversion circuit may further include a second source follower; the second source follower is electrically connected with the second transistor, the second source follower is electrically connected with the second capacitor, the second source follower is electrically connected with the judging circuit and the related multi-sampling circuit, and the second source follower is used for amplifying the pixel voltage and the reset voltage output by the photoelectric conversion circuit.

In a second aspect, an embodiment of the present application provides an image reading method that may be applied to an image reading circuit as described in the first aspect or any one of the possible implementations of the first aspect, the image reading method including:

and collecting the reset voltage. Optionally, the reset circuit outputs a reset voltage, the first transistor and the second transistor are in a conducting state, and the first capacitor and the second capacitor collect the reset voltage;

and collecting pixel voltage. Optionally, the photoelectric sensor outputs photoelectrons, at this time, the first transistor is in an on state, and the second transistor is in an off state, so that the first capacitor maintains a reset voltage, and the second capacitor further collects photoelectrons output by the photoelectric sensor on the basis of electrons corresponding to the reset voltage, thereby completing the collection of the pixel voltage;

a first number of samples is determined from the pixel voltage, wherein the first number of samples is inversely related to the pixel voltage. Optionally, the first sampling number is determined according to the pixel voltage. The threshold voltage generating circuit is used for generating one or more first threshold voltages, and the first threshold voltages are output to the first voltage comparator. The first voltage comparator compares the first threshold voltage with a pixel voltage from the photoelectric conversion circuit to determine a first voltage comparison result. The multi-sampling frequency selection circuit is preset with sampling frequencies corresponding to each voltage interval, and can determine a first sampling frequency according to a first voltage comparison result and determine a control sequence (control sequences) of a related multi-sampling circuit corresponding to the first sampling frequency;

and performing related multi-sampling on the pixel voltage and the reset voltage according to the first sampling times to determine the first voltage. Optionally, the correlated multiple sampling circuit is specifically configured to perform correlated multiple sampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit according to the first sampling frequency output by the determination circuit, and output a second voltage to the first analog-to-digital converter, where the second voltage is an accumulated sum of the first voltage, and the first voltage is a voltage generated by photoelectrons. The correlated multi-sampling circuit is electrically connected to the first analog-to-digital converter. The related multi-sampling circuit comprises one or more switches and one or more capacitors, and is used for performing related multi-sampling on the pixel voltage and the reset voltage according to the control time sequence configured by the multi-sampling time selection circuit. Specifically, when the first sampling number is 1, the pixel voltage and the reset voltage of the correlated multi-sampling circuit 10 are each subjected to sampling operation for 1 time; when the first sampling number of times is 2, the related multi-sampling circuit performs sampling operation on the pixel voltage and the reset voltage for 1 time respectively, and repeats the previous sampling operation, and so on.

In the embodiment of the application, because the sampling times (the first sampling times) of the pixel voltage are determined by the voltage value of the pixel voltage, the acquired pixel voltage is also higher in a scene with higher light intensity, and the lower first sampling times are determined according to the higher pixel voltage, so that the output voltage is prevented from exceeding the quantization range of the analog-to-digital converter, and the quality of the output image is improved. And under the scene of lower light intensity, the output pixel voltage is also lower, and a higher first sampling frequency is determined according to the lower pixel voltage, so that the noise of an output image under a dark light environment is reduced, the quality of the output image is improved, and the dynamic range of pixels is improved.

With reference to the second aspect, in a possible implementation of the second aspect, the determining the first sampling number according to the pixel voltage may include: generating a first threshold voltage; determining a first voltage comparison result according to the first threshold voltage and the pixel voltage; and determining the first sampling times according to the first voltage comparison result.

Specifically, a first voltage comparison result is determined according to a comparison between the first threshold voltage and the pixel voltage. For example, the first threshold voltage includes 0.25 volts (V), 0.5V, and 0.8V. The pixel voltage is 0.45V. First, 0.25V (first threshold voltage) and 0.45V (pixel voltage) are compared, and the comparison result of the output voltage is 1 (i.e. the pixel voltage is greater than the first threshold voltage). Then, 0.5V (first threshold voltage) is compared with 0.45V (pixel voltage), and the output voltage comparison result is 0 (i.e., the pixel voltage is less than the first threshold voltage). The voltage comparison results are collectively referred to as first voltage comparison results. The first voltage comparator is preset with a plurality of voltage intervals for determining the voltage intervals corresponding to the pixel voltages, and each voltage interval is preset with a corresponding sampling frequency. And determining the voltage interval of the pixel voltage according to the first voltage comparison result. The preset voltage intervals are respectively as follows: the first voltage interval is 0V-0.25V; the second voltage interval is 0.25V-0.5V; the third voltage interval is 0.5V-0.8V; the fourth voltage interval is 0.8V-1.5V. Accordingly, it is determined that the pixel voltage is in the second voltage interval. And determining a first sampling number according to the voltage interval.

In the embodiment of the application, the first sampling times corresponding to the pixel voltage are determined by determining the voltage interval where the pixel voltage is located. The implementation flexibility of the scheme is improved.

With reference to the second aspect, in one possible implementation of the second aspect, the method may further include: performing correlated multi-sampling on the pixel voltage and the reset voltage to obtain a second voltage, wherein the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after correlated multi-sampling, and the second voltage is the product of the first voltage and the first sampling times; converting the second voltage into a second digital code; and determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.

Specifically, firstly, the pixel voltage and the reset voltage are subjected to correlated multi-sampling to obtain a second voltage, wherein the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after the correlated multi-sampling, and the second voltage is the product of the first voltage and the first sampling times; secondly, converting the second voltage into a second digital code; and thirdly, determining a first digital code according to the first sampling times and the second digital code, wherein the first digital code is the digital code of the first voltage.

In the embodiment of the application, the voltage is converted into a digital code for further processing of a subsequent pixel processor and other elements.

With reference to the second aspect, in one possible implementation of the second aspect, the method may further include: converting the first pixel voltage into a third digital code according to the first pixel voltage, wherein the first pixel voltage is the accumulated sum of the pixel voltage after the pixel voltage is subjected to the correlated multi-sampling of the first sampling times; converting the reset voltage into a fourth digital code according to a first reset voltage, wherein the first reset voltage is the accumulated sum of the reset voltage after the reset voltage is subjected to related multi-sampling of the first sampling times; determining a second digital code according to the third digital code and the fourth digital code, wherein the second digital code is a digital code corresponding to a second voltage, and the second voltage is the accumulated sum of the pixel voltage and the voltage value of the reset voltage after relevant multi-sampling; and determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.

Specifically, first, after the pixel voltage is subjected to the correlated multisampling for the first sampling number of times, the first pixel voltage is output, and the first pixel voltage is the accumulated sum of the pixel voltages after the pixel voltage is subjected to the correlated multisampling for the first sampling number of times. Converting the first pixel voltage into a third digital code; and secondly, outputting the first reset voltage after the reset voltage is subjected to the correlated multi-sampling for the first sampling times, wherein the first reset voltage is the accumulated sum of the reset voltage after the reset voltage is subjected to the correlated multi-sampling for the first sampling times. Converting the first reset voltage into a fourth digital code; thirdly, determining a second digital code according to the third digital code and the fourth digital code, wherein the second digital code is a digital code corresponding to a second voltage, and the second voltage is the accumulated sum of the voltage values of the pixel voltage and the reset voltage after related multi-sampling; and determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.

In the embodiment of the application, after the accumulated sum of the pixel voltage and the accumulated sum of the reset voltage are quantized into the digital codes respectively, the subtraction operation is performed. Through the operation on the digital domain, the systematic error generated in the process of quantizing the voltage into the digital code is eliminated, so that the fixed pattern error (FPN) is improved.

In a third aspect, an embodiment of the present application further provides an image sensor, including a pixel control circuit and an image reading circuit, where the image reading circuit includes the image reading circuit as described in any one of the first aspect and the first aspect above, and the pixel control circuit is configured to control exposure of the image reading circuit.

In a fourth aspect, embodiments of the present application also provide an image capturing optical system comprising a lens group, a driving device, an image sensor and an image stabilization module, wherein the image sensor comprises the image sensor as described in the third aspect above. The lens group is used for converging light; the image sensor is used for processing the light rays converged by the lens group and outputting an image.

In a fifth aspect, an embodiment of the present application further provides a terminal device, including an image capturing optical system, a flash module, a focusing auxiliary module, an image signal processor, a user interface, and an image software processor, where the image capturing optical system includes the image capturing optical system according to the fourth aspect, the image capturing optical system includes an image sensor, the image sensor includes an image reading circuit, and the image reading circuit includes the image reading circuit according to any one of the first aspect and the first aspect as described above.

Drawings

Fig. 1 is a schematic diagram of a system structure of an image reading circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an image reading circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a photoelectric conversion circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic control timing diagram of a photoelectric conversion circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of an image reading circuit according to an embodiment of the present disclosure;

FIG. 6 is a control timing diagram of an image reading circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a simulation experiment according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another exemplary structure of an image reading circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of another control timing of the image reading circuit according to the embodiment of the present application;

FIG. 10 is a schematic diagram of another exemplary embodiment of an image reading circuit;

FIG. 11 is a schematic diagram of another exemplary structure of an image reading circuit according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another control timing sequence of an image reading circuit according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a time-of-flight sensor according to an embodiment of the present application;

FIG. 14 is a schematic view of an image capturing optical system according to an embodiment of the present disclosure;

fig. 15 is a schematic diagram of a terminal device in an embodiment of the present application;

fig. 16 is a schematic diagram of another terminal device in the embodiment of the present application;

fig. 17 is a flowchart illustrating an embodiment of an image reading method according to an embodiment of the present application.

Detailed Description

The embodiment of the application provides an image reading circuit, an image sensor and a terminal device, which improve the quality of an output image and improve the dynamic range of pixels.

Referring to fig. 1, fig. 1 is a schematic diagram of a system structure of an image reading circuit according to an embodiment of the present disclosure. In the embodiment of the present application, a circuit included in an image sensor (CIS) is referred to as an image reading circuit 100, and the image reading circuit 100 mainly includes two parts: a light-sensing portion and a non-light-sensing portion (the non-light-sensing portion is also referred to as a data reading portion). The light sensing portion is composed of a pixel array, and a basic unit included in the pixel array is referred to as a pixel (or referred to as a photoelectric conversion circuit 101), and each pixel includes a photosensor and other circuits. The photosensors in the pixels convert received photons (phototons) into photoelectrons (photoelectrons) using the photoelectric effect. Other circuits in the pixel (except the photosensor) convert and store the photoelectrons, resulting in corresponding electrical signals. The data readout section (including the column readout circuit) quantizes and processes the electric signal. In addition, the image sensor includes a pixel control circuit for controlling exposure of the photo sensor in the image reading circuit, for example, controlling the photo sensor to make 1/100 seconds of exposure.

Taking any one of the pixels in the pixel array of fig. 1 as an example, the pixel (the photoelectric conversion circuit 101) includes a photosensor for receiving photons and outputting photoelectrons and a reset circuit for outputting a reset voltage. Other circuits (other than the photosensor) included in the photoelectric conversion circuit 101 are used to collect the pixel voltage and the reset voltage. The column readout circuit electrically connected to the photoelectric conversion circuit 101 includes a determination circuit 102 (determination circuit) and a first circuit 103, wherein the determination circuit 102 is electrically connected to the first circuit 103. The judging circuit 102 is configured to determine a first sampling time according to the pixel voltage, where the first sampling time is inversely related to the pixel voltage. The determining circuit 102 is further configured to determine a control timing sequence of a correlated multiple sampling circuit (CMS circuit) in the first circuit 103 according to the first sampling number, so that the first circuit 103 performs correlated multiple sampling on the pixel voltage and the reset voltage according to the control timing sequence to determine a first voltage, where the first voltage is a voltage generated by photoelectrons, and a voltage value of the first voltage is positively correlated with illumination intensity (illumination).

Hereinafter, an image reading circuit according to an embodiment of the present application will be described in detail with reference to the drawings.

Referring to fig. 2, fig. 2 is a schematic diagram of a structure of an image reading circuit according to an embodiment of the present disclosure. The image reading circuit 100 according to the embodiment of the present application includes a photoelectric conversion circuit 101, a determination circuit 102, and a first circuit 103. Next, each part of the image reading circuit 100 is described separately.

(1) And a photoelectric conversion circuit 101.

The photoelectric conversion circuit 101 is specifically used to output a pixel voltage and a reset voltage to the other parts of the image reading circuit 100. The photoelectric conversion circuit 101 includes a photoelectric sensor 1011, a reset circuit 1012, a first transistor 1013, a second transistor 1014, a first capacitor 1015, a second capacitor 1016, a first source follower 1017, and a second source follower 1018, the photoelectric sensor 1011 is electrically connected to the first source follower 1017, the reset circuit 1012 is electrically connected to the first source follower 1017, the first source follower 1017 is electrically connected to the first transistor 1013, the first transistor 1013 is electrically connected to the second capacitor 1016, the first transistor 1013 is electrically connected to the second transistor 1014, the second transistor 1014 is electrically connected to the first capacitor 1015, the second capacitor 1016 is electrically connected to the second source follower 1018, and the second transistor 1014 is electrically connected to the second source follower 1018.

The photoelectric sensor 1011 converts received photons into photoelectrons by using a photoelectric effect, and optionally, the execution of the photoelectric sensor 1011 may be a photodiode (photodiode), a phototriode (phototriode), or other components capable of converting photons into photoelectrons, which is not limited herein. Optionally, the photosensor 1011 includes photodiode D and M5 transistors. The photodiode D is used for receiving photons and converting the photons into photoelectrons, the drain (or source) of the M5 transistor is electrically connected with the photodiode D, the source (or drain) of the M5 transistor is electrically connected with the first source follower 1017, the gate of the M5 transistor is used for receiving a control signal (TX) which is used for controlling the connection path between the photodiode D and the first source follower 1017 to be turned on or off. When the control signal (TX) controls the M5 transistor to be turned on, the photodiode D outputs photoelectrons to the first source follower 1017 through the M5 transistor.

The reset circuit 1012 is configured to apply a reset Voltage (VRST) to the photoelectric conversion circuit 101 before each exposure is completed, so that the first source follower 1017 electrically connected to the reset circuit 1012 is reset to a fixed voltage value (voltage value of the reset voltage), and photoelectrons received by the previous exposure are eliminated, thereby preventing the previous image from affecting the next image. Optionally, the reset circuit 1012 may be implemented by a reset circuit (reset circuit) formed by one or more components, or may be implemented by one or more reset transistors or reset transistors, which is not limited herein. For example, the reset circuit 1012 is an M6 transistor, the gate of the M6 transistor is used for receiving a control signal (RST) for controlling the M6 transistor to output a reset voltage, and the source or drain of the M6 transistor is electrically connected to the first source follower 1017. The source or drain of the M6 transistor outputs a reset voltage VRST.

First source follower 1017, source follower (source follower) has a function of impedance transformation (impedance transformer). In this embodiment, the first source follower 1017 is used to isolate the current between the photosensor 1011 and the first transistor 1013, and the first source follower is used to isolate the current between the reset circuit 1012 and the first transistor 1013. Specifically, the gate of the first source follower 1017 is electrically connected to the photosensor 1011, and the gate of the first source follower 1017 is electrically connected to the drain or the source of the reset circuit 1012. Optionally, the first source follower 1017 is composed of two transistors, i.e., an M3 transistor and an M4 transistor, wherein the M3 transistor serves as a source follower, the M4 transistor serves as a tail current transistor, and a drain (or source) of the M3 transistor and a drain (or source) of the M4 transistor are electrically connected, so that the M3 transistor and the M4 transistor form the first source follower 1017. The gate of the M3 transistor is electrically connected to the photosensor 1011 and the reset circuit 1012, and this connection point is also referred to as a Floating Diffusion (FD) point. The first source follower 1017 buffers the voltage at the FD point. The gate of the M4 transistor is used to receive a control signal (VBIAS) for controlling the first source follower 1017 to turn on or off, and when VBIAS controls the first source follower 1017 to turn off, the first source follower 1017 isolates the current between the photosensor 1011 and the reset circuit 1012, and the first transistor 1013. When VBIAS controls the first source follower 1017 to be turned on, the first source follower 1017 buffers the voltage output from the photosensor 1011 and the reset circuit 1012, and outputs the buffered voltage to the first transistor 1013.

The first transistor 1013 is electrically connected to the first source follower 1017, the first transistor 1013 is electrically connected to the second capacitor 1016, and the first transistor 1013 is electrically connected to the second transistor 1014. The first transistor 1013 is used to control the on and off of a circuit between the first source follower 1017 (i.e., the photosensor 1011 and the reset circuit 1012) and the second capacitor 1016 and the second transistor 1014. Alternatively, the first transistor 1013 may be composed of an M1 transistor, a source (or drain) of the M1 transistor being electrically connected to the first source follower 1017, and a drain (or source) of the M1 transistor being electrically connected to the second transistor 1014 and the second capacitor 1016. The gate of the M1 transistor is used to receive a control signal (SS) that controls the M1 transistor to turn on or off.

The second transistor 1014 is electrically connected to the first transistor 1013, the second transistor 1014 is electrically connected to the first capacitor 1015, and the second transistor 1014 is electrically connected to the second source follower 1018. The second transistor 1014 is used to control the connection path between the first transistor 1013 and the first capacitor 1015 to be turned on or off. Therefore, the first transistor 1013 and the second transistor 1014 control the connection path between the first source follower 1017 (i.e., the photosensor 1011 and the reset circuit 1012) and the first capacitor 1015 to be turned on or off. Alternatively, the second transistor 1014 may be composed of an M2 transistor, a source (or drain) of the M2 transistor being electrically connected to the first transistor 1013, and a drain (or source) of the M2 transistor being electrically connected to the first capacitor 1015. The gate of the M2 transistor is used to receive a control Signal (SR) for controlling the M2 transistor to turn on or off.

Specifically, how the first transistor 1013, the second transistor 1014, the first capacitor 1015, and the second capacitor 1016 collect the pixel voltage and the reset voltage is described below. First, the reset circuit 1012 outputs a reset voltage, the first transistor 1013 and the second transistor 1014 are in a conductive state, and the first capacitor 1015 and the second capacitor 1016 collect the reset voltage; next, the photo-electric sensor 1011 outputs photoelectrons, and at this time, the first transistor 1013 is in an on state, and the second transistor 1014 is in an off state, so that the reset voltage is maintained on the first capacitor 1015, and the second capacitor 1016 further collects the photoelectrons output by the photo-electric sensor 1011 on the basis of the electrons corresponding to the reset voltage, thereby completing the collection of the pixel voltage.

(2) And a judgment circuit 102.

The determination circuit 102 is specifically configured to determine, from the pixel voltage output by the photoelectric conversion circuit 101, the number of sampling times of the pixel voltage and the reset voltage by the correlated multi-sampling circuit 1031, which is referred to as a first sampling time. The determining circuit 102 includes a threshold voltage generator 1021, a first voltage comparator 1022 and a multi-sampling time selection circuit 1023, wherein the first voltage comparator 1022 is electrically connected to the second source follower 1018 of the photoelectric conversion circuit 101, the first voltage comparator 1022 is electrically connected to the threshold voltage generator 1021, the first voltage comparator 1022 is electrically connected to the multi-sampling time selection circuit 1023, and the multi-sampling time selection circuit 1023 is electrically connected to the related multi-sampling circuit 1031.

The threshold voltage generation circuit 1021 is used to generate one or more first threshold voltages, which are output to the first voltage comparator 1022.

The first voltage comparator 1022 determines a first voltage comparison result by comparing the first threshold voltage with the pixel voltage from the photoelectric conversion circuit 101. For example, the first threshold voltage generated by the threshold voltage generating circuit 1021 includes 0.25 volts (V), 0.5V, and 0.8V. The pixel voltage from the photoelectric conversion circuit 101 is 0.45V. The first voltage comparator 1022 first compares 0.25V (first threshold voltage) with 0.45V (pixel voltage), and outputs a voltage comparison result of 1 (i.e., the pixel voltage is greater than the first threshold voltage). Then, 0.5V (first threshold voltage) is compared with 0.45V (pixel voltage), and the output voltage comparison result is 0 (i.e., the pixel voltage is less than the first threshold voltage). The voltage comparison results are collectively referred to as first voltage comparison results. The first voltage comparator 1022 presets a plurality of voltage intervals for determining the voltage interval corresponding to the pixel voltage, and each voltage interval presets a corresponding sampling number. The first voltage comparator 1022 determines a voltage interval in which the pixel voltage is located according to the first voltage comparison result. The preset voltage intervals in the first voltage comparator 1022 are respectively: the first voltage interval is 0V-0.25V; the second voltage interval is 0.25V-0.5V; the third voltage interval is 0.5V-0.8V; the fourth voltage interval is 0.8V-1.5V. Accordingly, the first voltage comparator 1022 determines that the pixel voltage is in the second voltage interval. The first voltage comparator 1022 outputs the first voltage comparison result to the multi-sampling-number selection circuit 1023.

The multiple sampling times selecting circuit 1023 presets the sampling times corresponding to each voltage interval, and the multiple sampling times selecting circuit 1023 may determine a first sampling time according to the first voltage comparison result and determine a control sequence (control sequence) of the related multiple sampling circuit 1003 corresponding to the first sampling time. The multiple sampling count selection circuit 1023 is electrically connected to the relevant multiple sampling circuit 1031, and after the multiple sampling count selection circuit 1023 determines the control timing, the control timing is allocated to the relevant multiple sampling circuit 1031. For example: the first voltage interval is 0V-0.25V, and the corresponding first sampling times are 6; the second voltage interval is 0.25V-0.5V, and the corresponding first sampling times are 3; the third voltage interval is 0.5V-0.8V, and the corresponding first sampling frequency is 2; the fourth voltage interval is 0.8V-1.5V, and the corresponding first sampling times are 1. The first voltage comparator 1022 determines that the first voltage comparison result is: the voltage interval in which the pixel voltage is 0.25V is the second voltage interval. The multiple sampling number selection circuit determines that the first sampling number corresponding to the pixel voltage is 3, determines the control timing of the relevant multiple sampling circuit 1031 corresponding to the first sampling number, and configures the control timing to the relevant multiple sampling circuit 1031.

(3) And a first circuit 103.

The first circuit 103 includes a correlation multi-sampling circuit 1031, a first analog-to-digital converter 1032(ADC), and a pixel processor 1033(pixel processor), wherein the correlation multi-sampling circuit 1031 is electrically connected to the determination circuit 102, the correlation multi-sampling circuit 1031 is electrically connected to the first analog-to-digital converter 1032, the correlation multi-sampling circuit 1031 is electrically connected to the photoelectric conversion circuit 101, the first analog-to-digital converter 1032 is electrically connected to the pixel processor 1033, and the pixel processor 1033 is electrically connected to the determination circuit 102.

The correlated multisampling circuit 1031 is specifically configured to perform correlated multisampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit 101 according to the first sampling number output by the determination circuit 102, and output a second voltage to the first analog-to-digital converter 1032, where the second voltage is an accumulated sum of first voltages, and the first voltages are voltages generated by photoelectrons. The correlated multisampling circuit 1031 is electrically connected to the first analog-to-digital converter 1032. The correlated multi-sampling circuit 1031 includes a circuit including one or more switches and one or more capacitors, and the correlated multi-sampling circuit 1031 is configured to perform correlated multi-sampling on the pixel voltage and the reset voltage according to the control timing configured by the multi-sampling number selection circuit 1023. Specifically, when the first sampling number is 1, the correlated multi-sampling circuit 1031 performs sampling operation on the pixel voltage and the reset voltage 1 time each; when the first sampling number of times is 2, the correlated multi-sampling circuit 1031 performs sampling operation on the pixel voltage and the reset voltage 1 time each, repeats the previous sampling operation, and so on.

A first analog-to-digital converter 1032 is electrically connected to the pixel processor 1033, and the first analog-to-digital converter 1032 is electrically connected to the associated multi-sampling circuit 1031. An analog-to-digital converter (ADC) generally refers to an electronic component that converts an analog signal (voltage) into a digital signal (digital code). In this embodiment, the first analog-to-digital converter 1032 is electrically connected to the correlated multi-sampling circuit 1031, and the first analog-to-digital converter 1032 is configured to convert the electrical signal (voltage) output by the correlated multi-sampling circuit 1031 into a digital code (digital encoding). The digital code is a binary code used by computers, such as "0101001", to indicate the magnitude of the signal. The first analog-to-digital converter 1032 converts the analog signal such as the voltage into a digital code for processing by the subsequent pixel processor 1033.

Optionally, the first correlated multi-sampling circuit 1031 may perform correlated multi-sampling operation on the reset voltage on the basis of the pixel voltage after performing correlated multi-sampling operation on the pixel voltage; second, after the pixel voltage is subjected to the correlated multi-sampling operation, the accumulated sum of the pixel voltage is output to the first analog-to-digital converter, and the correlated multi-sampling circuit 1031 performs the reset operation, and then performs the correlated multi-sampling operation on the reset voltage output by the photoelectric conversion circuit 101. The description is as follows.

Firstly, the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the pixel voltage and the reset voltage according to a control timing sequence to obtain a second voltage, where the second voltage is an accumulated sum of voltage values of the pixel voltage and the reset voltage after the correlated multi-sampling, the control timing sequence is determined by the judgment circuit 102 according to a first sampling frequency, and the second voltage is a product of the first voltage and the first sampling frequency; secondly, the first analog-to-digital converter 1032 converts the second voltage into a second digital code; again, since the pixel processor 1033 is electrically connected to the multi-sampling number selection circuit 1023, the pixel processor 1033 determines a first digital code, which is a digital code of the first voltage, according to the first sampling number from the multi-sampling number selection circuit 1023 and the second digital code from the first analog-to-digital converter 1032.

Second, firstly, the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the pixel voltage by the first sampling number of times, and outputs a first pixel voltage to the first analog-to-digital converter 1032, where the first pixel voltage is an accumulated sum of the pixel voltages of the correlated multi-sampling circuit 1031 that perform correlated multi-sampling on the pixel voltage by the first sampling number of times. The first analog-to-digital converter 1032 converts the first pixel voltage into a third digital code; next, the correlated multi-sampling circuit 1031 performs a reset operation to eliminate electrons remaining after the previous correlated multi-sampling of the pixel voltage. Then, the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the reset voltage for the first sampling number of times, and outputs a first reset voltage to the first analog-to-digital converter 1032, where the first reset voltage is an accumulated sum of the reset voltages of the correlated multi-sampling circuit 1031 after the reset voltage is subjected to correlated multi-sampling for the first sampling number of times. A first analog-to-digital converter 1032 converting the first reset voltage into a fourth digital code; thirdly, the pixel processor 1033 determines a second digital code according to the third digital code and the fourth digital code, where the second digital code is a digital code corresponding to a second voltage, and the second voltage is an accumulated sum of voltage values of the pixel voltage and the reset voltage after being subjected to correlated multi-sampling; the pixel processor 1033 determines a first digital code based on the second digital code and the first sampling number, the first digital code being a digital code of the first voltage.

The pixel processor 1033 is specifically configured to process the digital code output by the first analog-to-digital converter 1032 to determine a first digital code, which is a digital code of a first voltage, which is a voltage generated by photoelectrons. Optionally, the pixel processor 1033 may also perform post-processing such as filtering on the first digital code (digital signal).

In an embodiment of the present application, an image reading circuit includes a photoelectric conversion circuit, a determination circuit, and a first circuit, where the photoelectric conversion circuit is specifically configured to output a pixel voltage and a reset voltage to other parts of the image reading circuit; the judgment circuit is specifically used for determining the sampling times of the pixel voltage and the reset voltage by the first circuit according to the pixel voltage output by the photoelectric conversion circuit, wherein the sampling times are called as first sampling times; the first circuit is specifically configured to perform correlated multi-sampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit according to the first sampling number of times output by the determination circuit to determine the first voltage. In the photoelectric conversion circuit, a first transistor is electrically connected with a second capacitor, the first transistor is electrically connected with a second transistor, the second transistor is electrically connected with the first capacitor, the first transistor is used for controlling the connection or disconnection of a connection channel between the photoelectric sensor and the second capacitor, the first transistor is used for controlling the connection or disconnection of a connection channel between the reset circuit and the second transistor, and the second transistor is used for controlling the connection or disconnection of a connection channel between the first capacitor and the first transistor. Through the photoelectric conversion circuit, the first capacitor collects the reset voltage under the common control of the first transistor and the second transistor, and the second capacitor collects the pixel voltage under the control of the first transistor, so that the photoelectric conversion circuit can output the pixel voltage to the judgment circuit (and the first circuit) firstly, and the judgment circuit determines the first sampling times according to the pixel voltage, wherein the pixel voltage is positively correlated with the illumination intensity, and the first sampling times is negatively correlated with the pixel voltage. The first circuit comprises a correlation multi-sampling circuit, a first analog-to-digital converter and a pixel processor, wherein the correlation multi-sampling circuit performs correlation multi-sampling operation on pixel voltage and reset voltage output by the photoelectric conversion circuit according to a first sampling time, the first analog-to-digital converter converts the voltage output by the correlation multi-sampling circuit and determines a corresponding digital code, and the pixel processor processes the digital code output by the first analog-to-digital converter according to the first sampling time to determine a first digital code corresponding to a first voltage, wherein the first voltage is the voltage generated by photoelectrons. Because the sampling times (first sampling times) of the pixel voltage by the related multi-sampling circuit are determined by the voltage value of the pixel voltage, the pixel voltage output by the photoelectric conversion circuit is also higher in a scene with higher light intensity, and the judgment circuit determines the lower first sampling times according to the higher pixel voltage, so that the voltage output by the related multi-sampling circuit is prevented from exceeding the quantization range of the first analog-to-digital converter, and the image quality output by the image reading circuit is improved. And under the scene of lower light intensity, the pixel voltage output by the photoelectric conversion circuit is also lower, and the judgment circuit determines higher first sampling times according to the lower pixel voltage, so that the noise of an output image under a dark light environment is reduced, the quality of the output image is improved, and the dynamic range of pixels is improved.

The photoelectric conversion circuit 101 provided by the embodiment of the present application can be applied to circuits with various topologies. For example, referring to fig. 3 on the basis of the embodiment corresponding to fig. 2, fig. 3 is a schematic structural diagram of a photoelectric conversion circuit according to an embodiment of the present disclosure. The photoelectric conversion circuit 101 provided in the embodiment of the present application includes an M1 transistor, an M2 transistor, an M3 transistor, an M4 transistor, an M5 transistor, an M6 transistor, an M7 transistor, an M8 transistor, a C1 capacitor, a C2 capacitor, and a photodiode D. For convenience of understanding, please refer to fig. 4 on the basis of fig. 3, and fig. 4 is a control timing diagram of the photoelectric conversion circuit according to an embodiment of the present disclosure. The control timing shown in fig. 4 is the control timing of the photoelectric conversion circuit 101 shown in fig. 3.

One end of the photodiode D is grounded, the other end of the photodiode D is electrically connected with the M5 transistor, the photodiode D is used for receiving photons and converting the photons into photoelectron output, and the photodiode D forms a photoelectric sensor 1011; the source and the drain of the M5 transistor are electrically connected with the M3 transistor and the photodiode D respectively, and the gate of the M5 transistor is used for receiving a control signal (TX). The control signal (TX) is used to control the connection path between the M5 transistors to be turned on or off, thereby controlling the photoelectrons output by the photodiode D. When the control signal (TX) is at a high level, the M5 transistor is turned on, and photoelectrons output by the photodiode D can flow through the M5 transistor and be transferred to the FD point, indicating that exposure is started; when the control signal (TX) is at a low level, the M5 transistor is turned off, the transfer path of photoelectrons is cut off, and photoelectrons generated by the photodiode D are no longer collected by the FD point, indicating that the exposure is finished. When the photoelectrons generated by the photodiode D are transferred to the FD point, a voltage is cumulatively formed at the FD point. C in FIG. 3 _FD Parasitic capacitance, C, representing FD Point _FD The magnitude of the capacitance determines the Conversion Gain (CG) of the photoelectrons to voltage.

The M6 transistor constitutes a reset circuit 1012, a source (or drain) of the M6 transistor is electrically connected to an FD point and an input of a reset Voltage (VRST), respectively, a voltage output to the FD point by the M6 transistor is the reset Voltage (VRST), and a gate of the M6 transistor is used to receive a control signal (RST). The control signal (RST) is used to control the connection path between the M6 transistors to be turned on or off, thereby controlling the reset Voltage (VRST). When the control signal (RST) is at a high level, the M6 transistor is turned on, and the reset Voltage (VRST) is output to the FD point via the M6 transistor, so that the voltage of the FD point is reset to VRST, eliminating the photoelectrons collected at the last exposure; when the control signal (RST) is at a low level, the M6 transistor turns off and the reset Voltage (VRST) no longer affects the FD point.

The M3 transistor is a source follower transistor, the M4 transistor is a tail current transistor, the M3 transistor and the M4 transistor form a first source follower 1017, wherein a gate of the M3 transistor is electrically connected to an FD point, a source and a drain of the M3 transistor are electrically connected to a power supply Voltage (VDD) and a source (or a drain) of the M4 transistor, respectively, the other end of the drain (or the source) of the M4 transistor is grounded, and a gate of the M4 transistor is connected to a bias current (IBIAS). The M3 transistor and the M4 transistor together form a first source follower 1017 for separating the FD point from the subsequent capacitors (C1 capacitor and C2 capacitor) so that the FD point and the subsequent capacitors (C1 capacitor and C2 capacitor) do not interfere with each other, the photoelectric conversion circuit 101 may use capacitors (C1 capacitor and C2 capacitor) with large capacitance values to reduce the switching thermal noise (KT/C noise) of the capacitors, and the C of the FD point may be reduced as much as possible _FD The capacitance of the parasitic capacitor further increases the conversion gain. In the photoelectric conversion circuit 101, on the premise that the photodiode D receives the same illumination intensity, the conversion gain is increased to increase the generated pixel voltage, thereby increasing the signal to noise ratio (SNR) of the image sensor using the photoelectric conversion circuit 101.

The M1 transistor constitutes a first transistor 1013, the M1 transistor has a source (or drain) electrically connected to the first source follower 1017 (the M3 transistor and the M4 transistor), the M1 transistor has a drain (or source) electrically connected to the M2 transistor, the C2 capacitor and the M7 transistor, and the M1 transistor has a gate for receiving a control signal (SS). The control signal (SS) is used to control the connection path between the M1 transistors to be turned on or off. When the control signal (SS) is at a high level, the M1 transistor is turned on, and the voltage from the first source follower 1017 is input to the subsequent other components (the M2 transistor, the C2 capacitor, and the M7 transistor) via the M1 transistor; when the control signal (SS) is at a low level, the M1 transistor is turned off.

The M2 transistor forms a second transistor 1014, the source or the gate of the M2 transistor is electrically connected with the M1 transistor, the drain (or the source) of the M2 transistor is electrically connected with the C1 capacitor, and the gate of the M2 transistor is used for receiving a control Signal (SR) which is used for controlling the connection path between the M2 transistors to be switched on or off. When the control Signal (SR) is at a high level, the M2 transistor is turned on, and the voltage from the M1 transistor is input to the C1 capacitor via the M2 transistor; when the control Signal (SR) is at a low level, the M2 transistor is turned off.

One end of the C1 capacitor is electrically connected with the source (or drain) of the M2 transistor, the other end of the C1 capacitor is grounded, the C1 capacitor forms a first capacitor 1015, and the C1 capacitor is used for collecting reset voltage.

One end of the C2 capacitor is electrically connected with the grid of the M7 transistor, the other end of the C2 capacitor is grounded, the C2 capacitor forms a second capacitor 1016, and the C2 capacitor is used for collecting pixel voltage.

The M7 transistor forms a second source follower 1018 in conjunction with a tail current (not shown), the M7 transistor is similar to the M3 transistor, the source (or drain) of the M7 transistor receives a supply Voltage (VDD), and the drain (or source) of the M7 transistor is electrically connected to the M8 transistor. The M7 transistor is used for amplifying the reset voltage output by the C1 capacitor and the pixel voltage output by the C2 capacitor.

A source (or a drain) of the M8 transistor is electrically connected with the M7 transistor, a drain of the M8 transistor is electrically connected with other circuits (such as the judgment circuit 102 and the associated multi-sampling circuit 1031) subsequent to the source, a gate of the M8 transistor is used for receiving a control Signal (SEL) which is used for controlling the connection path between the M8 transistors to be turned on or off, when the control Signal (SEL) is at a high level, the M8 transistor is turned on, and the pixel voltage or the reset voltage is output to other circuits through the M7 transistor and the M8 transistor; when the control Signal (SEL) is at a low level, the M8 transistor is turned off.

The control sequence shown in fig. 4 will be described in detail below. Specifically, the control sequence shown in fig. 4 is a control sequence of the photoelectric conversion circuit 101 when the image sensor (to which the photoelectric conversion circuit 101 shown in fig. 3 is applied) proposed in the present application performs exposure using the global shutter mode. The control sequence shown in fig. 4 is only an exemplary one, and there is a different control sequence depending on the composition of each element of the actual photoelectric conversion circuit 101, and the control sequence is not limited here.

When an image sensor performs exposure, the operation time of a pixel is mainly divided into a Global shutter (Global shutter) period and a Column Readout (Column Readout) period.

In the global exposure period, first, before the pixel is exposed, the RST signal is controlled from a low level to a high level, and the M6 transistor is controlled to be turned on, so that the FD point is reset. At the same time, the TX signal is controlled from low to high, resetting the photodiode D. The M6 transistor is equivalent to a resistor during reset, and the FD point voltage will rise slowly and eventually be reset to VRST. After a preset reset time, for example, 100 ns-5 ms, the RST signal and the TX signal are controlled from high to low, the M6 transistor is turned off, and the FD point is maintained at the VRST voltage.

Since the transistor operating in the on state has a thermal noise current, the thermal noise current generated by the M6 transistor forms a thermal noise voltage, also referred to as KT/C noise, at the FD point. When the M6 transistor is pulled low, this thermal noise voltage also remains at the FD point, also referred to as reset noise. Due to the randomness of the noise, the noise on the FD point is different during each reset, that is, after each reset, the voltage of the FD point has a slight difference and appears as the noise on the image. According to the formula of KT/C noise, the smaller the FD point capacitance, the larger the thermal noise voltage. As the pixel size is reduced, the FD point capacitance is also reduced, and thus the reset noise is increased, and it is necessary to remove the reset noise to improve the image quality. The specific implementation method is that the reset voltage is stored together with the reset noise, and is read out at a certain subsequent time point, and is subtracted from the pixel voltage, so that the noise is eliminated. In this embodiment, the reset voltage at the FD point is transmitted to one end of the M1 transistor through the first source follower 1017 formed of the M3 transistor and the M4 transistor. Meanwhile, when the SR signal and the SS signal are controlled from low level to high level, the transistors M1 and M2 are both turned on, and the voltage of the upper plate of the capacitor C1 follows the voltage change of the FD point. When the pixel reset is completed, the SR signal is controlled from high level to low level, and the reset voltage and the reset noise thereof will remain on the capacitor C1, i.e. the storage of the reset voltage is completed, which is denoted by VRST. Then, the TX signal is controlled from low to high, at which time the M5 transistor is turned on, electrons generated by the photodiode D flow to the FD point through the M5 transistor, and the FD point voltage drops because the electrons are negatively charged. The voltage at the FD point is decreased by an amount equal to the number of electrons generated by the photodiode D multiplied by the conversion gain, which is linear with the light intensity received by the photodiode D. After the pixel exposure is finished, the TX signal is controlled to be from high level to low level, the M5 transistor is turned off, and the voltage of the FD point does not change any more. After the voltage is stabilized, the SS signal is controlled from high level to low level, and the pixel voltage is retained on the capacitor C2, i.e. the storage of the pixel voltage is completed, which is denoted by VSIG. The actual voltage value generated by the photoelectrons is the difference between the reset voltage and the pixel voltage, i.e., VRST-VSIG.

In the column readout period, the column readout circuit (including the judgment circuit 102 and the first circuit 103 proposed in the present application) completes readout and quantization of the electric signal within the pixel. First, the SEL signal is controlled from low to high, and at this time, the M7 transistor and the second source follower 1018 formed by the tail current are formed, and the voltage output by the photoelectric conversion circuit 101 follows the change of the gate voltage of the M7 transistor. Since the upper plate of the capacitor C2 is directly connected to the gate of the M7 transistor, and the upper plate voltage is the sampled pixel voltage at this time, the pixel voltage VSIG is read out. After the column readout circuit completes sampling of the pixel voltage VSIG, the SR signal is controlled from low to high, at which time the M2 transistor is turned on and the C1 capacitor and the C2 capacitor form a charge share. Since the upper plate voltage of the capacitor C2 is the pixel voltage, the upper plate voltage of the capacitor C1 is the reset voltage. The pixel voltage collected by the capacitor C1 is the summation of the voltages generated by the photoelectrons based on the reset voltage, so that the first voltage (voltage corresponding to the photoelectrons) obtained by subtracting the reset voltage from the final pixel voltage can successfully eliminate the reset noise.

The judgment circuit 102 and the related multi-sampling circuit 1031 provided by the embodiment of the application can be applied to circuits with various topological structures. For example, referring to fig. 5 on the basis of the embodiments corresponding to fig. 2 to fig. 3, fig. 5 is a schematic structural diagram of an image reading circuit according to an embodiment of the present disclosure. The image reading circuit 100 according to the embodiment of the present application includes a photoelectric conversion circuit 101 (other parts of the photoelectric conversion circuit 101 are not shown in fig. 5), a determination circuit 102, and a first circuit 103, where the determination circuit 102 includes a threshold voltage generation circuit 1021, a first voltage comparator 1022, a multi-sampling number selection circuit 1023, and a S5 switch therein, the first circuit 103 includes a correlated multi-sampling circuit 1031, a first analog-to-digital converter 1032, and a pixel processor 1033 (not shown in fig. 5), and the correlated multi-sampling circuit 1031 includes a S1 switch, a S2 switch, a S3 switch, a S4 switch, a Cin capacitor, a Cf capacitor, a switch AZ, an operational Amplifier (AMP), and an SH switch.

Specifically, one end of the S1 switch in the relevant multi-sampling circuit 1031 is electrically connected to the source (or drain) of the M8 transistor, and the other end of the S1 switch is electrically connected to the Cin capacitor. The S3 switch and the S4 switch are connected in parallel at two ends of the Cin capacitor, and the other ends of the S3 switch and the S4 switch are connected with a reference voltage (Vcom) and are electrically connected with the input end of the operational amplifier. One end of the Cin capacitor electrically connected with the S4 switch is electrically connected with the S2 switch, and the other end of the S2 switch is electrically connected with the input end of the operational amplifier. The output of the S2 switch may be electrically connected to the non-inverting input terminal of the operational amplifier (in this case, the outputs of the S3 switch and the S4 switch are electrically connected to the inverting input terminal of the operational amplifier), or may be electrically connected to the inverting input terminal of the operational amplifier (in this case, the outputs of the S3 switch and the S4 switch are electrically connected to the non-inverting input terminal of the operational amplifier), and is not limited herein. The operational amplifier may specifically be: a general-purpose operational amplifier, a programmable operational amplifier, a high-resistance operational amplifier, or a low-power operational amplifier, and the like, but not limited thereto. The Cf capacitor is connected in parallel at the two ends of the input end and the output end of the operational amplifier, and the AZ switch is connected in parallel at the two ends of the Cf capacitor. One end of the SH switch is electrically connected to the output terminal of the operational amplifier, the other end of the SH switch is electrically connected to the first analog-to-digital converter 1032, and the output terminal of the first analog-to-digital converter 1032 is electrically connected to the pixel processor 1033 (not shown in fig. 5).

An output end of the threshold voltage generation circuit 1021 in the judgment circuit 102 is electrically connected to an input end of the first voltage comparator 1022, another input end of the first voltage comparator 1022 is electrically connected to the S5 switch, optionally, the threshold voltage generation circuit 1021 is electrically connected to a non-inverting input end of the first voltage comparator 1022, and at this time, the S5 switch is electrically connected to an inverting input end of the first voltage comparator 1022; alternatively, the threshold voltage generating circuit 1021 is electrically connected to the inverting input terminal of the first voltage comparator 1022, and at this time, the switch S5 is electrically connected to the non-inverting input terminal of the first voltage comparator 1022. The other end of the S5 switch is electrically connected to the output terminal (i.e., the source or drain of the M8 transistor) of the photoelectric conversion circuit 101. The output terminal of the first voltage comparator 1022 is electrically connected to the multiple sampling number selection circuit 1023, and the output terminal of the multiple sampling number selection circuit 1023 is electrically connected to the relevant multiple sampling circuit 1031, and outputs a control timing sequence to the relevant multiple sampling circuit 1031.

For convenience of understanding, the following describes operation relationships among the components in fig. 5 with reference to fig. 6, and fig. 6 is a schematic control timing diagram of an image reading circuit according to an embodiment of the present application. First, the SEL signal is controlled from low to high, indicating that the pixel is gated on. And in a time period from t0 to t1, carrying out automatic zero setting, specifically: and controlling the AZ signal to be from low level to high level to close the AZ switch, and connecting the output of the operational amplifier with the inverting input end to form unit gain negative feedback. And two ends of the Cf capacitor are connected, and the charges stored in the last reading are reset to ensure that the next reading is not influenced. Optionally, during the auto-zero process, the inverting input terminal of the operational amplifier stores an offset value (offset) for compensating an error due to device mismatch during the production of the operational amplifier.

And after the automatic zero setting is finished, controlling the AZ signal to be switched from a high level to a low level, and switching off the AZ switch. Then, the S5 switch of the determination circuit 102 is turned on, the first voltage comparator 1022 and the photoelectric conversion circuit 101 are turned on, and the first voltage comparator 1022 samples the pixel voltage output from the M8 transistor. The threshold voltage generating circuit 1021 generates one or more first threshold voltages in a time-sharing manner, the first voltage comparator 1022 compares the first threshold voltage with the pixel voltage for multiple times, determines a first voltage comparison result, and determines a voltage range to which the pixel voltage belongs according to the first voltage comparison result.

The multi-sampling time selection circuit 1023(multi-sampling time selection) determines a first sampling time corresponding to the pixel voltage according to the first voltage comparison result. The multiple sampling number selection circuit 1023 determines a control timing of the correlated multiple sampling circuit 1031 according to the first sampling number, the control timing being used to control the correlated multiple sampling circuit 1031 to perform a correlated multiple sampling operation on the outputs (pixel voltage and reset voltage) of the photoelectric conversion circuit 101, and optionally, the correlated multiple sampling operation includes an Adaptive correlated multiple sampling (Adaptive-CMS) operation.

The correlation multi-sampling circuit 1031 samples and accumulates the pixel voltage once in a time period t1-t 2. The specific accumulation process is as follows: first, the S1 switch and the S4 switch are turned on, and the pixel voltage is sampled, at which time C _in The charge on the capacitor equals:

Q _in ₀ ＝C _in (V _com -V _SIG )；

wherein Q is _in ₀ Is C _in Charge on the capacitor, V _com Is a reference voltage (also known as common mode voltage), V _SIG Is a pixel voltage, C _in Is C _in The capacitance value of the capacitor.

When C is present _in Voltage stabilization of the capacitor (e.g., C within 10 nanoseconds _in The voltage value of the capacitor changes by less than 0.1 mv, which is only exemplified here, and the determination criterion of the actual voltage stabilization is not limited), the S1 switch and the S4 switch are turned off, and then the S2 switch and the S3 switch are turned on, at this time:

Q _total ＝Q _in ₁ +Q _f1 ＝C _in (V _- -V _com )+C _f (V _- -V _o,t2 )；

wherein Q is _total For the total charge amount, Q, of the correlated multi-sampling circuit 1031 _in ₁ The amount of charge of the capacitor Cin at time t2, Q _f1 The amount of charge of the capacitor Cf at time t2, V _- Is the voltage value of the inverting input terminal of the operational amplifier, V _com Is a reference voltage, V _o,t2 Is the voltage value at the output end of the operational amplifier (i.e. the voltage value of the lower plate of the Cf capacitor), C _in Is C _in Capacitance value of the capacitor, C _f Is C _f The capacitance value of the capacitor.

Due to the negative feedback effect of the operational amplifier, the voltages at the non-inverting input and the inverting input of the operational amplifier will tend to be equal, that is: v _- ＝V ₊ ＝V _com . Substituting the formula into the formula:

Q _total ＝C _in (V _com -V _com )+C _f (V _com -V _o,t2 )＝C _f (V _com -V _o,t2 )；

according to the principle of conservation of charge, Q _total ＝Q _in ₀ +Q _f0 ＝Q _in ₀ The following can be obtained:

C _in (V _com -V _SIG )＝C _f (V _com -V _o,t2 )；

thus, at time t2, the output voltage of the operational amplifier equals:

V _o,t2 ＝V _com -C _in /C _f (V _com -V _SIG )；

note that C _in The capacitance represents the input sampling capacitance, C _f The capacitance represents the feedback capacitance, the ratio C _in /C _f The gain of correlated multisampling circuit 1031 may be determined. With a gain of 1 (i.e. C) _in /C _f 1) as an example, let C _in ＝C _f The output voltage of the operational amplifier at time t2 is:

V _o,t2 ＝V _com +(V _SIG -V _com )；

the time period t 2-t 3 represents that the correlated multi-sampling circuit 1031 repeats the process of t1-t2, repeatedly sampling and accumulating the pixel voltage. This number of repetitions is equal to the first number of samples (M), e.g., 2, and then one more sample is needed on a t1-t2 basis. Similarly, first, the S1 switch and the S4 switch are turned on, and the pixel voltage is sampled, at which time C _in The charge on the capacitor equals: q _in ₂ ＝C _in (V _com -V _SIG ). Note that at time t2, C _f The presence of a charge on the capacitor: q _f2 ＝C _f (V _com -V _SIG ). The total charge of correlated multisampling circuit 1031 is therefore:

Q _total ＝Q _in ₂ +Q _f2 ＝C _in (V _com -V _SIG )+C _f (V _com -V _SIG )；

similarly, when C _in After the voltage of the capacitor is stabilized, the S1 switch and the S4 switch are turned off, and then the S2 switch and the S3 switch are turned on, at this time:

Q _total ＝Q _in ₃ +Q _f3 ＝C _in (V _com -V _com )+C _f (V _com -V _o,t3 )＝C _f (V _com -V _o,t3 )；

according to the principle of conservation of charge, the following can be obtained:

C _in (V _com -V _SIG )+C _f (V _com -V _SIG )＝C _f (V _com -V _o,t3 )；

thus, at time t3, the output voltage of the operational amplifier equals:

V _o,t3 ＝V _com +2(V _SIG -V _com )；

as can be seen from the above equation, with each time the correlated multisampling circuit 1031 performs multisampling, Δ V ═ V will be superimposed on its output _SIG -V _com Amount of (a) corresponding to each time C _in The up-sampled voltage difference is transferred to the output of the operational amplifier for accumulation. It can be derived that when the first number of samples is M, at time t3, the output voltage of the operational amplifier is:

V _o,t3 ＝M(V _SIG -V _com )+V _com ；

and a time period t 3-t 4, during which the SR signal is controlled from low to high, indicating that the photoelectric conversion circuit 101 outputs the stored reset voltage, at which time the M8 transistor output voltage changes from VSIG to VRST. In the time period t 4-t 5, the correlated multi-sampling circuit 1031 performs one reset voltage sampling and subtraction operation. First, the S1 switch is turned on, at which time C _in The upper plate voltage of the capacitor is equal to VRST, and the total charge can be represented as:

Q _total ＝Q _in +Q _f ＝C _in (V _com -V _RST )+C _f (V _com -V _o,t5 )；

at time t3, the total charge on the capacitor is equal to Q _f ＝C _f (V _com -V _o,t3 ) According to the principle of charge conservation, the following can be obtained:

C _f (V _com -V _o,t3 )＝C _in (V _com -V _RST )+C _f (V _com -V _o,t5 )；

the following can be deduced: v _o,t5 ＝V _o,t3 -(V _RST -V _com )。

Then at time t5, the S1 switch and the S2 switch are both off, while the S3 switch and the S4 switch are both on, turning C on _in The charge on the capacitor is emptied. At time t 5-t 6, the correlated multi-sampling circuit 1031 repeats the process of t 4-t 5, repeating the sampling and decrementing of the reset voltage. The number of repetitions is a first number of samples (M). Similarly, assuming the first sampling number is 2, another sampling is required on the basis of t 4-t 5. First, the S1 switch and the S2 switch are turned on to make C _in The capacitor top plate voltage is equal to VRST, and the total charge can be represented as:

Q _total ＝Q _in +Q _f ＝C _in (V _com -V _RST )+C _f (V _com -V _o,t6 )；

at time t5, the total charge on the capacitor is equal to Q _f ＝C _f (V _com -V _o,t5 ) According to the principle of charge conservation, the following can be obtained:

C _f (V _com -V _o,t5 )＝C _in (V _com -V _RST )+C _f (V _com -V _o,t6 )；

then, it can be deduced that: v _o,t6 ＝V _o,t5 -(V _RST -V _com )＝V _o,t3 -2(V _RST -V _com )。

As can be seen from the above equation, with each time the correlated multisampling circuit 1031 performs multisampling, one Δ V — V will be subtracted from its output _RST -V _com Amount of (a) corresponding to each time C _in The charge on is drained to ground. It can be derived that when the first number of samples is M, at time t6, the output voltage of the operational amplifier is:

V _o,t6 ＝V _o,t3 -M(V _RST -V _com )；

according to the frontWith respect to the derivation of the time period t1-t 3, it can be seen that the output voltage of the operational amplifier is equal to V at time t3 _o,t3 ＝M(V _SIG -V _com )+V _com Substituting the formula to obtain:

V _o,t6 ＝V _com -M(V _RST -V _SIG )；

the time period t 6-t 7 indicates that the first analog-to-digital converter 1032(ADC) samples the output voltage of the operational amplifier in the correlated multi-sampling circuit 1031, and the SH switch is turned on. After time t7, the first analog-to-digital converter 1032 quantizes the voltage value after multiple sampling to obtain a corresponding digital code. From V _o,t6 By the expression (V), it can be seen that _com The reference voltage is subtracted from the voltage value output by the operational amplifier, and the difference value between the reset voltage and the pixel voltage is multiplied by the first sampling times, so that the random noise can be effectively reduced.

In the embodiment of the present application, please refer to fig. 7 for a simulation diagram of the correlated multi-sampling circuit 1031 performing correlated multi-sampling on the voltage output by the photoelectric conversion circuit 101, and fig. 7 is a simulation experiment diagram according to the embodiment of the present application. In fig. 7, Vo _ amp is the output voltage of the operational amplifier in the correlated multi-sampling circuit 1031, as can be seen from fig. 7, since the sampling times (first sampling times) of the pixel voltage (and the reset voltage) by the correlated multi-sampling circuit are determined by the voltage value of the pixel voltage, in a scene with higher light intensity, the pixel voltage output by the photoelectric conversion circuit is also higher, and the judgment circuit determines a lower first sampling time according to the higher pixel voltage, so as to avoid that the voltage output by the correlated multi-sampling circuit exceeds the quantization range of the first analog-to-digital converter; and under the scene of lower light intensity, the pixel voltage output by the photoelectric conversion circuit is also lower, and the judgment circuit determines a higher first sampling frequency according to the lower pixel voltage, wherein the sampling frequency is not limited by the full hydrazine capacity of the pixel. In both high-light-intensity and low-light-intensity scenes, Vo _ amp does not exceed the quantization range of an analog-to-digital converter (ADC), so that the noise of an output image in a dark light environment can be effectively reduced, the quality of the output image is improved, and the dynamic range of pixels is improved.

Optionally, please refer to fig. 8, fig. 8 is a schematic diagram of another structure of the image reading circuit in the embodiment of the present application. In addition to the image reading circuit shown in fig. 5, the judgment circuit 102 further includes: the circuit comprises an S6 switch, an AZ1 switch, a C3 capacitor and a C4 capacitor, wherein two ends of the C3 capacitor are respectively and electrically connected with an S5 switch and a first voltage comparator, one end of the S6 switch is electrically connected with a threshold voltage generating circuit, the other end of the S6 switch is electrically connected with one end of the C4 capacitor, and the other end of the C4 capacitor is electrically connected with the first voltage comparator. The positive phase input end and the negative phase input end of the first voltage comparator are respectively electrically connected with an AZ1 switch, and the other end of the AZ1 switch is used for connecting a reference voltage Vcom 2.

For convenience of understanding, please refer to fig. 9 corresponding to the image reading circuit shown in fig. 8, and fig. 9 is a schematic diagram of another control timing of the image reading circuit according to an embodiment of the present disclosure. Before the determination circuit 102 detects the pixel voltage (time period t0-t 1), the AZ1 signal is controlled from low level to high level, and the AZ1 switch is turned on. The S5 signal and the S6 signal are controlled to be at low level, and the S5 switch and the S6 switch are turned off, so that the first voltage comparator 1022 performs auto-zero, specifically: the reference voltage (Vcom2) is input to the non-inverting input terminal and the inverting input terminal of the first voltage comparator 1022, and if the voltages at the two terminals determined by the first voltage comparator 1022 are not the same, an error occurs in the first voltage comparator 1022, and the error is equal to the difference between the voltages. The first voltage comparator 1022 uses the voltage difference to eliminate the error, so as to improve the accuracy of the first voltage comparator.

When the photoelectric conversion circuit 101 outputs the pixel voltage (t1-t2 time period), the S5 signal and the S6 signal are controlled from a low level to a high level, the S5 switch and the S6 switch are turned on, the C3 capacitor acquires the pixel voltage, and the C4 capacitor acquires the first threshold voltage. Since the capacitor has a function of isolating direct current, the C3 capacitor and the C4 capacitor can be used to protect the first voltage comparator 1022, and the first voltage comparator 1022 can also determine the voltage value interval in which the pixel voltage is located when the lower first threshold voltage and the power supply voltage are used, so as to reduce the power consumption of the image reading circuit.

In the embodiment of the application, the first voltage comparator eliminates errors by using the voltage difference value obtained by automatic zero-adjusting measurement so as to improve the accuracy of the first voltage comparator. A capacitor is arranged between the first voltage comparator and the threshold voltage generation circuit and between the first voltage comparator and the photoelectric conversion circuit, and the first voltage comparator can determine the voltage value interval of the pixel voltage under the condition of using lower first threshold voltage and power supply voltage while protecting the first voltage comparator, so that the power consumption of the image reading circuit is reduced.

Optionally, referring to fig. 10, fig. 10 is a schematic diagram of another composition structure of the image reading circuit in the embodiment of the present application. On the basis of the image reading circuit shown in fig. 8, the determining circuit 102 may further include one or more second voltage comparators, which have similar purposes to the first voltage comparators 1022. Specifically, the determining circuit 102 further includes: the circuit comprises an S7 switch, an S8 switch, a C5 capacitor and a C6 capacitor, wherein two ends of the C5 capacitor are respectively and electrically connected with an S7 switch and a second voltage comparator, one end of the S8 switch is electrically connected with a threshold voltage generating circuit, the other end of the S8 switch is electrically connected with one end of the C6 capacitor, and the other end of the C6 capacitor is electrically connected with the second voltage comparator. The positive phase input end and the negative phase input end of the second voltage comparator are respectively electrically connected with an AZ1 switch, and the other end of the AZ1 switch is used for connecting a reference voltage Vcom 2.

Specifically, the second voltage comparator is configured to determine a second voltage comparison result according to a second threshold voltage and the pixel voltage, where the second threshold voltage is generated by the threshold voltage generation circuit; and the multi-sampling time selection circuit is also used for determining the first sampling time according to the first voltage comparison result and the second voltage comparison result.

In the embodiment of the application, one or more second voltage comparators are arranged in the judgment circuit, the judgment circuit can simultaneously compare the pixel voltage domain with a plurality of threshold voltages (second threshold voltages), and the speed of determining the voltage comparison result (second voltage comparison result) of the pixel voltage is greatly increased, so that the speed of reading the pixel image can be effectively improved.

Optionally, referring to fig. 11, fig. 11 is a schematic diagram of another structure of an image reading circuit in an embodiment of the present application. The first circuit 103 can also process voltages using a plurality of analog-to-digital converters on the basis of the image reading circuit shown in fig. 8. Specifically, the first circuit 103 further includes an SHR switch, a CSHR capacitor, an SHS switch, a CSHS capacitor, and a second analog-to-digital converter, wherein an output terminal of the operational Amplifier (AMP) is electrically connected to one end of the SHR switch and one end of the SHS switch, respectively, another end of the SHR switch is electrically connected to the CSHR capacitor and the first analog-to-digital converter, and another end of the SHS switch is electrically connected to the CSHS capacitor and the second analog-to-digital converter.

For convenience of understanding, please refer to fig. 12, which corresponds to the image reading circuit shown in fig. 11, and fig. 12 is a schematic diagram of another control timing sequence of the image reading circuit according to an embodiment of the present disclosure.

In the time period t0-t1, the determination circuit 102 in the image reading circuit 100 collects the pixel voltage and determines the first sampling number from the pixel voltage. Then, in a time period from t1 to t3, the correlated multi-sampling circuit 1031 in the first circuit 103 performs correlated multi-sampling on the pixel voltage by controlling the S1 switch, the S2 switch, the S3 switch and the S4 switch to obtain a first pixel voltage, which is similar to the description of the foregoing embodiments and will not be described herein again.

In a time period from t3 to t4, the SHS switch is turned on, the first pixel voltage (the accumulated sum of the pixel voltages) is sampled to the CSHS capacitor and output to the second analog-to-digital converter at the rear end for quantization, and the obtained digital code is called a third digital code.

In the time period t 3-t 4, an SR switch (not shown in the figure) in the photoelectric conversion circuit 101 is turned on, and the photoelectric conversion circuit 101 outputs a reset voltage to the correlated multi-sampling circuit 1031.

And in a time period from t3 to t4, after the accumulated sum of the pixel voltages is sampled to the CSHS capacitor, the SHS switch is switched off (at the moment, the SHR switch is also in a switched-off state), the AZ signal is controlled to be switched from a low level to a high level, the AZ switch is switched on, and the operational amplifier is automatically zeroed.

In the time period t 4-t 6, the control timings of the S1 switch, the S2 switch, the S3 switch, and the S4 switch are similar to those of the above switches in the time period t1-t 3, and the correlated multi-sampling circuit 1031 completes correlated multi-sampling of the reset voltage to obtain the first reset voltage.

In the time period from t6 to t7, the SHR switch is turned on, the first reset voltage (the accumulated sum of the reset voltages) is sampled to the CSHR capacitor and output to the first analog-to-digital converter at the back end for quantization, and the obtained digital code is called a fourth digital code.

Finally, the pixel processor (not shown in the figure) processes the digital codes output by the first analog-to-digital converter and the second analog-to-digital converter, specifically, the third digital code and the fourth digital code are subtracted to obtain a second digital code, the second digital code is a digital code corresponding to a second voltage, and the second voltage is a difference value between an accumulated sum of the pixel voltage after being subjected to correlated multi-sampling and an accumulated sum of the reset voltage after being subjected to correlated multi-sampling. And the pixel processor determines a first digital code according to the second digital code and the first sampling times, wherein the first digital code is a digital code corresponding to the first voltage. Specifically, the second digital code is divided by the first number of samples to obtain the first digital code.

It should be noted that, in the embodiment of the present application, the first analog-to-digital converter and the second analog-to-digital converter may be different analog-to-digital converters or may be the same analog-to-digital converter, and when the first analog-to-digital converter and the second analog-to-digital converter belong to the same analog-to-digital converter, the analog-to-digital converters respectively perform the steps performed by the first analog-to-digital converter and the second analog-to-digital converter in the embodiment, which is not limited herein.

In this embodiment, the analog-to-digital converter in the first circuit performs subtraction operation after quantizing the accumulated sum of the pixel voltages and the accumulated sum of the reset voltages into digital codes, respectively. By operating in the digital domain, systematic errors generated by the analog-to-digital converter are eliminated, so that fixed pattern errors (FPN) of the image reading circuit (and an image sensor using the image reading circuit) are improved.

Optionally, the determining circuit shown in fig. 10, the first circuit shown in fig. 11, and the photoelectric conversion circuit shown in fig. 3 may constitute another image reading circuit, and the specific connection structure and the operation manner of the image reading circuit are similar to those described in the foregoing embodiments, and are not described again here.

On the other hand, the image reading circuit described in the foregoing embodiment can be applied to an image sensor, which is a CMOS Image Sensor (CIS) manufactured by using a CMOS process. Specifically, the following description will be given taking the image sensor as a time-of-flight sensor as an example. Referring to fig. 13, fig. 13 is a schematic structural diagram of a time-of-flight sensor according to an embodiment of the present disclosure. A time-of-flight (ToF) sensor is an image sensor that detects the flight time of light emitted from a camera and reflected by an object to be measured until the light is received by the camera, and calculates the depth of the object by combining the speed of the light. The time-of-flight sensor includes a pixel array (pixel array), a column readout circuit (column readout), a post-processing circuit (post-processing), a timing controller (sequence), a modulation driver (modulation driver), and the like. The time-of-flight sensor first generates a specific modulation pulse by using a time schedule controller, and controls a pixel array by a modulation driver. Meanwhile, the other path of signal drives an external laser to emit a modulated light signal through a board-level laser driving chip, and the modulated light signal is reflected by a measured object and then focused on a pixel array of the flight time sensor through a lens. The pixels convert the received optical signals into electric signals, and the electric signals of the pixels are quantized and processed by the column reading circuit and the post-processing unit, so that the flight time of an optical path received by each pixel can be obtained. And finally, obtaining complete depth information of the object through other post-processing algorithms.

Because the time-of-flight sensor needs to actively emit the optical pulse signal, and all pixels need to receive photons at the same time according to the principle of time-of-flight detection to ensure the consistency of the pixel array, the time-of-flight sensor usually adopts an exposure mode of a global shutter. In addition, for high-speed moving objects, the global shutter mode can avoid the occurrence of serious motion artifact problems. In addition, in order to reduce the error of the actual detection depth, the chip is required to accurately quantify the received light energy and reduce noise. Therefore, low noise is also an important design requirement.

In the image reading circuit provided by the application, because the sampling times (first sampling times) of the pixel voltage by the related multi-sampling circuit are determined by the voltage value of the pixel voltage, the pixel voltage output by the photoelectric conversion circuit is also higher in a scene with higher light intensity, and the judgment circuit determines the lower first sampling times according to the higher pixel voltage, so that the voltage output by the related multi-sampling circuit is prevented from exceeding the quantization range of the first analog-to-digital converter, and the image quality output by the image reading circuit is improved. And under the scene of lower light intensity, the pixel voltage output by the photoelectric conversion circuit is also lower, and the judgment circuit determines higher first sampling times according to the lower pixel voltage, so that the noise of an output image under a dark light environment is reduced, the quality of the output image is improved, and the dynamic range of pixels is improved. When the image reading circuit provided by the application is applied to the time-of-flight sensor, the design requirement of the time-of-flight sensor can be fully met, and the output image quality of the time-of-flight sensor is improved.

On the other hand, please refer to fig. 14, fig. 14 is a schematic structural diagram of an image capturing optical system according to an embodiment of the present disclosure. In the present embodiment, the image capturing optical system 1400 includes an imaging lens group 1401, a driving device 1402, an image sensor 1403, and an image stabilizing module 1404. The image sensor 1403 includes the image reading circuit in any of the embodiments described above. The image capturing optical system 1400 focuses light by the lens group 1401 to generate an image, focuses the image by the driving device 1402, and finally forms an image on the image sensor 1403 and outputs the image as image data.

The driving device 1402 may have an auto-focus (auto-focus) function, and the driving method may use a driving system such as a Voice Coil Motor (VCM), a micro-electro-mechanical system (MEMS), a piezoelectric system (piezoelectric), and a memory metal (shape memory alloy). The driving device 1402 can make the lens group 1401 obtain a better imaging position, and can provide a clear image for the subject in the state of different object distances.

In addition, the image capturing optical system 1400 carries an image sensor 1403 with good sensitivity and low noise, such as a complementary metal-oxide-semiconductor (CMOS) sensor. The image sensor 1403 is disposed on the image surface of the lens group, so that good imaging quality of the lens group can be truly exhibited.

The image stabilization module 1404 is, for example, an accelerometer, a gyroscope, or a Hall Effect Sensor. The driving device 1402 may be used as an Optical Image Stabilization (OIS) device in combination with the image stabilization module 1404, and compensates a blurred image caused by shaking at the moment of shooting by adjusting the different axial changes of the lens group 1401, or provides an Electronic Image Stabilization (EIS) function by using an image compensation technique in image software, so as to further improve the imaging quality of dynamic and low-illumination scene shooting.

Referring to fig. 15 and fig. 16, fig. 15 is a schematic diagram of a terminal device in an embodiment of the present application, and fig. 16 is a schematic diagram of another terminal device in the embodiment of the present application. In this embodiment, the terminal device 20 is a smartphone. The terminal 20 includes an image capturing optical system 1400, a flash module 21, a focus assist module 22, an image signal processor 23(image signal processor), a user interface 24, and an image software processor 25. The terminal device 20 includes an image capturing optical system 1400 as an example, but the embodiment is not limited thereto. The terminal apparatus 20 may include a plurality of image capturing optical systems 1400, or may further include other image capturing optical systems in addition to the image capturing optical systems 1400.

When a user shoots an object (subject) through the user interface 24, the terminal device 20 utilizes the image capturing optical system 1400 to capture light, starts the flash module 21 to supplement light, performs fast focusing using the object distance information of the subject provided by the focusing auxiliary module 22, and performs image optimization processing by the image signal processor 23 to further improve the quality of an image generated by the lens assembly of the camera system. The focus aid module 22 may employ an infrared or laser focus aid system to achieve rapid focus.

The user interface 24 may employ a touch screen or a physical capture button, which is used in conjunction with the various functions of the image software processor 25 to capture and process images.

The image capturing optical system 1400 of the present application is not limited to being applied to a smart phone. The image capturing optical system 1400 can be applied to a mobile focusing system according to the requirement, and has the characteristics of excellent aberration correction and good imaging quality. For example, the image capturing optical system 1400 may be applied to three-dimensional (3D) image capturing, digital cameras, mobile devices, tablet computers, smart televisions, network monitoring devices, driving recorders, back-up developing devices, multi-lens devices, identification systems, motion sensing game machines, wearable devices, and other terminal devices in many ways. The terminal device disclosed in the embodiment is only an example for illustrating the practical application of the present application, and does not limit the application scope of the image capturing optical system of the present application.

Based on the image reading circuits of fig. 1 to fig. 11, the present application further provides an image reading method of an image reading circuit, which is applied to an image reading circuit 1400, specifically, please refer to fig. 17, and fig. 17 is a flowchart illustrating an embodiment of an image reading method in an embodiment of the present application.

Step 1701, a reset voltage is collected. The reset circuit 1012 outputs a reset voltage, the first transistor 1013 and the second transistor 1014 are in a conductive state, and the first capacitor 1015 and the second capacitor 1016 collect the reset voltage.

Step 1702, collect pixel voltages. The photo-electric sensor 1011 outputs photoelectrons, at this time, the first transistor 1013 is in an on state, and the second transistor 1014 is in an off state, so that the reset voltage is maintained on the first capacitor 1015, and the second capacitor 1016 further collects the photoelectrons output by the photo-electric sensor 1011 on the basis of electrons corresponding to the reset voltage, thereby completing the collection of the pixel voltage.

Step 1703, determining a first sampling number according to the pixel voltage. The threshold voltage generation circuit 1021 is used for generating one or more first threshold voltages, and the first threshold voltages are output to the first voltage comparator 1022. The first voltage comparator 1022 determines a first voltage comparison result by comparing the first threshold voltage with the pixel voltage from the photoelectric conversion circuit 101. The multiple sampling times selecting circuit 1023 presets the sampling times corresponding to each voltage interval, and the multiple sampling times selecting circuit 1023 may determine a first sampling time according to the first voltage comparison result and determine a control sequence (control sequence) of the related multiple sampling circuit 1003 corresponding to the first sampling time.

And step 1704, performing related multi-sampling on the pixel voltage and the reset voltage according to the first sampling times to determine a first voltage.

The correlated multi-sampling circuit 1031 is specifically configured to perform correlated multi-sampling on the pixel voltage and the reset voltage output by the photoelectric conversion circuit 101 according to the first sampling frequency output by the determining circuit 102, and output a second voltage to the first analog-to-digital converter 1032, where the second voltage is an accumulated sum of first voltages, and the first voltages are voltages generated by photoelectrons. The correlated multisampling circuit 1031 is electrically connected to the first analog-to-digital converter 1032. The correlated multi-sampling circuit 1031 includes a circuit including one or more switches and one or more capacitors, and the correlated multi-sampling circuit 1031 is configured to perform correlated multi-sampling on the pixel voltage and the reset voltage according to the control timing configured by the multi-sampling number selection circuit 1023. Specifically, when the first sampling number is 1, the correlated multi-sampling circuit 1031 performs sampling operation on the pixel voltage and the reset voltage 1 time each; when the first sampling number is 2, the correlated multi-sampling circuit 1031 performs sampling operation on the pixel voltage and the reset voltage 1 time each, repeats the previous sampling operation, and so on.

Optionally, the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the pixel voltage and the reset voltage according to a control timing sequence to obtain a second voltage, where the second voltage is an accumulated sum of voltage values of the pixel voltage and the reset voltage after the correlated multi-sampling, the control timing sequence is determined by the judgment circuit 102 according to the first sampling frequency, and the second voltage is a product of the first voltage and the first sampling frequency; secondly, the first analog-to-digital converter 1032 converts the second voltage into a second digital code; again, since the pixel processor 1033 is electrically connected to the multi-sampling number selection circuit 1023, the pixel processor 1033 determines a first digital code, which is a digital code of a first voltage, according to the first sampling number from the multi-sampling number selection circuit 1023 and a second digital code from the first analog-to-digital converter 1032.

Optionally, the correlated multi-sampling circuit 1031 outputs the first pixel voltage to the first analog-to-digital converter 1032 after the pixel voltage is subjected to correlated multi-sampling for the first sampling number of times, where the first pixel voltage is an accumulated sum of the pixel voltages after the correlated multi-sampling circuit 1031 performs correlated multi-sampling for the pixel voltage for the first sampling number of times. The first analog-to-digital converter 1032 converts the first pixel voltage into a third digital code; next, the correlated multi-sampling circuit 1031 performs a reset operation to eliminate electrons remaining after the previous correlated multi-sampling of the pixel voltage. Then, the correlated multi-sampling circuit 1031 performs correlated multi-sampling on the reset voltage by the first sampling number of times, and outputs a first reset voltage to the first analog-to-digital converter 1032, where the first reset voltage is an accumulated sum of the reset voltages of the correlated multi-sampling circuit 1031 that perform correlated multi-sampling on the reset voltage by the first sampling number of times. A first analog-to-digital converter 1032 converting the first reset voltage into a fourth digital code; thirdly, the pixel processor 1033 determines a second digital code according to the third digital code and the fourth digital code, where the second digital code is a digital code corresponding to a second voltage, and the second voltage is a difference between an accumulated sum of the pixel voltage after being subjected to the correlated multi-sampling and an accumulated sum of the reset voltage after being subjected to the correlated multi-sampling; the pixel processor 1033 determines a first digital code based on the second digital code and the first sampling number, the first digital code being a digital code of the first voltage.

In the embodiment of the application, because the sampling frequency (the first sampling frequency) of the pixel voltage by the related multi-sampling circuit is determined by the voltage value of the pixel voltage, the pixel voltage output by the photoelectric conversion circuit is also higher in a scene with higher light intensity, and the judgment circuit determines the lower first sampling frequency according to the higher pixel voltage, so that the voltage output by the related multi-sampling circuit is prevented from exceeding the quantization range of the first analog-to-digital converter, and the image quality output by the image reading circuit is improved. And under the scene of lower light intensity, the pixel voltage output by the photoelectric conversion circuit is also lower, and the judgment circuit determines higher first sampling times according to the lower pixel voltage, so that the noise of an output image under a dark light environment is reduced, the quality of the output image is improved, and the dynamic range of pixels is improved.

On the basis of the embodiment shown in fig. 17, determining the first sampling number according to the pixel voltage may include: generating a first threshold voltage; determining a first voltage comparison result according to the first threshold voltage and the pixel voltage; and determining the first sampling times according to the first voltage comparison result.

Specifically, a first voltage comparison result is determined according to a comparison between the first threshold voltage and the pixel voltage. For example, the first threshold voltages include 0.25 volts (V), 0.5V and 0.8V. The pixel voltage is 0.45V. First, 0.25V (first threshold voltage) and 0.45V (pixel voltage) are compared, and the comparison result of the output voltage is 1 (i.e. the pixel voltage is greater than the first threshold voltage). Then, 0.5V (first threshold voltage) is compared with 0.45V (pixel voltage), and the output voltage comparison result is 0 (i.e., the pixel voltage is less than the first threshold voltage). The voltage comparison results are collectively referred to as first voltage comparison results. The first voltage comparator is preset with a plurality of voltage intervals for determining the voltage intervals corresponding to the pixel voltages, and each voltage interval is preset with a corresponding sampling frequency. And determining the voltage interval of the pixel voltage according to the first voltage comparison result. The preset voltage intervals are respectively as follows: the first voltage interval is 0V-0.25V; the second voltage interval is 0.25V-0.5V; the third voltage interval is 0.5V-0.8V; the fourth voltage interval is 0.8V-1.5V. Accordingly, it is determined that the pixel voltage is in the second voltage section. And determining a first sampling number according to the voltage interval.

In the embodiment of the application, the first sampling times corresponding to the pixel voltage are determined by determining the voltage interval where the pixel voltage is located. The realization flexibility of the scheme is improved.

On the basis of the embodiment shown in fig. 17, it is also possible to include: performing correlated multi-sampling on the pixel voltage and the reset voltage to obtain a second voltage, wherein the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after correlated multi-sampling, and the second voltage is the product of the first voltage and the first sampling times; converting the second voltage into a second digital code; and determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.

On the basis of the embodiment shown in fig. 17, it is also possible to include: converting the first pixel voltage into a third digital code according to the first pixel voltage, wherein the first pixel voltage is the accumulated sum of the pixel voltage after the pixel voltage is subjected to the correlated multi-sampling of the first sampling times; converting the reset voltage into a fourth digital code according to a first reset voltage, wherein the first reset voltage is the accumulated sum of the reset voltage after the reset voltage is subjected to related multi-sampling of the first sampling times; determining a second digital code according to the third digital code and the fourth digital code, wherein the second digital code is a digital code corresponding to a second voltage, and the second voltage is the accumulated sum of the pixel voltage and the voltage value of the reset voltage after relevant multi-sampling; and determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.

Specifically, first, after the pixel voltage is subjected to the correlated multi-sampling for the first sampling number of times, a first pixel voltage is output, and the first pixel voltage is the accumulated sum of the pixel voltages after the pixel voltage is subjected to the correlated multi-sampling for the first sampling number of times. Converting the first pixel voltage into a third digital code; and secondly, outputting a first reset voltage after the reset voltage is subjected to the correlated multi-sampling for the first sampling times, wherein the first reset voltage is the accumulated sum of the reset voltage after the reset voltage is subjected to the correlated multi-sampling for the first sampling times. Converting the first reset voltage into a fourth digital code; thirdly, determining a second digital code according to the third digital code and the fourth digital code, wherein the second digital code is a digital code corresponding to a second voltage, and the second voltage is the accumulated sum of the voltage values of the pixel voltage and the reset voltage after relevant multi-sampling; and determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In short, the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

The image reading circuit and components provided in the present application are described in detail above, and specific embodiments of the present application are described herein by using specific examples, and the description of the above embodiments is only used to help understanding the method and its core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

An image reading circuit, comprising: a photoelectric conversion circuit, a judgment circuit and a related multi-sampling circuit;

the photoelectric conversion circuit comprises a photoelectric sensor and a reset circuit, wherein the photoelectric sensor is used for receiving photons and outputting photoelectrons, and the reset circuit is used for outputting a reset voltage;

the photoelectric conversion circuit is used for collecting pixel voltage and respectively outputting the pixel voltage to the judging circuit and the related multi-sampling circuit;

the judging circuit is used for determining a first sampling time according to the pixel voltage, wherein the first sampling time is negatively related to the pixel voltage;

the correlated multi-sampling circuit is used for performing correlated multi-sampling on the pixel voltage and the reset voltage according to the first sampling times to determine a first voltage, and the first voltage is a voltage generated by photoelectrons.
The image reading circuit according to claim 1, wherein the photoelectric conversion circuit further comprises: a first transistor, a second transistor, a first capacitor, and a second capacitor, wherein,

the first transistor is electrically connected with the photosensor, the first transistor is electrically connected with the second capacitor, and the first transistor is electrically connected with the reset circuit, wherein the first transistor is used for switching on or off a connection path between the photosensor and the second capacitor, the first transistor is also used for controlling the switching on or off of the connection path between the reset circuit and the second capacitor, and the second capacitor is used for collecting the pixel voltage;

the second transistor is electrically connected with the first transistor, the second transistor is electrically connected with the first capacitor, the second transistor and the first transistor are jointly used for controlling the connection or disconnection of a connection path between the reset circuit and the first capacitor, and the first capacitor is used for collecting the reset voltage;

the correlated multi-sampling circuit is electrically connected with the second transistor, and the second transistor is used for controlling the connection path between the correlated multi-sampling circuit and the first capacitor to be switched on or switched off;

the correlated multi-sampling circuit is electrically connected to the second capacitor.
The image reading circuit according to claim 2, wherein the judgment circuit includes a first voltage comparator, a threshold voltage generation circuit, and a multi-sampling number selection circuit, the first voltage comparator being electrically connected to the threshold voltage generation circuit, the threshold voltage generation circuit being configured to generate a first threshold voltage;

the first voltage comparator is electrically connected with the second capacitor and used for comparing the first threshold voltage with the pixel voltage to generate a first voltage comparison result;

the first voltage comparator is electrically connected with the multi-sampling frequency selection circuit, and the multi-sampling frequency selection circuit determines the first sampling frequency according to the first voltage comparison result.
The image reading circuit according to claim 3, wherein the judgment circuit further comprises a second voltage comparator electrically connected to the threshold voltage generation circuit, the second voltage comparator being electrically connected to the multiple sampling number selection circuit;

the second voltage comparator is used for determining a second voltage comparison result according to a second threshold voltage and the pixel voltage, and the second threshold voltage is generated by the threshold voltage generation circuit;

the multi-sampling-frequency selection circuit is specifically configured to: determining a voltage interval of the pixel voltage according to the first voltage comparison result and the second voltage comparison result;

and determining the first sampling times according to the voltage interval.
The image reading circuit according to any one of claims 1 to 4, further comprising a first analog-to-digital converter and a pixel processor, wherein the correlated multisampling circuit is electrically connected to the determination circuit, the correlated multisampling circuit is electrically connected to the first analog-to-digital converter, the correlated multisampling circuit is electrically connected to the photoelectric conversion circuit, the first analog-to-digital converter is electrically connected to the pixel processor, and the pixel processor is electrically connected to the determination circuit;

the correlated multi-sampling circuit is used for performing correlated multi-sampling on the pixel voltage and the reset voltage to obtain a second voltage, wherein the second voltage is the accumulated sum of voltage values of the pixel voltage and the reset voltage after the correlated multi-sampling, and the second voltage is the product of the first voltage and the first sampling times;

the first analog-to-digital converter is used for converting the second voltage into a second digital code;

the pixel processor is used for determining a first digital code according to the second digital code and the first sampling times, wherein the first digital code is the digital code of the first voltage.
The image reading circuit according to any one of claims 1 to 4, further comprising a first analog-to-digital converter and a pixel processor, wherein the correlated multisampling circuit is electrically connected to the determination circuit, the correlated multisampling circuit is electrically connected to the photoelectric conversion circuit, the correlated multisampling circuit is electrically connected to the first analog-to-digital converter, the first analog-to-digital converter is electrically connected to the pixel processor, and the pixel processor is electrically connected to the determination circuit;

the correlated multi-sampling circuit is also used for performing correlated multi-sampling on the pixel voltage for the first sampling times and acquiring a first pixel voltage;

the first analog-to-digital converter is used for converting the first pixel voltage into a third digital code;

the correlated multi-sampling circuit is also used for acquiring the reset voltage after correlated multi-sampling of the first sampling times to obtain a first reset voltage;

the first analog-to-digital converter is further configured to convert a first reset voltage into a fourth digital code, where the first reset voltage is an accumulated sum of the reset voltages after the reset voltages are subjected to the correlated multi-sampling by the correlated multi-sampling circuit for the first sampling number of times;

the pixel processor is configured to determine a second digital code according to the third digital code and the fourth digital code, where the second digital code is a digital code corresponding to a second voltage, and the second voltage is an accumulated sum of voltage values of the pixel voltage and the reset voltage after related multi-sampling;

the pixel processor is further configured to determine a first digital code according to the second digital code and the first sampling frequency, where the first digital code is a digital code of the first voltage.
The image reading circuit according to any one of claims 1 to 6, wherein the photoelectric conversion circuit further includes a first source follower;

first source follower with the photoelectric sensor electricity is connected, first source follower with reset circuit electricity is connected, first source follower with first transistor electricity is connected, first source follower is used for completely cutting off photoelectric sensor with first transistor reset circuit with electric current between the first transistor.
The image reading circuit according to claim 7, wherein the photoelectric conversion circuit further includes a second source follower;

the second source follower is electrically connected with the second transistor, the second source follower is electrically connected with the second capacitor, the second source follower is electrically connected with the judging circuit and the related multi-sampling circuit, and the second source follower is used for amplifying the pixel voltage and the reset voltage output by the photoelectric conversion circuit.
An image sensor comprising a pixel control circuit and the image reading circuit of any one of claims 1 to 8,

the pixel control circuit is used for controlling the exposure of the image reading circuit.
An image capturing optical system comprising a lens group and the image sensor of claim 9,

the lens group is used for converging light;

the image sensor is used for processing the light rays converged by the lens group.
A terminal device comprising an image signal processor and the optical system for image capturing according to claim 10, wherein,

the image capturing optical system is used for outputting an image;

the image signal processor is used for optimizing the image output by the image capturing optical system.