KR102110482B1 - Analog-digital converter using time stretcher, and image sensor having the same - Google Patents

Abstract

The present invention relates to an analog-to-digital converter having an improved effect such as reduction in required clock and power consumption by applying a time amplification technique. According to the present invention, the analog-to-digital converter comprises: a comparator for generating a first reference signal based on an analog signal; a time amplifier which amplifies the residual time difference formed between a falling edge of a master clock and a falling edge of the first reference signal generated by the comparator to generate a second reference signal; and a counter which generates a digital signal using the first and second reference signals.

Description

Analog-to-digital converter using time amplifier and image sensor including it {ANALOG-DIGITAL CONVERTER USING TIME STRETCHER, AND IMAGE SENSOR HAVING THE SAME}

The present invention relates to an analog-to-digital converter using a time amplifier and an image sensor including the same, and more specifically, a technique for an analog-to-digital converter having improved effects such as reduction in required clock and reduction in power consumption by applying time amplification technology. to be.

As the demand for high-speed image sensors increases, analog-to-digital converters that convert the output of image sensors also require high-speed driving.

The single-slope analog-to-digital converter is the most widely used analog-to-digital converter for image sensors. Conventional single-slope analog-to-digital converters have the advantages of small footprint, efficient power consumption, and low noise design in low-speed environments. However, with the advent of high-speed image sensors, single-slope analog-to-digital converters require gigahertz (GHz) clocks and power consumption proportional to speed for high-speed operation. As the conventional single-slope analog-to-digital converter consumes enormous power, it is difficult to improve the camera performance of a mobile device.

In order to solve the problems of the conventional single-slope analog-to-digital converter, various alternatives such as a multi-slope, double-slope analog-to-digital converter, and a dual gain amplifier have been proposed.

In the multi-slope technique, in order to perform sampling multiple times, the number of ramp signals required for a single slope must be included in the number of multiple samplings. As multiple ramp signals are inputted in multiple slopes, mismatch between each other is generated, and an error is generated due to mismatch, which has not been put into practical use.

The dual gain amplifier is a technique to convert the slope of the lamp. The double gain amplifier has not been put into practical use due to a problem of linearity. In addition, two gains are included at the front end of the lamp, whereby the problem of excessive power consumption still exists.

All of the conventionally proposed techniques are proposed to be applied to a megahertz (MHz) environment, and when used in gigahertz, power consumption is remarkably high and there is a problem in linearity. I can't.

Patent Registration No. 10-1750240

Accordingly, the present invention has been proposed to solve the above-mentioned problems, and the object of the present invention is to provide an analog-to-digital converter with improved effects such as reduction in required clock and reduction in power consumption by applying a time amplification technique. Let's do it as an assignment.

In order to achieve the above object, an analog-to-digital converter using a time amplifier according to the technical idea of the present invention is an analog-to-digital converter for converting an analog signal into a digital signal, and based on the analog signal, a first reference signal Comparators to produce; A time amplifier for amplifying a time residual difference formed between a falling edge of the master clock and a falling edge of the first reference signal generated by the comparator to generate a second reference signal; It characterized in that it comprises a counter for generating a digital signal using the first reference signal and the second reference signal.

In addition, the time amplifier may be characterized in that it is driven at the same clock frequency as the master clock.

In addition, the time amplifier may be characterized by amplifying the remaining time difference by using a difference in charging time of at least two capacitors having different capacities by an amplification multiple.

In addition, the time amplifier, the signal control unit for generating a reset signal and a start signal using the master clock and the first reference signal; A battery unit including a first battery charged when a reset signal is generated by the signal control unit and a second battery charged when a start signal is generated by the signal control unit and having a capacity greater than an amplification multiple than the first battery; It may be characterized in that it comprises a dynamic comparison unit for generating the second reference signal using the voltage of the first battery and the second battery.

In addition, in order to remove different reset noises of the first battery and the second battery, a noise removing unit connected between the battery unit and the dynamic comparison unit may be further included.

In addition, the dynamic comparator may generate a second reference signal by generating a clock until the voltage of the second battery reaches the voltage of the first battery.

In addition, the counter includes a first counter for generating a first digital signal based on the second reference signal and the master clock; It may be characterized in that it comprises a second counter for generating a second digital signal based on the first reference signal and the master clock.

In addition, the second counter may be characterized by adding an extra bit of 1 bit to the first reference signal for the accurate time amplification.

Also, the second counter may include a double data rate (DDR) counter that adds the extra bit to the first reference signal without increasing the cycle.

According to the analog-to-digital converter using the time amplifier according to the present invention and an image sensor comprising the same,

First, the present invention has an effect that the required clock is significantly reduced by using a time amplifier, so that the cycle is reduced by 1/10 or more compared to a conventional single-slope analog-to-digital converter.

Second, according to the present invention, power consumption is reduced as cycles are reduced.

Third, according to the present invention, as the DDR counter adds an extra bit to the first reference signal, no cycle addition occurs even if the extra bit is added.

Fourth, according to the present invention, since a negative value can be derived from the first counter, it is possible to acquire the necessary CDS data even in one operation.

Fifth, since the present invention uses the format of a signal input to a conventional single-slope analog-to-digital converter such as a pixel signal and a ramp signal, it is easy to apply since the design of the conventional image sensor module is not significantly changed.

1 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention.
Fig. 2 shows the analog-to-digital converter circuit structure of this embodiment.
Fig. 3 is a diagram showing the operation signal relationship of the analog-to-digital converter circuit of this embodiment.
4 is a view showing an example in which a negative value is derived from the first counter and a process for processing the negative value.
5 is a view showing the relationship between the output of the first counter and the output of the second counter.
6 is a block diagram of a time amplifier according to this embodiment.
7 is a view showing a step of resetting the time amplifier using a reset signal.
8 is a diagram showing a circuit structure and an operation signal relationship of a time amplifier driven by a sampling stage.
9 is a view showing a circuit structure and an operation signal relationship of a time amplifier driven by an amplification step.
10 is a configuration diagram of an image sensor according to an embodiment of the present invention.
11 is a block diagram and timing diagram of an experimental CMOS image sensor according to an embodiment of the present invention.
Fig. 12 is a block diagram of time stretch and the principle of operation.
13 is a simplified block diagram of MSB counter, LSB counter and CDS operation.
14 is a diagram showing an experimental chip produced for the experiment of the present invention.
15 is a view showing the results of measuring the random noise of the test chip.
16 is a diagram showing a sample image taken at 500 fps by an experimental chip.

An analog-to-digital converter using a time amplifier according to embodiments of the present invention and an image sensor including the same will be described in detail with reference to the accompanying drawings. The present invention can be variously changed and can have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure form, and it should be understood that it includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each drawing, similar reference numerals are used for similar components.

In addition, unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms, such as those defined in a commonly used dictionary, should be interpreted as having meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application. Does not.

1 to 3, the analog-to-digital converter 100 according to an embodiment of the present invention includes a comparator 110 that generates a first reference signal based on an input analog signal. In addition, a time amplifier (120) for generating a second reference signal by amplifying the time residual difference formed between the falling edge of the master clock and the falling edge of the first reference signal generated by the comparator 110 (Time stretcher, 120) Includes. In addition, it includes a counter (Counter, 140) for generating a digital signal using the first reference signal and the second reference signal.

In the related art, one comparator 110 and one counter 140 are connected in series. The embodiment of the present invention further includes a time amplifier 120, the counter 140 is composed of two, and the like.

)의 변환에 의한 자동영점조정(Auto-Zeroing)에 의해 감소된다.The offset of the comparator 110 is AZ signal before analog-to-digital conversion (

) Is reduced by auto-zeroing.

)이 입력된다. 또한, 픽셀전압(

)과 함께 램프전압(

)도 입력된다. 픽셀전압(

)은 먼저 리셋전압이 입력된다. 램프전압(

)은 종래 싱글슬로프(Single-Slope) 아날로그-디지털 변환기에서도 이용되는 신호이다.The comparator 110 detects incident light and generates a pixel voltage of the pixel 210 (

) Is entered. Also, the pixel voltage (

) And lamp voltage (

) Is also entered. Pixel voltage (

), The reset voltage is input first. Lamp voltage (

) Is a signal that is also used in a conventional single-slope analog-to-digital converter.

)과 픽셀전압(

)의 출력이 동일할 때 출력되는 제1기준신호(

)를 생성한다. 비교기(110)에서 생성된 제1기준신호(

)는 마스터클록(

)과 함께 제2카운터(142) 및 시간증폭기(120)에 전달된다.The comparator 110 has a lamp voltage (

) And pixel voltage (

) Is the first reference signal output when the output is the same (

). The first reference signal generated by the comparator 110 (

) Is the master clock (

) Is transmitted to the second counter 142 and the time amplifier 120.

)에 대응하여 마스터클록(

)이 발생된다.3, the lamp voltage (

) Corresponding to the master clock (

) Occurs.

)이 반복하여 상승하강하는 것은 램프전압(

)의 하강을 개수하는 것이다.Master clock in red dashed circle (

) Is the ramp voltage (

) Is to count the descent.

)이 픽셀전압(

)의 신호에 도달될 때까지 증가된다.ADC OUT is lamp voltage (

) Is the pixel voltage (

) Until the signal is reached.

)의 하강 에지(edge)와 마스터클록(

)의 다음 하강 에지 사이에는 시간잔여차이(

)가 존재한다.Referring to the enlarged view of the red dashed circle, the first reference signal (

) 'S falling edge and master clock (

) Between the next falling edges.

) Exists.

)를 증폭한다.The time amplifier 120 is the difference in time remaining by the number of A times gained (倍)

Amplify).

)를 몇 배로 증폭하느냐에 따라 사이클의 속도가 상이해진다. 예를 들어, 시간증폭기(120)가 시간잔여차이(

)를 16배 증폭하면 10ns 동안 나타나는 영역이 160ns 동안 나타나게 된다. 1GHz를 기준으로 가정하면, 10ns에서 10GHz를 얻기 위해서는 1GHz 클록이 10회 반복되어야 하고, 160ns에서 10GHz를 얻기 위해서는 16배 증가된 80MHz 클록이 10회 반복되어야 한다. 즉, 필요 클록이 현저히 감소된다.Time amplifier 120 is the time difference (

), The speed of the cycle varies depending on how many times it is amplified. For example, the time amplifier 120 is the time remaining difference (

When amplified) 16 times, the region appearing for 10 ns appears for 160 ns. Assuming 1 GHz, the 1 GHz clock must be repeated 10 times to obtain 10 GHz at 10 ns, and the 80 MHz clock increased by 16 times to obtain 10 GHz at 160 ns must be repeated 10 times. That is, the required clock is significantly reduced.

) 및 마스터클록(

)을 비교 및 증폭하여 제2기준신호(

)를 생성한다. 시간증폭기(120)에서 생성된 제2기준신호(

)는 제1카운터(141)에 전달된다. The time amplifier 120 is the first reference signal (

) And master clock (

) To compare and amplify the second reference signal (

). The second reference signal generated by the time amplifier 120 (

) Is transferred to the first counter 141.

)과 동일한 클록 주파수에서 구동한다.Time amplifier 120 is a master clock (

).

) 및 마스터클록(

)에 기초하여 제1 디지털 신호를 생성하는 제1카운터(141), 제1기준신호(

) 및 마스터클록(

)에 기초하여 제2 디지털 신호를 생성하는 제2카운터(142)를 포함한다.The counter 140 is the second reference signal (

) And master clock (

), A first counter 141 for generating a first digital signal, a first reference signal (

) And master clock (

), A second counter 142 for generating a second digital signal.

The first counter 141 may be an LSB counter (Least Significant Bit counter). Also, the second counter 142 may be a MSB counter (Most Significant Bit counter).

)이 아날로그-디지털 변환된 신호의 값이 출력된다.The signal output from the LSB counter and MSB counter is the pixel voltage (

) The value of the analog-digital converted signal is output.

)이 필요하다. 반면 이 실시예는 시간증폭기(120)의 이득이 16배로 설정하면, 제1카운터(141)는 4비트, 제2카운터(142)는 6비트로 분할될 수 있다. 이때 제1카운터(141)는 16사이클(

), 제2카운터(142)는 64사이클(

)이 되고, 최종 변환되는 사이클은 제1카운터(141)의 사이클과 제2카운터(142)의 사이클을 더한 80사이클이 된다. 종래 싱글슬로프 아날로그-디지털 변환기와 이 실시예의 사이클 수를 비교하면, 종래기술이 이 실시예보다 12.8배 만큼 많은 사이클이 필요함을 알 수 있다.The bit division of the counter 140 corresponds to a multiple that the time amplifier 120 amplifies. For example, when the analog signal of the pixel 210 is converted into a 10-bit digital signal, the conventional single-slope analog-to-digital converter converts 1,024 cycles (

) Is required. On the other hand, in this embodiment, when the gain of the time amplifier 120 is set to 16 times, the first counter 141 may be divided into 4 bits, and the second counter 142 may be divided into 6 bits. At this time, the first counter 141 is 16 cycles (

), The second counter 142 is 64 cycles (

), And the last converted cycle is 80 cycles of the cycle of the first counter 141 plus the cycle of the second counter 142. Comparing the number of cycles of this embodiment with the conventional single-slope analog-to-digital converter, it can be seen that the prior art requires 12.8 times as many cycles as this embodiment.

)에 1비트의 여분비트를 추가한다. 이때, 범위를 벗어나는 오류에는 칩과 같은 하드웨어 제조 공정의 문제로 시간증폭기(120)가 증폭하는 배수와 실제 이득이 서로 상이한 경우가 포함된다. 예를 들어, 시간증폭기(120)가 16배 증폭하는 것으로 설정되었으나, 칩이나 제조상의 문제에 의해 16.6배와 같이 실제 이득이 상이하게 나타날 수 있다. 이때 제1카운터(141)의 출력은 0 내지 16으로 나타나고, 16의 출력은 본래의 범위인 0 내지 15를 벗어나는 오류가 된다.On the other hand, if the second counter 142 is composed of two steps of analog-digital conversion of a large range, and then the first counter 141 is composed of two steps of analog-digital conversion of the detailed range or the remaining range, the first counter 141 and If the second counter 142 is not exactly matched and driven, a code of the output digital signal may be omitted or an error may occur. The second counter 142 of this embodiment prevents errors out of range, and a first reference signal (

) To add a 1-bit extra bit. At this time, the error out of the range includes a case in which the multiple of the time amplified by the time amplifier 120 and the actual gain are different due to a problem of a hardware manufacturing process such as a chip. For example, the time amplifier 120 is set to amplify 16 times, but the actual gain may be different, such as 16.6 times, due to chip or manufacturing problems. At this time, the output of the first counter 141 appears as 0 to 16, and the output of 16 becomes an error that is outside the original range of 0 to 15.

=8)와 같다. 예를 들어, 여분비트가 0이라면 제1카운터(141)는 0 내지 7의 값이 출력되어야 하고(제1카운터의 4번째 비트가 0이므로), 여분비트가 1이라면 제1카운터(141)는 8 내지 15의 값이 출력되어야 한다. 따라서 여분비트가 0임에도 8 또는 9가 출력되거나, 여분비트가 1임에도 16이 출력되면 이것을 비교하여 보정한다.If the first counter 141 is 4 bits, the extra bit is the 4th bit of the first counter 141 (

= 8). For example, if the extra bit is 0, the first counter 141 should output a value from 0 to 7 (because the fourth bit of the first counter is 0), and if the extra bit is 1, the first counter 141 is Values from 8 to 15 should be output. Therefore, if 8 or 9 is output even if the spare bit is 0 or 16 is output even when the spare bit is 1, it is compared and corrected.

)에 여분비트를 추가하는 DDR(Double Data Rate)카운터(143)를 포함한다. 일반적인 카운터는 클록의 하강에지(edge) 또는 상승에지를 이용한다. 하지만 DDR카운터(143)는 클록의 상승에지 및 하강에지를 모두 이용하기 때문에 기준 클록의 두 배의 주파수를 갖는 클록을 사용하는 효과를 가지게 된다. 즉, 일반 카운터는 여분비트의 추가에 2배의 클록 주파수가 필요하지만, DDR카운터(143)는 기준 클록을 2배의 주파수 클록처럼 이용하므로 클록이 증가되지 않는다.Adding an extra bit as a normal counter should double the clock frequency. That is, double conversion cycles must be executed within the same time. To solve this problem, the second counter 142 has a first reference signal (

) Includes a double data rate (DDR) counter 143 that adds an extra bit. A typical counter uses the clock's falling edge or rising edge. However, since the DDR counter 143 uses both the rising edge and falling edge of the clock, it has an effect of using a clock having a frequency twice the reference clock. That is, the normal counter requires twice the clock frequency to add an extra bit, but the DDR counter 143 uses the reference clock like a double frequency clock, so the clock does not increase.

)에 추가한 1비트에 의해 제1카운터(141) 및 제2카운터(142)가 정확히 일치되어 오류 방지가 가능하게 된다.DDR counter 143 is the first reference signal (

), The first counter 141 and the second counter 142 are exactly matched by 1 bit added to prevent errors.

In this embodiment, digital CDS (Correlated Double Sampling) is performed to implement low noise of the image sensor 10. CDS is a method of measuring voltage or current values that can eliminate unwanted offsets.

In the prior art, since the CDS cannot be performed at one time, the calculation results are merged after performing the calculation twice. However, in this embodiment, it is possible to acquire data of the CDS required even in one operation.

)가 후행되는 픽셀데이터(

)보다 항상 작기 때문에 픽셀데이터(

)에서 리셋데이터(

)를 차감하면 양수 값이 도출되는 규칙이 있었다.In the prior art, reset data preceded by the ADC OUT signal (

) Followed by pixel data (

Pixel data (because it is always smaller than)

) To reset data (

There was a rule that subtracted) to derive a positive value.

과 같이 연산된다. 이때, 1의 자리에 해당되는 제1카운터(141)는 [3-9]를 연산하여 [-6]이라는 음수 값을 발생시킨다. 이로써 67에서 57을 차감하여 10이라는 양수의 결과가 출력되는 과정에 제1카운터(141)는 음수 값을 도출할 수 있음을 알 수 있다.On the other hand, a negative value may be derived from the first counter 141 of this embodiment. 4 is a diagram showing a process of subtracting the reset output 57 from the signal output 67 as an example. It can be seen by a simple calculation that the solution of the decimal value minus 67 to 57 is 10. However, if you decompose this into hexadecimal

Is calculated as At this time, the first counter 141 corresponding to 1 digit calculates [3-9] to generate a negative value of [-6]. Accordingly, it can be seen that the first counter 141 can derive a negative value in the process of subtracting 67 from 57 and outputting a positive result of 10.

In this embodiment, a sign flag bit indicating a negative value is added over the first counter 141. The method used at this time is bit inversion (BI).

)는 픽셀(210)의 다음 신호로 변환된 때의 초기 값으로 이용된다. 픽셀(210)의 신호 변환 후, 픽셀데이터(

)도 리셋데이터(

)를 읽을 때와 마찬가지의 신호형태를 갖는다.Reset data (

) Is used as an initial value when converted to the next signal of the pixel 210. After the signal conversion of the pixel 210, the pixel data (

) Reset data (

) Has the same signal format as when reading.

)는 제1카운터(141)의 출력

와 제2카운터(142)의 출력

가 더해진 값이고, 픽셀데이터(

)는 제1카운터(141)의 출력

와 제2카운터(142)의 출력

가 더해진 값이다.5, reset data (

) Is the output of the first counter 141

And the output of the second counter 142

Is the added value, and the pixel data (

) Is the output of the first counter 141

And the output of the second counter 142

Is the added value.

-

와 같게 된다.The final result of the first counter 141 and the second counter 142 is

-

It becomes like.

The configuration and operation of the time amplifier 120 will be described in more detail with reference to FIGS. 6 to 9.

) 및 제1기준신호(

)를 이용하여 리셋신호(

) 및 시동신호(

)를 생성하는 신호제어부(122)를 포함한다. 또한, 신호제어부(122)에서 리셋신호(

)가 생성될 때 충전되는 제1전지(

) 및 신호제어부(122)에서 시동신호(

)가 생성될 때 충전되며 제1전지(

)보다 증폭 배수(A)만큼 큰 용량을 가지는 제2전지(

)를 포함하는 전지부(124)를 포함한다. 또한, 제1전지(

) 및 제2전지(

)의 전압을 이용하여 제2기준신호(

)를 생성하는 동적비교부(126)를 포함한다.The time amplifier 120 of this embodiment, the master clock (

) And the first reference signal (

) To reset signal (

) And start signal (

It includes a signal control unit 122 for generating a. In addition, the reset signal from the signal control unit 122 (

) Is the first cell that is charged when it is generated (

) And the start signal (

) Is charged when generated and the first cell (

), The second battery having a capacity greater than the amplification multiple (A) (

), Including a battery unit 124. In addition, the first battery (

) And the second battery (

), The second reference signal (

It includes a dynamic comparison unit 126 to generate a.

)과 제1기준신호(

)의 하강 에지를 비교하여 리셋신호(

) 및 시동신호(

)를 생성한다.The signal control unit 122 uses a D-flip-flop and a NOR logic gate to create a master clock (

) And the first reference signal (

) To compare the falling edge of the reset signal (

) And start signal (

).

) 생성 시 전류원(

)과 제1전지(

)를 연결하는 제1스위치를 on 한다(도 7 참조).Signal control unit 122 is a reset signal (

) Current source at creation (

) And the first battery (

) Is turned on (see Fig. 7).

) 생성 시 제1스위치를 off 하고, 전류원(

)와 제2전지(

)를 연결하는 제2스위치를 on 한다(도 8 참조).Also, the start signal (

) When generating, turn off the first switch, and

) And the second battery (

) Is turned on (see Fig. 8).

) 및 제2전지(

)는 커패시터로 구성될 수 있다. 만약, 증폭 배수(A)가 16이면, 제2전지의 용량은 16×

가 된다.First battery (

) And the second battery (

) May be composed of a capacitor. If the amplification multiple (A) is 16, the capacity of the second battery is 16 ×

Becomes.

)의 출력 전압

가 입력되고, 타측에 제2전지(

) 출력 전압

가 입력된다.The dynamic comparison unit 126 has a first battery (

) Output voltage

Is input, and the second battery (

) Output voltage

Is input.

) 생성 전에 제1전지(

)의 출력 전압

및 제2전지(

) 출력 전압

를 초기화한다.The dynamic comparison unit 126 includes an offset removal technique. The dynamic comparison unit 126 is a second reference signal (

) First battery before creation (

) Output voltage

And the second battery (

) Output voltage

Initialize

)와 제2전지(

)의 서로 상이한 리셋노이즈 제거를 위해, 전지부(124)와 동적비교부(126) 사이에 연결되는 노이즈제거부(

, 128)를 더 포함한다. 노이즈제거부(

, 128)는 제1전지(

)와 동적비교부(126)를 연결하는 선로와 제2전지(

)와 동적비교부(126)를 연결하는 선로에 각각 연결되는 커패시터가 될 수 있다.The time amplifier 120 of this embodiment is a first battery (

) And the second battery (

) For removing different reset noises of the noise removing unit connected between the battery unit 124 and the dynamic comparison unit 126 (

, 128). Noise removal unit (

, 128) is the first cell (

) And the line connecting the dynamic comparison unit 126 and the second battery (

) And a capacitor connected to a line connecting the dynamic comparison unit 126, respectively.

)와 제2전지(

)의 오프셋은 동적비교부(126)의 입력 오프셋과 같다. 따라서 리셋을 하는 동안 제1전지(

)와 제2전지(

)의 오프셋은 노이즈제거부(

, 128)에 음수로 저장된다. 리셋 후 제1전지(

)와 제2전지(

)의 출력은 가지고 있는 오프셋에 노이즈제거부(

, 128)에 저장된 음수 오프셋이 더해져 오프셋이 제거된 형태로 동적비교부(126)에 입력된다.First battery (

) And the second battery (

) Is the same as the input offset of the dynamic comparison unit 126. Therefore, during reset, the first battery (

) And the second battery (

) Is the noise removal part (

, 128). After reset, the first battery (

) And the second battery (

), The noise is removed at the offset of the output (

, 128) is added to the dynamic comparison unit 126 in a form in which the offset is removed by adding the negative offset.

)가 제1전지(

), 제2전지(

) 및 동적비교부(126)에 전달되어 각 구성이 리셋된다.Referring to Figure 7, first, the reset signal (

) Is the first battery (

), Second battery (

) And the dynamic comparison unit 126 to reset each component.

)가 생성될 때 시간잔여차이(

)의 샘플링이 실시된다. 신호제어부(122)가 제1스위치를 on 하면(제2스위치는 off), 전류원(

)이 제1전지(

)에 공급되어, 제1전지(

)가 충전된다. 이때 출력 전압

신호는

보다 상대적으로 높은 기울기로 상승하게 된다.Referring to FIG. 8, the reset signal (

) Is generated, the time residual difference (

) Is sampled. When the signal control unit 122 turns on the first switch (the second switch is off), the current source (

) Is the first battery (

), The first battery (

) Is charged. At this time, the output voltage

The signal is

It rises at a higher slope.

)가 생성될 때 시간잔여차이(

)의 증폭이 실시된다. 신호제어부(122)가 제1스위치 off 및 제2스위치를 on 하면, 제1전지(

)의 충전이 중단되어

신호의 상승도 중단된다. 이때

는

가 된다. 또한 전류원(

)이 제2전지(

)에 공급되어 제2전지(

)가 충전된다.Referring to FIG. 9, the start signal from the signal control unit 122 (

) Is generated, the time residual difference (

) Is amplified. When the signal control unit 122 turns on the first switch and the second switch, the first battery (

) Is stopped charging

The signal rise is also stopped. At this time

The

Becomes. Also the current source (

) Is the second battery (

) Supplied to the second battery (

) Is charged.

)는 제1전지(

)와 대비하여 증폭 배수만큼 큰 용량을 가지므로,

는

보다 증폭 배수만큼 느리게 전압이 상승한다.Second battery (

) Is the first battery (

), So it has a capacity as large as the amplification multiple,

The

The voltage rises more slowly than the amplification multiple.

)의 전압

가 제1전지(

)의 전압

에 도달될 때까지 클록을 발생시켜 제2기준신호(

)를 생성한다.The dynamic comparison unit 126 is a second battery (

) Voltage

1st battery (

) Voltage

Generate a clock until reaching the second reference signal (

).

)의 동작 시간은

이 된다.Therefore, the second reference signal (

)

It becomes.

The reason for the difference between the capacitors of the first battery and the second battery is that the time amplifier 120 multiplies the time with a slew rate.

)만을 이용하기 때문에 커패시터로 구성된 전지부(124)의 용량이 클수록 전하를 충전하기 위해 비례하는 시간이 필요하다. 즉, 증폭 배수가 16인 상태에서 전류원(

)을 이용하여 제1전지(

)가 충전되면, 제2전지는 제1전지만큼 충전하기 위해 16×

, 즉 16배 더 많은 시간이 필요하다. 이로써 시간 증폭이 실시될 수 있게 된다.The time amplifier 120 is a current source (

), The larger the capacity of the battery unit 124 made of a capacitor, the more time is required to charge the electric charge. That is, the current source (with amplification multiple of 16)

) Using the first battery (

) Is charged, the second battery is 16 × to charge as much as the first battery.

In other words, 16 times more time is required. This allows time amplification to be performed.

Referring to FIG. 10, an embodiment of the present invention may be an image sensor 10.

The image sensor 10 of this embodiment includes a pixel 210 that detects incident light and generates an analog signal. It also includes an analog-to-digital converter 100 that is connected to the pixel 210 and converts an analog signal to a digital signal.

The pixel 210 is composed of a plurality. The plurality of pixels 210 are respectively coupled to the column lines to form the pixel array 200.

)는 복수의 칼럼라인을 통해 아날로그-디지털 변환기(100)에 제공될 수 있다.Each pixel 210 may convert an optical signal into an electrical signal. The pixel array 200 may be driven by driving signals such as a selection signal, a reset signal, and a transmission signal from a row decoder. In addition, the pixel voltage, which is an electrical signal sensed by each pixel 210 in response to the driving signals (

) May be provided to the analog-to-digital converter 100 through a plurality of column lines.

The analog-to-digital converter 100 includes a comparator 110 generating a first reference signal based on the analog signal, a falling edge of the master clock, and a falling edge of the first reference signal generated by the comparator 110. It includes a time amplifier 120 for amplifying the residual time difference formed in the second reference signal to generate a digital signal using the first reference signal and the second reference signal.

The analog-to-digital converter 100 of this embodiment may include the configuration and features of the embodiments of the analog-to-digital converter 100 described above.

Experiment.

)의 변환에 의한 자동영점조정(Auto-Zeroing)에 의해 감소된다. 픽셀의 리셋 신호는 비교기(100)에 적용되며, 리셋 변환은 0.6μs 변환 시간 내에 수행된다. 램프전압(

)이 픽셀전압(

)의 출력 전압과 같을 때, 비교기(100) 출력인 제1기준신호(

)는 100MHz 클록 주파수에서 작동하는 7b MSB카운터(142)를 트리거한다. 제1기준신호(

)의 하강 에지와 마스터클록(

)의 다음 하강 에지 사이에는 시간잔여차이(

)가 여전히 존재한다. 시간증폭기(120)는 시간잔여차이(

)를 16배로 확장하고, 4b LSB카운터(141)에 제2기준신호(

)를 제공한다. LSB카운터(141)는 마스터클록(

)과 동일한 클록 주파수에서 작동한다. 10b 변환의 경우, 64 (MSB)와 16 (LSB)의 합계로 계산되는 80 사이클을 필요로 한다. 범위를 벗어나는 오류를 피하기 위해, MSB카운터(142)는 1b 이중화를 사용하여 시간증폭기(120)의 정확성에 대한 요구 사항을 완화한다. 리셋 변환 후 카운터 출력의 각 비트가 반전된다. 이 비트반전(BI)은 리셋데이터의 음의 값(-

)을 제공하며 다음 변환의 초기 값으로 이용한다. 픽셀에서의 전하 전송 후, 0.8μs의 변환 시간 내에 픽셀전압(

)(전압 스윙 = 1V)의 신호 레벨을 판독한다. MSB카운터(142)와 LSB카운터(141)의 최종 결과는 디지털 CDS 작동을 실현하는 두 신호 (

-

)의 차이를 가진다. 변환 후, 각 열의 카운터 출력은 SRAM으로 동시에 전송되고, 다음 행의 변환 동안 감지증폭기(sense amplifiers)에 의해 판독된다.11 is a block and timing diagram of this embodiment. The column circuit is composed of a comparator 110, a time stretcher 120, and an MSB counter 142 and an LSB counter 141. The 1-H conversion time is set to 4 μs, allowing 500 fps for the VGA pixel array. Before conversion, the offset of the comparator 100 is an AZ signal (

) Is reduced by auto-zeroing. The reset signal of the pixel is applied to the comparator 100, and the reset conversion is performed within 0.6 μs conversion time. Lamp voltage (

) Is the pixel voltage (

), The same as the output voltage, the first reference signal (

) Triggers a 7b MSB counter 142 operating at a 100 MHz clock frequency. 1st reference signal (

) 'S falling edge and master clock (

) Between the next falling edges.

) Still exists. The time amplifier 120 is the time remaining difference (

) To 16 times, and the second reference signal (4b LSB counter 141)

). LSB counter 141 is the master clock (

) At the same clock frequency. For a 10b conversion, it takes 80 cycles, calculated as the sum of 64 (MSB) and 16 (LSB). To avoid out-of-range errors, MSB counter 142 uses 1b redundancy to alleviate the requirement for accuracy of time amplifier 120. After reset conversion, each bit of the counter output is inverted. This bit inversion (BI) is the negative value of the reset data (-

) And is used as the initial value of the next transformation. Pixel voltage (within 0.8 μs conversion time after charge transfer from pixel)

) (Voltage swing = 1V). The final result of the MSB counter 142 and LSB counter 141 is that the two signals that realize digital CDS operation (

-

). After conversion, the counter output of each column is simultaneously sent to the SRAM and read by sense amplifiers during the conversion of the next row.

)를 마스터클록(

) 신호의 하강 에지와 비교하는 것으로 리셋신호(

) 및 시동신호(

)가 생성된다. 시간증폭기(120)는 전류원(

), 제1전지(

)와 제2전지(16×

) 및 오프셋을 캔슬하는 동적비교부(126)로 구성된다. 변환 전, 제1전지(

)와 제2전지(16×

)의 출력 전압

및

가 리셋된다. 동시에, 비교기(110)의 프리앰프의 바이어스 전압은 노이즈제거부(

, 128)에 저장된다. 리셋신호(

)를 이용한 잔여 샘플링 단계에서 전류원(

)은 제1전지(

)(0.2pF)를 충전하고, 출력 전압

는 선형으로 상승하며,

는 0으로 유지된다. 비교기(110)의 오차를 고려할 때, 최대

스윙은 0.8V로 선택되며, 이것은 625ps의 시간 분해능을 위한 50mV의 LSB스텝에 해당한다.The operation of the time amplifier 120 will be described with reference to FIG. 12. The first reference signal of the comparator 110 (

) To the master clock (

) Compared to the falling edge of the signal to reset signal (

) And start signal (

) Is generated. The time amplifier 120 is a current source (

), The first battery (

) And the second battery (16 ×

) And the dynamic comparison unit 126 for canceling the offset. Before conversion, first battery (

) And the second battery (16 ×

) Output voltage

And

Is reset. At the same time, the bias voltage of the preamplifier of the comparator 110 is a noise removing unit (

, 128). Reset signal (

Current source in the residual sampling stage using)

) Is the first battery (

) (0.2pF), output voltage

Is linearly rising,

Remains 0. Considering the error of the comparator 110, the maximum

The swing is chosen to be 0.8V, which corresponds to an LSB step of 50mV for a time resolution of 625ps.

)은 제2전지(16×

)로 전환되어 공급되고,

를

/

로 설정한다.

는 16배 느린 슬루레이트로 램프 업을 시작하고,

가

값에 도달할 때까지 동적비교부(126)가 LSB카운터(141)에 대한 제2기준신호(

)를 생성한다. 따라서 제2기준신호(

)의 동작주기는 16

를 나타내며, 주기는 LSB카운터(141)의 값을 결정한다.The current source (

) Is the second battery (16 ×

) And supplied,

To

/

Set to

Starts ramping up with a 16x slow slew rate,

end

The dynamic comparison unit 126 until the value reaches the second reference signal for the LSB counter 141 (

). Therefore, the second reference signal (

) Is 16

And the period determines the value of the LSB counter 141.

13 is a simplified block diagram of the MSB counter 142 and the LSB counter 141. Since the MSB counter 142 and the LSB counter 141 have no interaction, they can operate independently. Each counter cell includes a toggle flip-flop (TFF) and a BI block. For counter operation, the BI block transfers bits from the LSB counter 141 to the MSB cell.

The CDS operation generates a toggle signal regardless of the state of the LSB counter 141, and inverts the state of each counter cell.

)가 트리거 될 때 마스터클록(

)의 상태를 저장하는 DDR(Double Data Rate)카운터(143) 셀을 사용하므로 MSB카운터(142)의 1b 확장(

)이 발생한다. 클록 스위칭이 배제되기 때문에 DDR카운터(143) 셀의 전력 소비는 무시할 수 있다.To implement 1b redundancy, the MSB counter 142 has a first reference signal (

) When the master clock (

) Uses the DDR (Double Data Rate) counter 143 cell to store the state, so the 1b extension of the MSB counter 142 (

) Occurs. Since the clock switching is excluded, the power consumption of the DDR counter 143 cell can be neglected.

)를 추가하여 해결된다.After the CDS operation, unlike the value of the MSB counter 142 (eg, 16), the value of the LSB counter 141 may be positive or negative (eg, -1) as shown in the lower part of FIG. 13. . This prevents direct bit combinations between the results of the two counters. This problem is caused by the sign flag bit (sign flag bit) in the LSB counter 141 (

).

After conversion, including CDS operation, the ADC output can be obtained by summing the MSB counter 142 and LSB counter 141 outputs (eg, 15 = 16-1). This summation operation can be processed at the output of the sense amplifier, so it does not increase the complexity of the heat level.

14, the chip of this embodiment occupies an area of 5.5 x 4.5 mm2. The chip consumes 76mW from a 3.3 / 1.5V (analog / digital) power supply. The pixel array consists of 640x480 pixels with a 4μm pixel pitch and is implemented with standard 4T pixels.

의 픽셀 변환 이득으로 2.85

의 RN을 달성하였다. 이 RN은 8배 아날로그 게인으로 1.95

로 더욱 개선되었다. 시간증폭의 이득은 모든 열에 대해서도 측정된다. 16.12의 평균 이득과 15.84와 16.34 사이의 이득 편차를 나타내며, 누락된 코드가 없는 경우 ±0.2LSB 오류를 나타내었다. 수직FPN(VFPN)은 0.71

와 0.18

이다. 각각 1배와 8배의 아날로그 게인을 얻는다. 도 16은 이 실시예에 따른 칩이 500fps에서 촬영한 샘플 이미지이다.Referring to FIG. 15, random noise (RN) is measured using an analog gain of a ramp generator. 82

With a pixel conversion gain of 2.85

RN was achieved. This RN is an 8x analog gain of 1.95

Was further improved. The gain of time amplification is also measured for all heat. It shows the average gain of 16.12 and the gain deviation between 15.84 and 16.34, and ± 0.2LSB error when there is no missing code. Vertical FPN (VFPN) is 0.71

And 0.18

to be. 1 and 8 times the analog gain, respectively. 16 is a sample image taken by the chip according to this embodiment at 500 fps.

의 FoM을 1배 및 8배 아날로그 게인으로 달성하였다.Table 1 shows a summary of the performance of the chip according to this embodiment and a comparison with the state-of-the-art technology. The pixel rate of the embodiment of the present invention is lower than the others, but it has a fast 1-H time among single-slope ADCs even when the clock frequency is low. In terms of energy efficiency, these examples are 1.41 and 0.96 respectively.

FoM was achieved with 1x and 8x analog gain.

The preferred embodiments of the present invention have been described above, but the present invention can use various changes, modifications, and equivalents. It is clear that the present invention can be equally applied by appropriately modifying the above embodiments. Therefore, the above description is not intended to limit the scope of the present invention as defined by the following claims.

10: image sensor 100: analog to digital converter
110: comparator 120: time amplifier
122: signal control unit 124: battery unit
126: dynamic comparison unit 128: noise removal unit
140: counter 141: first counter
142: 2nd counter 143: DDR counter
200: pixel array 210: pixel

Claims (10)

In the analog-to-digital converter for converting an analog signal to a digital signal,
A comparator generating a first reference signal based on the analog signal;
A time amplifier for amplifying a time residual difference formed between a falling edge of the master clock and a falling edge of the first reference signal generated by the comparator to generate a second reference signal; And
And a counter for generating a digital signal using the first reference signal and the second reference signal. According to claim 1,
The time amplifier is analog-to-digital converter, characterized in that is driven at the same clock frequency as the master clock. According to claim 1,
The time amplifier is an analog-to-digital converter, characterized in that amplifying the remaining time difference by using a difference in charging time of at least two capacitors having different capacities by amplification multiples. The method of claim 1, wherein the time amplifier,
A signal control unit generating a reset signal and a start signal using the master clock and the first reference signal;
A battery unit including a first battery charged when a reset signal is generated by the signal control unit and a second battery charged when a start signal is generated by the signal control unit and having a capacity greater than an amplification multiple than the first battery; And
And a dynamic comparison unit that generates the second reference signal using the voltages of the first battery and the second battery. The method of claim 4,
Analog-to-digital converter further comprises a noise removing unit connected between the battery unit and the dynamic comparison unit to remove different reset noises of the first battery and the second battery. The method of claim 4,
The dynamic comparison unit generates a second reference signal by generating a clock until the voltage of the second battery reaches the voltage of the first battery. The method of claim 1, wherein the counter
A first counter for generating a first digital signal based on the second reference signal and the master clock; And
And a second counter for generating a second digital signal based on the first reference signal and the master clock. The method of claim 7,
Analog-to-digital converter, characterized in that by adding an extra bit of 1 bit to the second counter for accurate time amplification. The method of claim 8,
The second counter includes an analog-to-digital converter, comprising a DDR (Double Data Rate) counter that adds the extra bits without increasing cycles. A pixel that senses incident light to generate an analog signal; And
An analog-to-digital converter connected to the pixel and converting the analog signal to a digital signal,
The analog-to-digital converter,
A comparator generating a first reference signal based on the analog signal;
A time amplifier for amplifying a time residual difference formed between a falling edge of the master clock and the falling edge of the first reference signal generated by the comparator to generate a second reference signal; And
And a counter for generating a digital signal using the first reference signal and the second reference signal.

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