KR100976697B1 - Residue amplifier and its application for analog to digital converter - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a residual voltage amplifier and an analog / digital converter using the same, and includes a residual amplifier of each stage in a multi-stage analog / digital converter (hereinafter, referred to as 'ADC'). ) Function, LDO (Dow) which is used as power supply voltage of ADC without receiving reference voltage necessary for operation of Digital Analog Converter (DAC) from separate reference voltage supply. By using the stabilized voltage generated by the Low Drop-Out Regulator, it is possible to design power consumption and chip area by eliminating the reference voltage supply, which is one of the essential components in the existing design, and to maximize the input signal. By allowing the power supply voltage to be processed, it is possible to improve the dynamic range (DR) of the input signal at low power supply voltage conditions. And it is.

Residual Voltage Amplifier, MDAC, Pipeline, ADC, LDO

Description

RESIDUE AMPLIFIER AND ITS APPLICATION FOR ANALOG TO DIGITAL CONVERTER}

The present invention relates to a residual voltage amplifier and an analog / digital converter using the same. More particularly, the residual voltage of each stage in a multi-stage analog / digital converter (hereinafter, referred to as 'ADC') is described. In the function of the Residue Amplifier, the reference voltage necessary for the operation of the Digital Analog Converter (DAC) is not supplied from a separate reference voltage supply, but is supplied to the power supply voltage of the ADC. By utilizing the stabilized voltage generated by the low drop-out regulator (LDO) used, the design reduces power consumption and chip area by eliminating the reference voltage supply, which is one of the essential components in the existing design. As the input signal can be processed up to the maximum power voltage, the dynamic range (DR) of the input signal can be The present invention relates to a residual voltage amplifier that can be improved and an analog / digital converter using the same.

In general, a pipelined analog digital converter (ADC) is a multi-step quantizer in which low-resolution ADCs of the same or similar structure are connected in a cascade form.

1 is a block diagram illustrating the structure of a conventional pipeline ADC.

Referring to FIG. 1, the pipeline ADC is composed of n stages STG1 to STGn, and each stage STGi is a sample-and-holder 110 for sampling an input analog signal. And an ADC 120 for converting an input analog signal into a low resolution digital code of a corresponding stage, and a DAC (Digital Analog Converter) for obtaining a difference between a representative analog value corresponding to an output of the ADC 120 and an actual signal. 130, a subtractor 140, and a residual voltage amplifier 150 that amplifies the difference (residual voltage) between the analog input signal and the corresponding digital code and has a gain of 2 ^Bi-1 .

Here, Bi is the resolution of the i-th stage (STGi), which is designed to correct the error of the ADC generated in each stage by designing at 1/2 of the gain in the ideal case, and generally DCL (Digital) Correction Logic (170).

In FIG. 1, a building block that combines the S / H 110, the DAC 130, and the residual voltage amplifier 150 is called a multiplying DAC 160 (MADC), which is a core in implementing a pipelined ADC. Block.

In order for the MDAC and Flash ADCs of traditional pipeline ADCs to operate correctly, precise reference voltages are required to drive the capacitors used in each stage. In order to achieve such a precise reference voltage, an integrated circuit (IC) typically uses a unity feedback buffer.

The timing of each operation of the ADC having such a multi-stage structure may vary depending on the type (eg, pipeline, two-step and cyclic). However, the upper digital code including the MSB is obtained from the first stage (STG1) 100, and the remaining codes are sequentially obtained from the lower stages (STG2 to STGn). Each stage can achieve digital codes ranging from a minimum of one bit to a maximum of six bits, depending on the design.

FIG. 2 is a circuit diagram for explaining the structure of a stage that obtains a 1.5-bit resolution. For simplicity of explanation, it is assumed that a positive power supply of + V _DD and -V _SS is applied based on a zero potential. (Single-ended) signal was used. However, the structure proposed in the present invention is not limited thereto, and can be easily applied to a structure using a single power supply and a differential signal.

The operation of this circuit is explained as follows. While the clock is Φ ₁ , the ADC 200, consisting of two comparators, outputs a code of B [1: 0] = 00, 01, or 10 to its output depending on the size of the input and into a switched-capacitor amplifier. The implemented residual voltage amplifier 210 stores input signals in the first and second capacitors C ₁ and C ₂ .

When the next Φ ₂ section, the corresponding reference voltage is connected to the first capacitor C ₁ according to the output code of the ADC 200 determined in the previous Φ ₁ section, and the second capacitor C ₂ is connected to the output. The residual voltage is amplified. The output voltage V _{RES at} this time is expressed by Equation 1 below.

V _RES = 2V _IN -bV _REF

Here, b corresponds to a value of -1 if the output B [1: 0] of the ADC 200 is 00, 0 if 01, and 0 if 10, and this connection is connected to the switch logic 220. Is performed by. When the residual voltage thus obtained is plotted against the input signal, transfer characteristics as shown in FIG. 3 are obtained. In addition, -V _REF / 4 and V _REF / 4 are reference voltages of the two comparators used in the ADC 200 (Non-Patent Document 1; S. Lewis, H. Fetterman, G. Gross, R. Ramachandran, and T. Viswanathan, "A 10-b 20-Msample / s Analog-to-Digital Converter," IEEE J. Solid-State Circuits , vol. SC-27, pp. 351-358, March 1992}.

FIG. 3 is a graph illustrating the residual voltage transfer characteristic of FIG. 2. FIG. 4 is a diagram illustrating an output terminal and a residual voltage curve of the residual voltage amplifier of FIG. 2. FIG. 5 is a residual voltage amplifier in an LDO power environment. Is a view for explaining the output terminal and the residual voltage curve of Figure 6 is a circuit diagram for driving the reference voltage applied in FIG.

3 to 6, it can be seen that the maximum range of the input signal is +/- V _REF equal to the range of the output signal of the residual voltage amplifier 210. That is, the maximum range of the input signal is limited to the maximum swing width of the residual voltage amplifier 210.

Considering the more practical case of the circuit of FIG. 2, which assumes a positive power supply, to a general case using a single power supply of V _DD and GND, the positive reference voltage indicated by V _REF is V _RT , and -V _REF. The negative reference voltage, denoted by, corresponds to V _RB , and the center of the reference voltage, denoted by zero potential, corresponds to V _DD / 2. 4 illustrates the output terminal structure 211 and the residual voltage characteristic curve 213 of the residual voltage amplifier 210.

That is, if the ADC 200 is designed in consideration of the maximum output swing of the residual voltage amplifier 210, the maximum value of the positive reference voltage V _RT corresponds to V _DD -V _dsat ", and the negative reference voltage V _RB The lowest value can be designed as V _dsat .

Therefore, if the residual voltage characteristic in Non-Patent Document 1 is used, the maximum range of the signal that can be processed by the ADC 200 becomes "V _RT -V _RB = V _DD -2V _dsat " as shown in FIG. . The voltage of 2V _dsat occupies an area that cannot be ignored in a trend where V _DD is gradually decreasing due to the miniaturization of the process, which drastically lowers the dynamic range (DR) of the input signal.

In addition, when the ADC IP is applied to the SoC, and the LDO (Low Drop-Out Regulator) 215 is used for stabilizing the power supply voltage, as shown in FIG. 5, the drop-out voltage (Drop−) of the LDO 215 is reduced. Out Voltage, V _DO ) causes the range of available input signals to be reduced further, making the problem even bigger.

In addition, in order to generate the reference voltages of V _RT and V _RB , a reference voltage generator 230 and a driver 240 as shown in FIG. 6 should be provided. This occupies an insurmountable proportion in the area and power consumption of the ADC 200.

As described above, if the residual voltage characteristic curve 213 shown in FIG. 4 is used to ensure the saturation region operation of the residual voltage amplifier 210 as the power supply voltage decreases, the output voltage of the residual voltage amplifier 210 may be reduced. The burden of the V _dsat voltage increases, which causes a serious reduction in the ratio of V _IN / V _DD , resulting in a decrease in dynamic range (DR), and a burden of a large area of the chip and power consumption for providing a reference voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a reference voltage required for the operation of a DAC in a multi-stage ADC in which a residual voltage amplifier of each stage functions. By using a stabilized voltage generated by the LDO, which is used as the supply voltage for the ADC, the design reduces power consumption and chip area by eliminating the reference voltage supply, which is one of the essential components in the existing design. The present invention provides a residual voltage amplifier and an analog / digital converter using the same to improve the dynamic range (DR) of an input signal under a lower power supply voltage condition by processing an input signal up to a maximum power supply voltage.

In order to achieve the above object, a first aspect of the present invention provides an operational amplifier having one input terminal connected to a first internal voltage; And a capacitor circuit connected to the other input terminal of the operational amplifier, the capacitor circuit comprising: a first capacitor having a common terminal connected to the other input terminal of the operational amplifier; A second capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to the common terminal of the first capacitor; A third capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to an output terminal of the operational amplifier; A first switch connected to an input terminal of the first capacitor to selectively switch a second internal voltage and a ground voltage; And a second switch connected to an input terminal of the second capacitor to selectively switch a third internal voltage and a ground voltage.

Here, the first internal voltage is preferably made of half of the second and third internal voltage.

Preferably, the first and second switches can be switched controlled in accordance with the output of the analog-to-digital converter.

Preferably, the first to third internal voltages may be supplied from a low drop-out regulator (LDO).

A second aspect of the present invention has a pipeline structure consisting of a multi-stage, each stage comprising: a sample-hold circuit for converting an analog input signal into a digital signal; An analog / digital converter for outputting a digital bit corresponding to the analog input signal; A digital / analog converter for converting the digital signal into an analogized signal according to the output digital bit; And a residual voltage amplifier for amplifying a difference between the analog input signal and the analogized signal, wherein the residual voltage amplifier comprises: an operational amplifier having one input terminal connected to a first internal power supply voltage; And a capacitor circuit connected to the other input terminal of the operational amplifier, the capacitor circuit comprising: a first capacitor having a common terminal connected to the other input terminal of the operational amplifier; A second capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to the common terminal of the first capacitor; A third capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to an output terminal of the operational amplifier; A first switch connected to an input terminal of the first capacitor to selectively switch a second internal voltage and a ground voltage; And a second switch connected to an input terminal of the second capacitor to selectively switch a third internal voltage and a ground voltage.

According to the residual voltage amplifier of the present invention and the analog-to-digital converter using the same as described above, the residual voltage amplifier of each stage in the multi-stage ADC function, the reference voltage required for the operation of the DAC as a separate reference By using a stabilized voltage generated by the LDO, which is used as the supply voltage for the ADC, instead of being provided by the voltage supply, power consumption and chip area can be reduced by eliminating the reference voltage supply, which is one of the essential components in conventional designs. Since the design is possible and the input signal can be processed up to the maximum power supply voltage, there is an advantage of improving the dynamic range DR of the input signal under the low power supply voltage condition.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to enable those skilled in the art to more fully understand the present invention.

First, the present invention is outside the Lewis structure shown in the existing non-patent literature 1, which is generally used, non-patent literature 2 {I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample / s Nyquist-rate CMOS ADC," IEEE J. Solid - State Circuits , vol. 35, pp. 318-325, March 2000} is proposed to obtain the proposed residual voltage characteristics for fast settling (settling), and propose a method using V _{DD_int} and GND as the reference voltage.

7 is a view for comparing the residual voltage characteristics of the structure applied in the conventional techniques and the structure proposed in the present invention, the current voltage characteristics of the conventional Lewis structure and the residual voltage characteristics 300 using a separate reference voltage supply; And a residual voltage characteristic 400 of the proposed structure of the present invention using V _DD and GND as reference voltages.

Referring to FIG. 7, reference numeral 500 denotes an output terminal of the residual voltage amplifier as illustrated in FIG. 5 and illustrates a case in which a power supply voltage is supplied using a low drop-out regulator (LDO).

That is, when using the proposed structure of the present invention, that is, the proposed residual voltage characteristic 400 using the power supply voltage as the reference voltage, the range of the input signal that the amplifier can process is from GND to V _{DD_int} , Can handle the full range of power supply voltage.

This residual voltage characteristic 400 is required only in the first stage, and after the second stage, the existing Lewis structure may be applied. This is because the output of the first stage already occupies only a part of the range that all subsequent stages can handle.

The disadvantage of this case, however, is that the offset range of the comparable comparator is reduced. For example, when setting a separate reference voltage in consideration of the maximum output swing of the amplifier as shown in FIG. 4 described above, in the case of assuming that there is no other error, a corresponding step using digital error correction is performed. The comparator offset to +/- 0.5LSB voltage with stage resolution is not a problem at all.

However, in the proposed structure of the present invention, only the signal until the output signal of the residual voltage amplifier is saturated can be modified. This is because if the output is more than that, the linearity of the output signal by the saturated amplifier is so low that the lower code cannot be obtained correctly.

The allowable offset voltage of the comparator is based on the difference between the minimum output voltage (V _RB ) and V _DD / 4 of the amplifier used, and the difference between the maximum output voltage (V _RT ) and V _DD * 3/4 of the amplifier. Is determined by.

In the 1.5-bit / stage structure shown as an example in FIG. 7, the allowable offset voltage of the comparator is determined to be (V _RT -3/4 * V _DD ) / 2 or (V _DD / 4-V _RB ) / 2. Where / 2 is due to the gain of the amplifier.

For example, as shown in FIG. 7, _{1.5-bit with} the output V _{DD_int} = 1V of the LDO, the lowest output voltage of the residual voltage amplifier, V _RB is V _{DD_int} / 8, and the maximum output voltage V _RT is _7/8 * V _{DD_int} . In the case of / stage, the allowable offset voltage in the comparator is +/- V _{DD_int} / 16.

When V _{DD_int} is 1V, +/- 62.5mV is the allowable offset of the comparator. However, as in the general case, when the circuit is implemented in full differential, the range of modifiable offsets doubles.

FIG. 8 is a circuit diagram of a specific residual voltage amplifier for implementing the residual voltage of FIG. 7. The proposed structure of the present invention is similar to the conventional Lewis structure, but the reference voltages are the internal power supply voltage V _{DD_int} and the ground voltage (0). Is the main difference.

Referring to FIG. 8, the residual voltage amplifier 800 according to an embodiment of the present invention includes a large operational amplifier 810 and a capacitor circuit 820.

Here, the operational amplifier 810 has a positive input terminal and an output terminal connected to the negative input terminal and the internal power supply voltage V _{DD_int} / 2. The capacitor circuit 820 has an operational amplifier 810 connected to a negative input terminal.

The capacitor circuit 820 includes first to third capacitors 821 to 823. The upper electrode of the first capacitor 821 is connected to the negative terminal of the operational amplifier 810, and the lower electrode is connected to the first switch 824. The upper electrode of the second capacitor 822 is connected to the negative terminal of the operational amplifier 810, and the lower electrode is connected to the second switch 825. The upper electrode of the third capacitor 823 is connected to the negative terminal of the operational amplifier 810, and the lower electrode is connected to the output terminal of the operational amplifier 810.

The first switch 824 is connected to the lower electrode of the first capacitor 821 to selectively switch the internal power supply voltage V _{DD_int} and the ground voltage 0 according to the output b of the ADC. The switch 825 is connected to the lower electrode of the second capacitor 822 to selectively switch the internal power supply voltage V _{DD_int} and the ground voltage 0 according to the output b of the ADC.

On the other hand, considering that the circuit in which the ADC receives the signal (usually a variable gain amplifier or an anti-aliasing filter) also uses the same internal power supply voltage (V _{DD_int} ) as the ADC, the input can be processed by the ADC. It will be appreciated that the magnitude of the signal does not need to reach V _DD . The circuit driving the ADC is also limited because its output is limited by the amplifier's output range. Therefore, the residual voltage characteristic shown in FIG. 7 is not necessarily essential.

9 is a view for explaining the output terminal and the residual voltage curve of the residual voltage amplifier according to an embodiment of the present invention using the Lewis structure in the LDO power environment, while using the reference voltage as the internal power supply voltage (V _{DD_int} ) It shows the case of using the existing Lewis structure shown in a non-Patent Document 1.

Referring to FIG. 9, assuming that the maximum range of the output swing of the amplifier is V _{DD_int} / 8 to V _{DD_int} x 7/8, the input of the signal capable of processing a signal without distortion of linearity in a 1.5-bit / stage structure The maximum range is 0.875V _DD with V _{DD_int} / 16 to V _{DD_int} * 15/16.

This voltage range is beyond the range of the maximum output swing that the preceding circuit can deliver to the ADC in low-power circuits, even though the ADC does not receive the full range of signals from GND to V _DD . There will be no loss of the incoming signal.

However, since all codes corresponding to the entire combination of the output codes of the ADC are not obtained, the disadvantage of the effective number of bits (ENOB) is slightly reduced.

That is, it can process only a signal that corresponds to 0.875V _{DD DD} ~ 0.9375V 0.0625V as in _DD 000 111 and 0 ... ... corresponding to the code or the largest signals corresponding to the smallest signal, such as 1 Extreme output codes such as codes cannot be generated.

For example, when designing a 10-bit ADC, supplying input voltages within the range of 0.0625V _DD to 0.9375V _DD yields up to 1024 * 0.875 = 896 codes at the output.

However, even with this reduced code, an ADC with 9.8-bit resolution is implemented, which is not a problem for most applications. In this case, the range of allowable offsets of the comparator has the same condition as in FIG.

That is, even if the existing Lewis structure is used as it is and the power voltage from the LDO is used as the reference voltage, there is an advantage that the performance change is almost unchanged. Since the range of the full scale signal is widened, the voltage corresponding to the LSB increases. The design conditions such as the offset of the comparator are also not significantly changed. However, in order to use the structure proposed in FIGS. 7 and 9, the regulation of V _{DD_int} is an important design issue in order to prevent the characteristic degradation caused by noise of the reference voltage.

Meanwhile, in order to explain the present invention, the structure of 1.5-bit / stage has been described as an example, but it can be applied to any resolution structure, and as the resolution obtained at each stage increases, the gain of the residual voltage amplifier is improved, thereby increasing the dynamics of the input. The dynamic range is increased. 10 shows an example of the configuration of the existing ADC and the proposed ADC.

Although a preferred embodiment of the above-described residual voltage amplifier according to the present invention and an analog-to-digital converter using the same has been described, the present invention is not limited thereto, but the scope of the claims and the detailed description of the invention and the accompanying drawings are various. It is possible to carry out the transformation by the branch and this also belongs to this invention.

1 is a block diagram illustrating the structure of a conventional pipeline ADC.

2 is a circuit diagram for explaining the structure of a stage that obtains a 1.5-bit resolution.

3 is a graph illustrating the residual voltage transfer characteristic of FIG. 2.

4 is a view for explaining the output terminal and the residual voltage curve of the residual voltage amplifier of FIG.

5 is a view for explaining the output voltage and the residual voltage curve of the residual voltage amplifier in the LDO power environment.

FIG. 6 is a circuit diagram for driving the reference voltage applied to FIG. 2.

7 is a view for comparing the residual voltage characteristics of the structure applied in the conventional techniques and the structure proposed in the present invention.

8 is a circuit diagram of a specific residual voltage amplifier for implementing the residual voltage of FIG.

9 is a view for explaining the output voltage and the residual voltage curve of the residual voltage amplifier according to an embodiment of the present invention using the Lewis structure in the LDO power environment.

10 is a view for explaining the configuration of the existing ADC and the configuration example of the proposed ADC of the present invention.

Claims (8)

An operational amplifier having one input terminal connected to the first internal voltage; And A capacitor circuit connected to the other input terminal of the operational amplifier, The capacitor circuit, A first capacitor having a common terminal connected to the other input terminal of the operational amplifier; A second capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to the common terminal of the first capacitor; A third capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to an output terminal of the operational amplifier; A first switch connected to an input terminal of the first capacitor to selectively switch a second internal voltage and a ground voltage; And And a second switch connected to an input terminal of the second capacitor to selectively switch a third internal voltage and a ground voltage. According to claim 1, And wherein the first internal voltage is half of the second and third internal voltages. According to claim 1, The first and second switches are residual voltage amplifiers, characterized in that the switching control according to the output of the analog-to-digital converter. According to claim 1, The first to third internal voltage is a residual voltage amplifier, characterized in that supplied from a low drop-out regulator (LDO). Has a pipeline structure consisting of multi-stage, each stage, A sample-hold circuit for converting an analog input signal into a digital signal; An analog / digital converter for detecting a digital bit corresponding to the analog input signal; A digital / analog converter for converting the digital signal into an analogized signal according to the digital bit; And A residual voltage amplifier for amplifying the difference between the analog input signal and the analogized signal, The residual voltage amplifier, An operational amplifier having one input terminal connected to the first internal voltage; And A capacitor circuit connected to the other input terminal of the operational amplifier, The capacitor circuit, A first capacitor having a common terminal connected to the other input terminal of the operational amplifier; A second capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to the common terminal of the first capacitor; A third capacitor having a common terminal connected to the other input terminal of the operational amplifier and connected to an output terminal of the operational amplifier; A first switch connected to an input terminal of the first capacitor to selectively switch a second internal voltage and a ground voltage; And And a second switch connected to an input terminal of the second capacitor to selectively switch a third internal voltage and a ground voltage. 6. The method of claim 5, And the first internal voltage is half of the second and third internal voltages. 6. The method of claim 5, And the first and second switches are controlled to be switched according to the output of the analog / digital converter. 6. The method of claim 5, And the first to third internal voltages are supplied from a low drop-out regulator (LDO).

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