CN114567323A - Differential input voltage charge scaling SAR _ ADC - Google Patents

Abstract

The invention discloses a differential input voltage charge scaling SAR _ ADC (synthetic aperture radar) which belongs to the field of integrated circuits and aims to solve the problem that a large amount of capacitors occupy the area of a chip in a common multi-bit SAR _ ADC circuit. The invention comprises a VREF voltage divider, a capacitor array DAC1, a capacitor array DAC2, a comparator, a SAR logic circuit and an N-bit register; the capacitor array DAC1 and the capacitor array DAC2 both adopt an A + B bit combined DAC, the high-order part A is subjected to capacitive scaling, the low-order part B is subjected to reference voltage scaling, and N is equal to A + B; the VREF voltage divider provides voltages for capacitive array DAC1 and capacitive array DAC 2; the capacitor array DAC1 and the capacitor array DAC2 are connected to differential input signals VREF-AD and AD, wherein VREF is a system reference voltage, and AD is an analog input signal; the capacitor array DAC1 and the capacitor array DAC2 respectively output N times of voltage values under the control of the SAR logic circuit, the output voltages VO1 and VO2 are subjected to difference comparison through a comparator each time, the comparison result is stored in an N-bit register as a valid bit each time, and the conversion result formed by N times of comparison is output.

Description

Differential input voltage charge scaling SAR _ ADC

Technical Field

The invention relates to a DAC circuit structure in a Successive Approximation Register (SAR) analog-to-digital converter (ADC), belonging to the field of integrated circuits.

Background

One of the most important functions of signal processing is to convert between analog and digital signals. The function of an analog-to-digital converter (ADC) is to convert an incoming analog signal into a corresponding binary digital character code. Since the analog signal is continuous in both time and amplitude, while the digital code is discrete, the ADC system includes signal sample and hold procedures. The successive approximation type in the ADC type is essentially a binary search method, taking the example of searching for a random number in 1-16, first determining whether the number is larger than 8 or smaller than 8, and if larger than 8, larger than 12 or smaller than 12. The third search is further narrowed in the second search interval, and so on until the corresponding number is found.

FIG. 1 shows a schematic block diagram of an analog-to-digital converter (ADC) in which an analog input voltage Vin and a DAC output voltage Vo are compared, V_REFIs the reference voltage supplied to the ADC, the N-bit register is first set to the middle scale (i.e., 100 … 00, MSB set to 1) to implement the binary search algorithm. Thus, the DAC output voltage Vo is set to V_REF/2. Then, the magnitude relation of Vin and Vo is compared and judged, if Vin is smaller than Vo, the comparator outputs logic high level or1, MSB of the N-bit register is clear 0. Conversely, if Vin is greater than or equal to Vo, the comparator outputs a logic low level and the MSB of the N-bit register remains 1. The control logic then moves to the next bit and sets that bit high for the next comparison. This process continues until the LSB. After the above operation is finished, the conversion is finished, and the N-bit conversion result is stored in the register.

The following is a specific analysis taking the structure of the circuit of a conventional three-bit SAR _ ADC as an example given in fig. 2. In fig. 2, the DAC is usually configured as the capacitor network shown in fig. 3, in fig. 2, COMP is a voltage comparator, and when Vin ≧ Vo, the output Vout of the comparator is 0; the output Vout of the comparator is 1 when Vin < Vo. The three flip-flops FFA, FFB and FFC form a 3-bit register, and the flip-flops FF1-FF5 and the gates G1-G9 form a control logic circuit.

Before conversion, the FFA, the FFB and the FFC are set to zero, and meanwhile, a ring shift register formed by FF1-FF5 is set to Q₁Q₂Q₃Q₄Q₅10000 states.

After the shift control signal VL becomes high level, the shift starts. Upon arrival of the first CLK pulse, FFA is set to 1 and FFB, FFC are set to 0. At this point in time state Q of the register_AQ_BQ_C100 to the input of the DAC, and the corresponding analog voltage V is obtained at the output of the DAC converter_O. Comparator C compares V_OAnd voltage value of Vin: when Vin is more than or equal to V_OIf Vout is 0; when Vin < V_OAnd Vout becomes 1. At the same time, the shift register is shifted to the right by one bit, so that Q₁Q₂Q₃Q₄Q₅＝01000。

FFB is set to 1 when the second CLK pulse arrives. If original Vout equals 1, FFA is set to 0; if original Vout is 0, FFA remains at 1. At the same time, the shift register shifts right by one bit, becoming 00100 state.

FFC is set to 1 when the third CLK pulse arrives. If original Vout equals 1, FFB is set to 0; if the original Vout is 0, FFB remains 1. At the same time, the shift register shifts right by one bit, and becomes 00010 state.

When the fourth CLK pulse arrives, it is also determined whether 1 of FFC remains according to the state of Vout at that time. At this time, the states of FFA, FFB and FFC are the result of conversion. At the same time, the shift register shifts right by one bit, becoming 00001 state. Due to Q₅Then the state of FFA, FFB, FFC is transferred to the output through transmission gates G6, G7, G8.

After the fifth CLK pulse arrives, the shift register is shifted to the right by one bit, so that Q₁Q₂Q₃Q₄Q₅10000, return to initial state. At the same time, due to Q₅When the signal is 0, the transmission gates G6, G7, and G8 are blocked, and the switching output signal disappears.

The DAC shown in fig. 3 is a weighted capacitor network used in the ADC of fig. 2, which operates using the principle of capacitive voltage division. Wherein the capacitance of C0, C1 and C2 is increased by a power multiple of 2 in sequence. The states of the switches S0, S1, S2 are controlled by the input digital signals d0, d1, d2, respectively. When di is 1, the corresponding switch Si is connected to the reference voltage V_REFOne side; and when di is 0, the corresponding switch Si is grounded, i is 0,1, 2.

All switches are grounded before switching, so that all capacitors are fully discharged. Then disconnect S_DThe input signals are applied in parallel to the inputs d0, d1, d 2.

According to the principle of capacitive voltage division, the expression of the output analog voltage is as follows:

ct denotes the sum of all capacitance values.

In practical application, a single capacitor of a DAC in the SAR _ ADC has a capacitance value error, and the capacitor array needs to be highly matched to reduce the influence of a process angle. For example, a 12-bit DAC requires 4095 unit capacitors, which occupy a large area of the chip, and it is obviously difficult to highly match a large number of capacitors, which greatly affects the effective number and linearity of the ADC due to the capacitance error of a single capacitor and the weak interference rejection of single-ended analog signal inputs.

Disclosure of Invention

The invention aims to solve the problems that a large number of capacitors occupy the area of a chip, layout cannot be highly matched, single-ended analog signal input has weak anti-interference capability and cannot meet the design requirements of a multi-bit high-speed high-bandwidth ADC in a conventional multi-bit SAR-ADC circuit, and provides a differential input voltage charge scaling SAR-ADC.

The differential input voltage charge scaling SAR _ ADC comprises a VREF voltage divider, a capacitor array DAC1, a capacitor array DAC2, a comparator, an SAR logic circuit and an N-bit register; the capacitor array DAC1 and the capacitor array DAC2 both adopt an A + B bit combined DAC, the high-order part A is subjected to capacitive scaling, the low-order part B is subjected to reference voltage scaling, and N is equal to A + B;

the VREF voltage divider provides voltages for capacitive array DAC1 and capacitive array DAC 2;

the capacitor array DAC1 and the capacitor array DAC2 are connected to differential input signals VREF-AD and AD, wherein VREF is a system reference voltage, and AD is an analog input signal;

the capacitor array DAC1 and the capacitor array DAC2 respectively output N times of voltage values under the control of the SAR logic circuit, the output voltages VO1 and VO2 are subjected to difference comparison through a comparator each time, the comparison result is stored in an N-bit register as a valid bit each time, and the conversion result formed by N times of comparison is output.

Preferably, capacitor array DAC1 and capacitor array DAC2 are identical in structure, and control terminals A, C are wired oppositely;

capacitor array DAC1 includes sampling switch SX, capacitor C0-C (A + B-1), and three-terminal switch S0-S (A + B-1);

one end of a capacitor C0-C (A + B-1) is simultaneously connected with the output port VO1 and one end of a switch SX;

the other end of the switch SX is connected with a voltage V output by a reference voltage VREF voltage divider_REF/2；

The other end of the capacitor C0-C (A + B-1) is respectively and correspondingly connected with a determining end of a three-terminal switch S0-S (A + B-1) in sequence;

GND is simultaneously connected with the A end of the three-terminal switch S (A + B-1) -S (B-1) and the A and B ends of the three-terminal switch S0-S (B-2);

VREF-AD is simultaneously connected with the B terminal of the three-terminal switch S (A + B-1) -S (B-1);

VREF is simultaneously connected with the C terminal of the three-terminal switch S (A + B-1) -S (B);

the C ends of the three-terminal switch S0-S (B-1) are respectively connected with V output by the reference voltage VREF voltage divider in sequence_REF/2^B、V_REF/2^B-1、……V_REF/2；

Capacitor array DAC2 includes sampling switch SX, capacitor C0-C (A + B-1), and three-terminal switch S0-S (A + B-1);

one end of a capacitor C0-C (A + B-1) is simultaneously connected with the output port VO2 and one end of a switch SX;

the other end of the switch SX is connected with a voltage VREF/2 output by a reference voltage VREF voltage divider;

the other end of the capacitor C0-C (A + B-1) is respectively and correspondingly connected with a determining end of a three-terminal switch S0-S (A + B-1) in sequence;

GND is simultaneously connected with the C terminal of the three-terminal switch S (A + B-1) -S (B-1) and the C and B terminals of the three-terminal switch S0-S (B-2);

VREF-AD is simultaneously connected with the B terminal of the three-terminal switch S (A + B-1) -S (B-1);

VREF is simultaneously connected with the A terminal of the three-terminal switch S (A + B-1) -S (B);

the A ends of the three-terminal switch S0-S (B-1) are respectively connected with V output by the reference voltage VREF voltage divider in sequence_REF/2^B、V_REF/2^B-1、……V_REF/2。

Preferably, the SAR logic circuit comprises a switch shift register and N switch controllers SW _ CTL < i >, i being 0,1, …, N-1;

the switch shift register sequentially generates control signals SR < i > according to a clock signal CLK to drive the corresponding switch controller SW _ CTL < i > to work, and generates control signals for controlling the control ends A, B, C of the three-terminal switches S (A + B-1) -S0;

the switch controller SW _ CTL < i > comprises an inverter INV, a flip-flop D1, an OR gate or1 and an NOR gate nor1,

the SR < i > signal is simultaneously connected with the input end of the inverter INV and one input end of the OR gate or 1;

the output end of the inverter INV is connected with the clock input end of the D flip-flop D1;

the Q signal line is connected with a data input end D of a D trigger D1;

the output Q of the D flip-flop D1 is connected with the other input end of the OR gate or 1;

the output end of the OR gate or1 is connected with one input end of the NOR gate nor1 and outputs a control signal SWA < i > for controlling the A control end of the three-terminal switch S (A + B-1) -S0;

the output end of the NOR gate nor1 outputs a control signal SWC < i > for controlling the C control end of the three-terminal switch S (A + B-1) -S0;

the control signals SWB < i > of the B control ends of the three-terminal switches S (A + B-1) -S0 are connected with the other input end of the NOR gate;

a sampling stage: the clock signal CLK is low, SX is 1, SWB is 1, D flip-flop D1 is clear 0, and SR is 0; SWA ═ SWC ═ 0 is obtained;

a comparison stage: the clock signal CLK is a pulse signal, the comparison phase comprises N comparison cycles, and the control end signals SWA < N-1:0> and SWC < N-1:0> of the three-terminal switches S (A + B-1) -S0 of the N comparison cycles are mutually inverse.

Preferably, the data accessed by the Q signal line in each comparison period is the comparison result of the input signal AD and the reference voltage Vi in the nth comparison period and the reference voltage V corresponding to the ith valid bit_i＝K_nV_REF；n＝N-i；

Wherein K_nThe reference voltage of the nth comparison period is compared with the system reference voltage V_REFThe ratio of (A) to (B);

setting initial sampling voltage as V _REF2, the ratio of the 1 st comparison period

At nth comparison period, if AD-K_nV_REFIf greater than 0, then

If AD-K_nV_REFIf less than 0, then

Preferably, the control signal SWA < N-1:0> adopts a successive approximation method and is sequentially obtained in N comparison periods according to the sequence of SWA < N-1> and SWA < N-2> … SWA <0 >;

the SWA <11:0> acquisition process for 12 comparison cycles with N-12 is:

1 st comparison period: by

And

the 1 st comparison period SWA can be deduced<11:0>100000000000 'b, where SWA'd is binary SWA<11:0>A converted decimal result;

comparison cycle 2: if AD-K₁V_REFIf greater than 0, then

Adjusting SWA<10>I.e. SWA<11>The right bit of (1) becomes 1, and the others do not; SWA<11:0>＝110000000000’b；

If AD-K₁V_REFIs less than 0, then

Adjusting SWA<10>1, while SWA<11>0, others are unchanged; SWA<11:0>＝010000000000’b；

Cycle 3: if AD-K₂V_REFIf greater than 0, then

Adjusting SWA<9>I.e. SWA<10>The right bit of (1) becomes 1, and the others do not; SWA<11:0>111000000000 'b or 101000000000' b;

if AD-K₂V_REF<0 then

Adjusting SWA<9>1, with SWA<10>Becomes 0, others do not; SWA<11:0>011000000000 'b or 001000000000' b;

and the rest comparison periods are analogized, and then SWA <11:0> of 12 comparison periods is obtained.

Preferably, the capacitor array DA is over N comparison periodsThe C1 and the DAC2 output N voltage differences VO1-VO2 to the comparator respectively, and the comparison result is used as the conversion result d of the input signal AD_N-1,…,d_i,…,d₁,d₀，

In the formula, V_{O1_Ti}Output voltage, V, for ith compare period capacitor array DAC1_{O2_Ti}For the ith comparison period, the capacitor array DAC2 outputs voltage, and SWA'd _ Ti is binary SWA in the ith comparison period<11:0>A converted decimal result;

if V_{O1_Ti}-V_{o2_Ti}> 0, conversion result d of corresponding bit_iIf 1, if V_{O1_Ti}-V_{o2_Ti}Not more than 0, conversion result d of corresponding bit_i＝0。

The invention has the beneficial effects that: the invention provides a differential input voltage and charge proportional scaling SAR _ ADC circuit, which changes the common sampling and holding mode of SAD _ ADC analog signal single-end input and large-scale capacitor array voltage division, adopts a novel analog signal differential input and voltage and capacitance proportional scaling combined structure, not only can effectively inhibit the interference of irrelevant signals to an input end, but also can greatly reduce the chip occupation area of an ADC, realizes the high matching of layout capacitance, and improves the linearity performance of the ADC, and the circuit is verified by a slice flow.

Drawings

FIG. 1 is a functional block diagram of a prior art successive approximation register analog-to-digital converter SAR _ ADC;

fig. 2 is a circuit configuration diagram of a 3-bit successive approximation register type analog-to-digital converter SAR _ ADC;

FIG. 3 is a diagram of a DAC weighted capacitor network of FIG. 2;

FIG. 4 is a functional block diagram of a differential input voltage charge-scaled SAR _ ADC according to the present invention;

FIG. 5 is a combined A + B DAC capacitor array;

FIG. 6 is a 12-bit DAC capacitor array;

FIG. 7 is a capacitor array structure of a differential DAC1 for an ADC;

FIG. 8 is a capacitor array structure of a differential DAC2 for an ADC;

FIG. 9 is an initialized (sample and hold phase) DAC capacitor array, wherein FIG. 9(a) is DAC1 and FIG. 9(b) is DAC 2;

FIG. 10 is a charge-redistribution DAC capacitor array, wherein FIG. 10(a) is DAC1, and FIG. 10(b) is DAC 2; (ii) a

FIG. 11 is a preliminary control circuit;

FIG. 12 is a SAR logic controller;

FIG. 13 is the signal change for SW _ CTRL <11> with the first comparison high;

FIG. 14 is a SR signal diagram;

fig. 15 is a complete SAR logic controller.

Detailed Description

In the description of a commonly used SAR _ ADC circuit, a single-ended input signal line is used for sampling and holding an analog signal, and the large number of capacitor arrays of a multi-bit DAC cannot be used for very accurate layout matching, so that the problems of poor ADC precision and serious linear distortion are finally caused.

The differential input voltage charge scaling SAR _ ADC circuit provided by the figure 4 adopts a novel analog signal differential input and voltage capacitance scaling type combined structure, and solves the problems that the common SAR _ ADC circuit has poor anti-interference capability of single-end analog signal input and large number of capacitance arrays occupying area and cannot be highly matched. Therefore, differential input and scaling are key to the implementation of the invention.

The first embodiment is as follows: the present embodiment is described below with reference to fig. 4 to 15, and the differential input voltage charge-scaling SAR _ ADC according to the present embodiment includes a VREF voltage divider, a capacitor array DAC1, a capacitor array DAC2, a comparator, a SAR logic circuit, and an N-bit register; the capacitor array DAC1 and the capacitor array DAC2 both adopt an A + B bit combined DAC, the high-order part A is subjected to capacitive scaling, the low-order part B is subjected to reference voltage scaling, and N is equal to A + B;

the VREF voltage divider provides voltages for capacitive array DAC1 and capacitive array DAC 2;

the capacitor array DAC1 and the capacitor array DAC2 are connected to differential input signals VREF-AD and AD, wherein VREF is a system reference voltage, and AD is an analog input signal;

the capacitor array DAC1 and the capacitor array DAC2 respectively output N times of voltage values under the control of the SAR logic circuit, the output voltages VO1 and VO2 are subjected to difference comparison through a comparator each time, the comparison result is stored in an N-bit register as a valid bit each time, and the conversion result formed by N times of comparison is output.

The DAC adopts a differential structure DAC, the DAC1 and the DAC2 have the same structure and different input, an A + B combined DAC is adopted, the DAC generally adopts a voltage and charge scaling mode and is combined according to the proportion of part A capacitance and part B reference voltage to form an A + B bit DAC, and the area of a capacitor array can be effectively reduced. The structure is as shown in FIG. 5:

let b_iIs the coefficient of the ith significant bit, i is 0,1,2, …, N-1, when the switch S is on_iWhen connected to GND, b_i0, otherwise b _i1 is ═ 1; setting VO of all capacitors to be 0 in initial state, when DAC starts to work, charge conservation can be obtained

In the formula, C_totRepresents the sum of all capacitances, C_tot＝(B+2^A-1) C; can be obtained from the above formula

Compared with the traditional capacitance DAC, the combination of the part A and the part B can greatly reduce the area of the capacitor; and compared with the traditional voltage division type, the part B further reduces the area of the resistor.

The following is further illustrated with a 12-bit DAC as an example:

for a 12-bit DAC, a-5 and B-7 combination can be used to achieve 12-bit D/a conversion. As shown in fig. 6:

its output voltage is

The capacitor used by the structure is 7+2⁵-1 ═ 38C (let C be the unit capacitance); is much smaller than 4095 unit capacitors described in the background art, and the resistor for voltage division only needs to provide 7 divided voltage values without designing a divided voltage type DAC.

Similarly, if 10-bit DAC is adopted, the combination is 4+6, 14-bit DAC is 6+8, and 16-bit DAC is 7+ 9.

When the single-ended DAC is applied to the differential structure shown in fig. 4, since a differential comparison structure is adopted, two DACs having the same structure but different switches and inputs are adopted to output a differential voltage V_O1And V_O2Input to a comparator. The structure of DAC1 is shown in fig. 7. The structure of DAC2 is shown in fig. 8.

The capacitor array DAC1 and the capacitor array DAC2 are identical in structure, and the control end A, C is connected in an opposite mode;

capacitor array DAC1 includes sampling switch SX, capacitor C0-C (A + B-1), and three-terminal switch S0-S (A + B-1);

one end of a capacitor C0-C (A + B-1) is simultaneously connected with the output port VO1 and one end of a switch SX;

the other end of the switch SX is connected with a voltage V output by a reference voltage VREF voltage divider_REF/2；

The other end of the capacitor C0-C (A + B-1) is respectively and correspondingly connected with a determining end of a three-terminal switch S0-S (A + B-1) in sequence;

GND is simultaneously connected with the A end of the three-terminal switch S (A + B-1) -S (B-1) and the A and B ends of the three-terminal switch S0-S (B-2);

VREF-AD is simultaneously connected with the B terminal of the three-terminal switch S (A + B-1) -S (B-1);

VREF is simultaneously connected with the C terminal of the three-terminal switch S (A + B-1) -S (B);

the C ends of the three-terminal switch S0-S (B-1) are respectively connected with V output by the reference voltage VREF voltage divider in sequence_REF/2^B、V_REF/2^B-1、……V_REF/2；

Capacitor array DAC2 includes sampling switch SX, capacitor C0-C (A + B-1), and three-terminal switch S0-S (A + B-1);

one end of a capacitor C0-C (A + B-1) is simultaneously connected with the output port VO2 and one end of a switch SX;

the other end of the switch SX is connected with a voltage VREF/2 output by the reference voltage VREF voltage divider;

the other end of the capacitor C0-C (A + B-1) is respectively and correspondingly connected with a determining end of a three-terminal switch S0-S (A + B-1) in sequence;

GND is simultaneously connected with the C terminal of the three-terminal switch S (A + B-1) -S (B-1) and the C and B terminals of the three-terminal switch S0-S (B-2);

VREF-AD is simultaneously connected with the B terminal of the three-terminal switch S (A + B-1) -S (B-1);

VREF is simultaneously connected with the A terminal of the three-terminal switch S (A + B-1) -S (B);

the A ends of the three-terminal switch S0-S (B-1) are respectively connected with V output by the reference voltage VREF voltage divider in sequence_REF/2^B、V_REF/2^B-1、……V_REF/2。

Compared with the single-ended DAC structure shown in FIG. 6, a control switch SX and a control switch B are added, the control switch B is used for connecting differential analog signals input by the ADC, namely VREF-AD and AD respectively, and the two signals are stored on a capacitor in a charge mode in a sampling and holding phase (SX closed); in addition, the control signals connected to GND and VREF by DAC1 and DAC2 are inverted (e.g., C11 of DAC2 is connected to VREF when C11 of DAC1 is connected to GND), and this inverted logic is used to complete SAR logic control.

SX (sample phase closed): the connected V _ REF/2 is mainly used for determining initial voltage, and actually can be other voltage values, but when comparison is carried out after sampling is finished, voltage jump at the point cannot be too large to exceed power supply voltage;

b (sampling phase closed): C11-C6 are connected with differential input quantities (AD, VREF-AD), and C5-C0 are connected with GND; this is to facilitate SAR control;

a and C (alternate closure of the comparison phases): a and C of the DAC1 are respectively connected with GND and a reference voltage, and the A and the C are not conducted at the same time; a and C of DAC2 are connected to reference voltage and GND, where A and C are not conducted at the same time; their a and C can be controlled by the same signal, which is advantageous for SAR logic control;

setting: for the states of two DACs which are switched on SX, A, B and C, SX, SWA < i >, SWB < i > and SWC < i > (i is 0-11) are respectively used for controlling, and 1 is used for switching on, and 0 is used for switching off; wherein SX is 1-bit switch, the other 3 are 12-bit switches, and can be represented by SWA, SWB and SWC (hereinafter, the representation method is used)

To summarize: a sampling stage: SX is 1; SWB <11:0> -1;

a comparison stage: SWA <11:0> and SWC <11:0> are in anti-phase with each other.

Vo1 and Vo2 with initial charge of 0

When SWA<i>When 1, b _i1, otherwise b_i0; assuming that the initial charge is 0 and the circuit is not sampled (SX ═ 0, SWB ═ 0), it can be deduced from equation (3)

Where the factor 38 represents the total capacitance, i.e., the ratio of the total capacitance to the minimum capacitance in the capacitor array.

In parentheses in formula (4)

I.e. SWA<11:0>Converted to decimal and divided by 128. Let SWA<11:0>Is represented by SWA'd (the same applies below) and has

Formulae (4) and (5) can be converted into

In the formula (9)

Is composed of

Maximum value of (d);

to V_o1And V_O2Making a difference, and mentioning 64 outside the brackets, there are

Where 38 represents the total capacitance and 64 is due to the 7-bit scaled reference voltage and the difference result.

SWA for each valid bit<i>Adjusted under control of logic circuit, corresponding SWA<11:0>In a different case, V_O1And V_o2Is different from each other when V_O1-V_O2If the conversion result di is greater than 0, the current valid bit i is represented as 1, otherwise, di is greater than 0, the current valid bit i is placed in a register for temporary storage, and after N times of comparison, the N-bit conversion result d is obtained_N-1,d_N-2The …, d2, d1, d0 are output from the register in binary form at a time as a result of digital conversion of the input signal AD.

The working principle is as follows:

the N-bit ADC conversion includes two phases, an initialization (sample, hold phase) and charge redistribution (compare phase), as described in detail below.

The first stage is as follows: initialization (sample, hold phase): SX is closed, and S11-S0 is connected with B;

the upper plates of all capacitors are connected with VREF/2, the lower plates of C11-C6 are connected with VREF-AD, and the lower plates of C5-C0 are connected with GND, as shown in FIG. 9.

The charge stored on the upper plate of the capacitor can be calculated:

(1) vo1 end:

(2) vo2 end:

(3) Q1-Q2:

sampling the input quantity of the ADC in the initialization process, and storing the comparison to be carried out in the first step of SAR, namely the difference value of AD and VREF/2;

and a second stage: charge redistribution (comparative phase): SX is disconnected, and S11-S0 are connected with A or C; as shown in fig. 10.

V_O1、V_O2Derivation of

After sampling is completed, the circuit enters a comparison phase, Vo1 and Vo2 generated by the DAC1 and the DAC2 in a differential structure are compared, and an ADC result is generated.

Since the circuit is subjected to a sampling phase, the equations (7), (8) and the principle of conservation of charge can be obtained

In the formula

In order to be an error in the measurement,

for key coefficients of SAR logic, it can set

The ADC implemented by the SAR logic needs to adjust Ki corresponding to each valid bit under the control of the SAR logic circuit.

SAR control logic

The SAR logic is a successive approximation process, and it needs to generate a reference voltage value of the next cycle according to the comparison result of the cycle, and obtains each bit code value Q by comparing the reference voltage value Vi with the sampling voltage AD. In a 12-bit ADC, the circuit needs to compare 12 times, i.e. has 12 comparison cycles.

Generally, the process is as follows: 1 st cycle vs. sampling voltage AD and 1 st cycle reference voltage V_REFA difference is made between/2, if the comparison result is greater than 0, the next cycle is to sample the voltage sum (3/4) V_REFDifferencing, otherwise summing (1/4) the sampled voltages_REFMaking a difference; and so on.

Setting AD as input, reference voltages Vi and V of the N-i cycle_REFHas a ratio of K_nThere are the following relationships:

the valid bit i-N-1 corresponds to the N-i-1 period:

the valid bit i ═ N-2 corresponds to the N ═ N-i ═ 2 cycles: if AD-K₁V_REFIf greater than 0, then

If AD-K₁V_REFIf less than 0, then

Cycle 3: if AD-K₁V_REF> 0, and AD-K₂V_REFIf greater than 0

If AD-K₁V_REF> 0, and AD-K₂V_REF<0 then

If AD-K₁V_REF<0, and AD-K₂V_REFIf greater than 0

If AD-K₁V_REF<0, and AD-K₂V_REF<0 then

And (3) knotting: if AD-K_nV_REFIf greater than 0, then

If AD-K_nV_REFIf less than 0, then

(wherein K is_nAs a result of the N-i th comparison cycle)

And (3) comparison process: in the comparison phase, N comparison periods are included, the 1 st comparison period corresponds to the valid bit i being N-1, and the nth comparison period corresponds to the valid bit i being 0.

(1) 1 st comparison period

By

And

the 1 st cycle SWA can be deduced<11:0>100000000000' b, in this case

V_{O1_T1}DAC1 outputs a voltage, V, for the 1 st comparison period_{O2_T1}For the 1 st comparison period DAC2 output voltage, the difference between the two determines d_N-1The result of (1).

(2) 2 nd comparison period

K₂Is at K₁On the basis of addition or subtraction

Therefore, we only need to adjust on the string of binary values of the 1 st cycle SWA.

Adding

Adjusting SWA<10>I.e. SWA<11>The right bit of (1) becomes 1, and the others do not;

reducing

Adjusting SWA<10>1, while SWA<11>0, others are unchanged;

i.e., the SWA should be 110000000000 'b or 010000000000' b.

(3) 3 rd comparison cycle and thereafter

In the same way, K₂Is at K₁On the basis of plus or minus

Therefore, we need to make adjustments on the basis of the 2 nd cycle SWA.

Adding

Adjusting SWA<9>I.e. SWA<10>The right bit of (1) becomes 1, and the others do not;

reducing

Adjusting SWA<9>1, while SWA<10>Becomes 0, others do not;

thus SWA may be 111000000000 'b or 101000000000' b, 011000000000 'b or 001000000000' b.

The following periods are analogized in turn.

And (3) knotting: the comparison process is carried out under the condition of changing SWA; however, it can be seen that during the comparison, SWA <11:0> has changed by at most two bits compared to the previous cycle (the current cycle corresponds to the number of bits and the previous bit); for example: the 3 rd compare cycle SWA <11:0> is changed from 110000000000 'b to 101000000000' b.

SAR logic implementation

(1) Preliminary control

According to the previous analysis, four control signals SX, SWA, SWB and SWC are shared, wherein the last three control signals are 12-bit signals;

from the above derivation, the first condition can be: the sampling stages SWB and SX are 1, and SWA and SWC are 0; comparison stages SWB and SX are 0, SWA and SWC are in anti-phase with each other.

We can initially derive the following control circuit as shown in fig. 11:

so we currently need two control signals, SWA and SWB; wherein SWB is 1 in the sampling stage and 0 in the comparison stage;

(2) SW _ CTRL logic control (SWA variants)

According to equation (15), in the comparison stage, two bits may need to be changed for each change of SWA <11:0> (the current period corresponds to the bit number and the previous bit); this may be equivalent to the SWA possibly needing to be changed twice per bit (start of this cycle and start of the next cycle). Namely: SWA < N > is constantly required to become 1 in the nth cycle and may be 0 or1 in the (N + 1) th cycle (0 and 1 are determined by comparing results);

SWA <11:0> is a 12-bit binary signal, and each bit control signal can be generated by 12 identical digital circuits (SW _ CTRL). From the above analysis, the SAR logic controller (SW _ CTRL) can be designed as shown in fig. 12:

a total of 12 SW _ CTRL modules which respectively correspond to the outputs SWA <11:0 >; the SR is generated by a shift register, is a pulse signal and is high level only in the corresponding comparison period time; q is the result of the comparison;

for example, fig. 15 shows the signal change for SW _ CTRL <11> with the first comparison result high as shown in fig. 13:

during sampling, SWB is equal to 1, trigger is clear 0, and SR is equal to 0; SWA ═ SWC ═ 0 is obtained;

entering a first period of comparison, wherein SWB is changed from 1 to 0, SR high level comes, and SWA is changed from 0 to 1; the result of the comparison is Q, when the first comparison period is over (namely the second period is over), SR changes from 1 to 0, the falling edge of SR triggers the Q result to be transmitted to an OR gate, and the SWA result is determined by Q (the principle of the following period is the same);

it can be seen that the result of SWA is changed only twice in total, and the 1 st time is fixed to 1, and the second time is determined by the comparison result; and the logic design requirements are met.

(3) The shift register generates pulse signals

Generating a pulse signal of a period in the shift register, and sequentially transmitting the pulse signal to the SW _ CTRL controller cycle by cycle through a clock CLK signal; where CLK is 0 at the time of sampling, which may be implemented by the SX signal and a nor gate, the SR signal is generated as shown in fig. 14:

(4) SAR logic controller

In summary, the SAR logic controller is composed of a shift register and 12 SW _ CTRL modules; the whole module only needs to input an SX signal and a clock signal CLK. The circuit diagram of the controller is as shown in FIG. 15:

V_O1、V_O2timing derivation

Let V_Offset＝V_O1-V_O2Then V is_{Offset_T1}Indicates the first week V_O1、V_O2Difference of (V)_{Offset_T(N)}Indicates the Nth week V_O1、V_O2Difference of (A), in the same way, V_{O1_T1}、V_{O2_T1}Represents the first period V_O1、V_O2Value of (A), V_{O1_T(N)}、V_{O2_T(N)}Indicates the Nth period V_O1、V_O2The value of (c). V can be derived by SAR logic_O1、V_O2Timing sequence value:

(1) in the first period:

(2) the Nth cycle:

if V_{O1_T(N-1)}＞V_{O2_T(N-1)}Then, then

V of Nth comparison period_O1Value of

V of Nth comparison period_O2Value of

If V_{O1_T(N-1)}＜V_{O2_T(N-1)}Then, then

One specific example is given below: AD 2.5V, N12 Vo1 and Vo2

The voltage values for each period when AD 2.5V can be listed as follows:

third column V_O1-V_O2There are two possibilities, depending on the comparison result of AD-Vi for each comparison cycle, to finally calculate V of 12 bits_O1-V_O2Difference, the comparison result determining d_N-1…, d0 (digital output result of input signal analog quantity 2.5V).

The differential voltage-charge scaling SAR _ ADC circuit provided by the invention changes the condition that a DAC in the traditional ADC is single-ended signal line input and uses a large number of unit capacitors, and adopts the differential signal input and voltage-charge scaling method, so that the interference of noise on input signals is greatly reduced, the number of the unit capacitors is also reduced, and the chip area is reduced. The method is suitable for the design and research of the multi-bit high-precision ADC.

Claims (6)

1. A differential input voltage charge-scaling SAR _ ADC, comprising a VREF voltage divider, a capacitive array DAC1, a capacitive array DAC2, a comparator, SAR logic circuitry, and an N-bit register; the capacitor array DAC1 and the capacitor array DAC2 both adopt an A + B bit combined DAC, the high-order part A is subjected to capacitive scaling, the low-order part B is subjected to reference voltage scaling, and N is equal to A + B;

the VREF voltage divider provides voltages for capacitive array DAC1 and capacitive array DAC 2;

the capacitor array DAC1 and the capacitor array DAC2 are connected to differential input signals VREF-AD and AD, wherein VREF is a system reference voltage, and AD is an analog input signal;

the capacitor array DAC1 and the capacitor array DAC2 respectively output N times of voltage values under the control of the SAR logic circuit, the output voltages VO1 and VO2 are subjected to difference comparison through a comparator each time, the comparison result is stored in an N-bit register as a valid bit each time, and the conversion result formed by N times of comparison is output.

2. The differential input voltage charge-scaling SAR _ ADC of claim 1, wherein the capacitor array DAC1 and the capacitor array DAC2 are structurally identical, and the control terminals A, C are wired oppositely;

capacitor array DAC1 includes sampling switch SX, capacitor C0-C (A + B-1), and three-terminal switch S0-S (A + B-1);

one end of a capacitor C0-C (A + B-1) is simultaneously connected with one end of the output port VO1 and one end of the switch SX;

the other end of the switch SX is connected with a voltage V output by a reference voltage VREF voltage divider_REF/2；

The other end of the capacitor C0-C (A + B-1) is respectively and correspondingly connected with a determining end of a three-terminal switch S0-S (A + B-1) in sequence;

GND is simultaneously connected with the A end of the three-terminal switch S (A + B-1) -S (B-1) and the A and B ends of the three-terminal switch S0-S (B-2);

VREF-AD is simultaneously connected with the B terminal of the three-terminal switch S (A + B-1) -S (B-1);

VREF is simultaneously connected with the C terminal of the three-terminal switch S (A + B-1) -S (B);

the C ends of the three-terminal switch S0-S (B-1) are respectively connected with V output by the reference voltage VREF voltage divider in sequence_REF/2^B、V_REF/2^{B -1}、……V_REF/2；

Capacitor array DAC2 includes sampling switch SX, capacitor C0-C (A + B-1), and three-terminal switch S0-S (A + B-1);

one end of a capacitor C0-C (A + B-1) is simultaneously connected with the output port VO2 and one end of a switch SX;

the other end of the switch SX is connected with a voltage VREF/2 output by a reference voltage VREF voltage divider;

the other end of the capacitor C0-C (A + B-1) is respectively and correspondingly connected with a determining end of a three-terminal switch S0-S (A + B-1) in sequence;

GND is simultaneously connected with the C terminal of the three-terminal switch S (A + B-1) -S (B-1) and the C and B terminals of the three-terminal switch S0-S (B-2);

VREF-AD is simultaneously connected with the B terminal of the three-terminal switch S (A + B-1) -S (B-1);

VREF is simultaneously connected with the A terminal of the three-terminal switch S (A + B-1) -S (B);

the A ends of the three-terminal switch S0-S (B-1) are respectively connected with V output by the reference voltage VREF voltage divider in sequence_REF/2^B、V_REF/2^{B -1}、……V_REF/2。

3. The differential input voltage charge-scaling SAR _ ADC of claim 2, wherein the SAR logic circuit comprises a switch shift register and N switch controllers SW _ CTL < i >, i-0, 1, …, N-1;

the switch shift register sequentially generates control signals SR < i > according to the clock signal CLK to drive the corresponding switch controller SW _ CTL < i > to work, and generates control signals for controlling the control end A, B, C of the three-terminal switch S (A + B-1) -S0;

the switch controller SW _ CTL < i > comprises an inverter INV, a flip-flop D1, an OR gate or1 and an NOR gate nor1,

the SR < i > signal is simultaneously connected with the input end of the inverter INV and one input end of the OR gate or 1;

the output end of the inverter INV is connected with the clock input end of the D flip-flop D1;

the Q signal line is connected with a data input end D of a D trigger D1;

the output Q of the D flip-flop D1 is connected with the other input end of the OR gate or 1;

the output end of the OR gate or1 is connected with one input end of the NOR gate nor1 and outputs a control signal SWA < i > for controlling the A control end of the three-terminal switch S (A + B-1) -S0;

the output end of the NOR gate nor1 outputs a control signal SWC < i > for controlling the C control end of the three-terminal switch S (A + B-1) -S0;

the control signals SWB < i > of the B control ends of the three-terminal switches S (A + B-1) -S0 are connected with the other input end of the NOR gate;

a sampling stage: the clock signal CLK is low, SX is 1, SWB is 1, D flip-flop D1 is clear 0, and SR is 0; SWA ═ SWC ═ 0 is obtained;

a comparison stage: the clock signal CLK is a pulse signal, the comparison phase comprises N comparison cycles, and the control end signals SWA < N-1:0> and SWC < N-1:0> of the three-terminal switches S (A + B-1) -S0 of the N comparison cycles are mutually inverse.

4. The differential input voltage charge-scaling SAR _ ADC of claim 3, wherein the data accessed by the Q signal line in each comparison period is the comparison result of the input signal AD and the reference voltage Vi in the nth comparison period, and the reference voltage V corresponding to the ith valid bit_i＝K_nV_REF；n＝N-i；

Wherein K_nThe reference voltage of the nth comparison period is compared with the system reference voltage V_REFThe ratio of (a) to (b);

setting initial sampling voltage as V_REF2, the ratio of the 1 st comparison period

At the nth comparison period, if AD-K_nV_REFIf greater than 0, then

If AD-K_nV_REFIf less than 0, then

5. The differential input voltage charge-scaling SAR _ ADC of claim 4, wherein the control signal SWA < N-1:0> is obtained sequentially in N comparison periods according to the sequence SWA < N-1>, SWA < N-2> … SWA <0> by a successive approximation method;

the SWA <11:0> acquisition process for 12 compare cycles with N-12 is:

1 st comparison period: by

And

the 1 st comparison period SWA can be deduced<11:0>100000000000 'b, where SWA'd is binary SWA<11:0>A converted decimal result;

comparison cycle 2: if AD-K₁V_REFIf greater than 0, then

Adjusting SWA<10>I.e. SWA<11>The right bit of (1) becomes 1, and the others do not; SWA<11:0>＝110000000000’b；

If AD-K₁V_REFIf less than 0, then

Adjusting SWA<10>1, while SWA<11>0, others are unchanged; SWA<11:0>＝010000000000’b；

Cycle 3: if AD-K₂V_REFIf greater than 0, then

Adjusting SWA<9>I.e. SWA<10>The right bit of (1) becomes 1, and the others do not; SWA<11:0>111000000000 'b or 101000000000' b;

if AD-K₂V_REF<0 then

Adjusting SWA<9>1, while SWA<10>Becomes 0, others do not; SWA<11:0>011000000000 'b or 001000000000' b;

and the rest comparison periods are analogized, and then SWA <11:0> of 12 comparison periods is obtained.

6. The differential input voltage charge-scaling SAR _ ADC of claim 5, wherein after N comparison cycles, the capacitor array DAC1 and the capacitor array DAC2 output N voltage differences VO1-VO2 to the comparator respectively, and the comparison result is used as the conversion result d of the input signal AD_N-1,…,d_i,…,d₁,d₀，

In the formula, V_{O1_Ti}Output voltage, V, for ith compare period capacitor array DAC1_{O2_Ti}For the ith compare cycle capacitor array DAC2 output voltage, SWA'd _ Ti is the binary SWA in the ith compare cycle<11:0>A converted decimal result;

if V_{O1_Ti}-V_{O2_Ti}> 0, conversion result d of corresponding bit_iIf 1, if V_{O1_Ti}-V_{O2_Ti}Not more than 0, conversion result d of corresponding bit_i＝0。

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