CN104092466A - Assembly line successive approximation analog-to-digital converter - Google Patents
Assembly line successive approximation analog-to-digital converter Download PDFInfo
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- CN104092466A CN104092466A CN201410298216.0A CN201410298216A CN104092466A CN 104092466 A CN104092466 A CN 104092466A CN 201410298216 A CN201410298216 A CN 201410298216A CN 104092466 A CN104092466 A CN 104092466A
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Abstract
The invention relates to an assembly line successive approximation analog-to-digital converter which can eliminate offset voltage of an allowance amplifier. A capacitor is added to a signal channel between the input end of a comparator and the input end of the allowance amplifier and is used for storing the offset voltage of the allowance amplifier without changing the working principle of a single-level circuit. By means of the assembly line successive approximation analog-to-digital converter, errors which are caused by the offset voltage of the allowance amplifier to the whole circuit can be reduced.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, be specifically related to a kind of streamline gradually-appoximant analog-digital converter.
Background technology
Current, in order to adapt to computer, the digitlization process of the develop rapidly of communication and multimedia technology and high-technology field is constantly accelerated, and ADC has had very large variation on technique, properity, towards low-power consumption, at a high speed, high-resolution future development.Streamline gradually-appoximant analog-digital converter has had both the advantage that conventional flow pipeline analog-to-digital converter and conventional successive are approached analog to digital converter simultaneously, have high accuracy, at a high speed, the feature of low-power consumption.
Surplus amplifier is the nucleus module of streamline gradually-appoximant analog-digital converter, and its performance is directly determining the overall performance of analog to digital converter.Many non-ideal factors of surplus amplifier all can produce error to whole circuit, one of them very important factor is the input offset voltage of amplifier, the output of surplus amplifier is transferred in the closed loop gain that it can be multiplied by amplifier, in whole circuit, produce error, so the elimination of surplus amplifier offset voltage is vital.
A kind of streamline gradually-appoximant analog-digital converter of single-ended input has been proposed in document " Chun C.Lee, A SAR-Assisted Two-Stage Pipeline ADC, IEEE Journal Of Solid-State Circuits; 2011; VOL.46, NO.4, pp.859～869 ".This analog to digital converter one is divided into two-stage, and the resolution of the first order is 6bit, and the resolution of the second level is 7bit.With reference to accompanying drawing 1, provided the schematic diagram of first order circuit.Its operation principle is: the course of work is divided into three phases, sample phase, translate phase and amplification stage.
In sample phase, switch S and switch S P are closed, and switch H disconnects, and in capacitance network, the top crown of all electric capacity meets input signal Vin, the bottom crown ground connection of all electric capacity.The electric charge of storing on electric capacity is:
Q＝2
6C*V
in
At translate phase, switch S, switch S P and switch H disconnect, and in capacitance network, the top crown of all electric capacity selects to receive reference voltage Vref or ground according to the value of digital code di.If di is high level, corresponding electric capacity 2 (6-i) C receives in reference voltage Vref, if di is low level, corresponding electric capacity 2 (6-i) C receives on the ground.The bottom crown of all electric capacity connects comparator input terminal.Now, the electric charge of storing on electric capacity is:
Q'＝(d
12
5C+d
22
4C+......+d
6C)*(V
ref-V
com)+(2
6C-d
12
5C-d
22
4C-......-d
6C)*(0-V
com)
Vcom is the voltage of comparator input terminal, according to law of conservation of charge:
Q＝Q'
Can draw:
V
com＝-V
in+(d
12
-1+d
22
-2+......+d
62
-6)*V
ref
After through six clock cycle, digital code d1 has all quantized to d6, and circuit enters amplification stage.
At amplification stage, switch S and switch S P disconnect, and switch H is closed, in capacitance network the method for attachment of the top crown of all electric capacity the same with translate phase, the bottom crown of all electric capacity is received the negative-phase input of surplus amplifier.The characteristic short according to void, the voltage of amplifier negative-phase input equals the voltage of normal phase input end, and now, the electric charge of storing on electric capacity is:
Q”＝(d
12
5C+d
22
4C+......+d
6C)*(V
ref-0)+(2
6C-d
12
5C-d
22
4C-......-d
6C)*(0-0)+4C*(V
res-0)
According to law of conservation of charge:
Q＝Q”
Can draw:
V
res＝16*[V
in-(d
12
-1+d
22
-2+......+d
62
-6)*V
ref]
Above-mentioned formulation process is not considered the offset voltage of surplus amplifier, suppose that surplus amplifier normal phase input end has an offset voltage Vos, the derivation of sample phase and translate phase and above-mentioned derivation are just the same, but, at amplification stage, the characteristic short according to void, the voltage of amplifier negative-phase input equals the voltage Vos of normal phase input end, so now, the electric charge of storing on electric capacity is:
Q”'＝(d
12
5C+d
22
4C+......+d
6C)*(V
ref-V
os)+(2
6C-d
12
5C-d
22
4C-......-d
6C)*(0-V
os)+4C*(V
res-V
os)
According to law of conservation of charge:
Q＝Q”'
Can draw:
V
res＝16*[V
in-(d
12
-1+d
22
-2+......+d
62
-6)*V
ref]+17V
os
Can find out that single-level circuit that above-mentioned document proposes do not eliminate the offset voltage of surplus amplifier, this offset voltage produces error in residual signal, affects the performance of whole analog to digital converter.
Summary of the invention
The technical problem solving
For fear of the deficiencies in the prior art part, the present invention proposes a kind of streamline gradually-appoximant analog-digital converter that can eliminate surplus amplifier offset voltage.In signal path between comparator input terminal and surplus amplifier in, add an electric capacity, for the offset voltage of memory margin amplifier, and do not change the operation principle of single-level circuit.
Technical scheme
A streamline gradually-appoximant analog-digital converter, comprises M level pipelining-stage circuit, and the resolution of every grade of circuit is Ni position, i=1,2......M; Described pipelining-stage circuit comprises switched capacitor network, comparator and surplus amplifier; Switched capacitor network comprises positive capacitance network and negative capacitance network; It is characterized in that between comparator input terminal and surplus amplifier in, adding an electric capacity, for the offset voltage of memory margin amplifier; Physical circuit is as follows:
The positive capacitance network being connected with comparator normal phase input end is connected with the negative-phase input of surplus amplifier with capacitor C 1 by switch S 3, and the top crown of capacitor C 1 is connected on common mode electrical level Vcm by switch S 5; The negative capacitance network being connected with comparator negative-phase input is connected with the normal phase input end of surplus amplifier with capacitor C 2 by switch S 4, and the top crown of capacitor C 2 is connected on common mode electrical level Vcm by switch S 6; The bottom crown of the negative-phase input of surplus amplifier, capacitor C 3 is connected with the input of switch S 9, the output of the positive output end of surplus amplifier, switch S 9 is connected with the output of switch S 11, the top crown of capacitor C 3 is connected with the input of switch S 11, and the top crown of capacitor C 3 is connected on common mode electrical level Vcm by switch S 7; The bottom crown of the normal phase input end of surplus amplifier, capacitor C 4 is connected with the input of switch S 10, the negative output of surplus amplifier, the output of switch S 10 are connected with the output of switch S 12, the top crown of capacitor C 4 is connected with the input of switch S 12, and the top crown of capacitor C 4 is connected on common mode electrical level Vcm by switch S 8.
Described capacitor C 1 and the size of capacitor C 2 are 2
nic, C is the size of a specific capacitance.
Described capacitor C 3 and the size of capacitor C 4 are C, and C is the size of a specific capacitance.
Beneficial effect
A kind of streamline gradually-appoximant analog-digital converter that the present invention proposes, has reduced the error that the offset voltage due to surplus amplifier produces whole circuit.
Accompanying drawing explanation
The single-level circuit schematic diagram of a kind of streamline gradually-appoximant analog-digital converter proposing in Fig. 1 background technology of the present invention.
A kind of streamline gradually-appoximant analog-digital converter structural representation proposing in Fig. 2 embodiment of the present invention.
The single-level circuit schematic diagram of the analog to digital converter proposing in Fig. 3 embodiment of the present invention.
Embodiment
Now in conjunction with the embodiments, the invention will be further described for accompanying drawing:
The present embodiment is one 13 the overall structure schematic diagrames of enough eliminating the streamline gradually-appoximant analog-digital converter of surplus amplifier offset voltage, as shown in Figure 2.This analog to digital converter comprises altogether level Four, and the first order, the second level, third level structure are identical, all comprise the gradually-appoximant analog-digital converter of a 4bit and the multiplying digital-to-analog converter of a 4bit, and concrete schematic diagram is with reference to shown in accompanying drawing 3.The fourth stage only comprises the gradually-appoximant analog-digital converter of a 5bit.For the Output rusults of first three grade of multiplying digital-to-analog converter preventing from causing due to various non-ideal factors exceeds the input range of next stage, produce uncorrectable error, the multiplication factor of first three grade is reduced to half, being multiplication factor is reduced to 8 by original 16, like this, the folded digital output code that addition is exactly whole analog to digital converter of the digital output code of level Four circuit.
Be the single-level circuit schematic diagram of analog to digital converter as shown in Figure 3, comprise switched capacitor network, comparator and surplus amplifier; Switched capacitor network comprises positive capacitance network and negative capacitance network.Between comparator input terminal and surplus amplifier in, add an electric capacity, for the offset voltage of memory margin amplifier; Physical circuit is as follows: the positive capacitance network being connected with comparator normal phase input end is connected with the negative-phase input of surplus amplifier with capacitor C 1 by switch S 3, and the top crown of capacitor C 1 is connected on common mode electrical level Vcm by switch S 5; The negative capacitance network being connected with comparator negative-phase input is connected with the normal phase input end of surplus amplifier with capacitor C 2 by switch S 4, and the top crown of capacitor C 2 is connected on common mode electrical level Vcm by switch S 6; Capacitor C 1 and capacitor C 2 sizes are 2
nic (C is the size of a specific capacitance), is used for the offset voltage of memory margin amplifier.The bottom crown of the negative-phase input of surplus amplifier, capacitor C 3 is connected with the input of switch S 9, the output of the positive output end of surplus amplifier, switch S 9 is connected with the output of switch S 11, the top crown of capacitor C 3 is connected with the input of switch S 11, and the top crown of capacitor C 3 is connected on common mode electrical level Vcm by switch S 7; The bottom crown of the normal phase input end of surplus amplifier, capacitor C 4 is connected with the input of switch S 10, the negative output of surplus amplifier, the output of switch S 10 are connected with the output of switch S 12, the top crown of capacitor C 4 is connected with the input of switch S 12, and the top crown of capacitor C 4 is connected on common mode electrical level Vcm by switch S 8.The size of capacitor C 3 and capacitor C 4 is C (C is the size of a specific capacitance).
The removing method of surplus amplifier offset voltage will be discussed in detail below.Whole circuit working process is divided into three phases: sample phase, translate phase and amplification stage.
In sample phase, clock Φ 1, Φ 1e, Φ 1f are high level, and clock Φ 2 is low level.Switch S 1, S2, S5, S6, S7, S8, S9, S10 closure, switch S 3, S4, S11, S12 disconnect.In positive capacitance network, the top crown of all electric capacity meets input signal Vip, and bottom crown meets common mode electrical level Vcm.In negative capacitance network, the top crown of all electric capacity meets input signal Vin, and bottom crown meets common mode electrical level Vcm.Capacitor C 1, C2, C3 and C4 have been connected between surplus amplifier in and common mode electrical level Vcm.The electric charge of storing on the electric capacity being connected with A node is:
Q
A＝2
4C*(V
cm-V
ip)
The electric charge of storing on the electric capacity being connected with B node is:
Q
B＝2
4C*(V
cm-V
ip)
The electric charge of storing on the electric capacity being connected with C node is:
Q
C＝C1*(V
cm-V
opa)
Vopa is the common-mode voltage of surplus amplifier in, and the electric charge of storing on the electric capacity being connected with D node is:
Q
D＝C2*[V
cm-(V
opa+V
os)]
The electric charge of storing on the electric capacity being connected with E node is:
Q
E＝C1*(V
opa-V
cm)+C3*(V
opa-V
cm)
The electric charge of storing on the electric capacity being connected with F node is:
Q
F＝C2*(V
opa+V
os-V
cm)+C4*(V
opa+V
os-V
cm)
At translate phase, clock Φ 1, Φ 1e, Φ 1f, Φ 2 are low level.Switch S 1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12 disconnect.In capacitance network, the top crown of all electric capacity is selected to receive on reference voltage Vref p or Vrefn according to the value of digital code di.If the value of di is high level, in positive capacitance network, the top crown of all electric capacity is received reference voltage Vref p above, and in negative capacitance network, the top crown of all electric capacity is received on reference voltage Vref n.If the value of di is low level, in positive capacitance network, the top crown of all electric capacity is received reference voltage Vref n above, and in negative capacitance network, the top crown of all electric capacity is received on reference voltage Vref p.The top crown of capacitor C 1, C2, C3 and C4 is unsettled, and bottom crown connects the input of surplus amplifier.The electric charge of the now upper storage of capacitor C 1, C2, C3 and C4 is constant, and the upper electric charge storing of circuit node C, D, E and F is constant.
The electric charge of storing on the electric capacity being connected with A node is:
Q'
A＝(d
12
3C+d
22
2C+d
32
1C+d
42
0C)*(V
A-V
refp)
+(2
4C-d
12
3C-d
22
2C-d
32
1C-d
42
0C)*(V
A-V
refn)
The electric charge of storing on the electric capacity being connected with B node is:
Q'
B＝(d
12
3C+d
22
2C+d
32
1C+d
42
0C)*(V
B-V
refn)
+(2
4C-d
12
3C-d
22
2C-d
32
1C-d
42
0C)*(V
B-V
refp)
According to law of conservation of charge:
Q
A＝Q'
A
Q
B＝Q'
B
Can draw:
V
A-V
B＝-(V
ip-V
in)+(d
1+d
22
-1+d
32
-2+d
42
-3-1)*(V
refp-V
refn)
After through four clock cycle, digital code d1 has quantized to d4, enters amplification stage.
At amplification stage, clock Φ 1, Φ 1e, Φ 1f are low level, and clock Φ 2 is high level.Switch S 1, S2, S5, S6, S7, S8, S9, S10 disconnect, switch S 3, S4, S11, S12 closure.In capacitance network, the top crown of all electric capacity is selected to receive on reference voltage Vref p or Vrefn according to the value of digital code di, and method of attachment is the same with translate phase.The top crown of capacitor C 1 is received the normal phase input end of comparator, the top crown of capacitor C 2 is received the negative-phase input of comparator, the top crown of capacitor C 3 is received the positive output end of surplus amplifier, the top crown of capacitor C 4 is received the negative output of surplus amplifier, and the bottom crown of capacitor C 1, C2, C3 and C4 connects the input of surplus amplifier.
Due to switch S 3 closures, circuit node A, C connect into a node, and the electric charge of storing on the electric capacity being connected with A, C node is:
Q”
AC＝(d
12
3C+d
22
2C+d
32
1C+d
42
0C)*(V
AC-V
refp)
+(2
4C-d
12
3C-d
22
2C-d
32
1C-d
42
0C)*(V
AC-V
refn)+C1*(V
AC-V
opa)
In like manner, circuit node B, D connect into a node, and the electric charge of storing on the electric capacity being connected with B, D node is:
Q”
BD＝(d
12
3C+d
22
2C+d
32
1C+d
42
0C)*(V
BD-V
refp)
+(2
4C-d
12
3C-d
22
2C-d
32
1C-d
42
0C)*(V
BD-V
refn)+C2*(V
BD-V
opa-V
os)
The electric charge of storing on the electric capacity being connected with E node is:
Q”
E＝C1*(V
opa-V
AC)+C3*(V
opa-V
op)
The electric charge of storing on the electric capacity being connected with F node is:
Q”
F＝C2*(V
opa+V
os-V
BD)+C4*(V
opa+V
os-V
on)
According to law of conservation of charge:
Q
A+Q
C＝Q”
AC
Q
B+Q
D＝Q”
BD
Q
E＝Q”
E
Q
F＝Q”
F
C1＝C2
C3＝C4
Can draw:
Make C1=mC, C3=nC, m>0, n>0, because the multiplication factor of surplus amplifier is 8, so:
So n=1, can obtain m=16 by n=1 substitution above formula, thus C1=C2=16C, C3=C4=C.
Claims (3)
1. a streamline gradually-appoximant analog-digital converter, comprises M level pipelining-stage circuit, and the resolution of every grade of circuit is Ni position, i=1,2......M; Described pipelining-stage circuit comprises switched capacitor network, comparator and surplus amplifier; Switched capacitor network comprises positive capacitance network and negative capacitance network; It is characterized in that between comparator input terminal and surplus amplifier in, adding an electric capacity, for the offset voltage of memory margin amplifier; Physical circuit is as follows:
The positive capacitance network being connected with comparator normal phase input end is connected with the negative-phase input of surplus amplifier with capacitor C 1 by switch S 3, and the top crown of capacitor C 1 is connected on common mode electrical level Vcm by switch S 5; The negative capacitance network being connected with comparator negative-phase input is connected with the normal phase input end of surplus amplifier with capacitor C 2 by switch S 4, and the top crown of capacitor C 2 is connected on common mode electrical level Vcm by switch S 6; The bottom crown of the negative-phase input of surplus amplifier, capacitor C 3 is connected with the input of switch S 9, the output of the positive output end of surplus amplifier, switch S 9 is connected with the output of switch S 11, the top crown of capacitor C 3 is connected with the input of switch S 11, and the top crown of capacitor C 3 is connected on common mode electrical level Vcm by switch S 7; The bottom crown of the normal phase input end of surplus amplifier, capacitor C 4 is connected with the input of switch S 10, the negative output of surplus amplifier, the output of switch S 10 are connected with the output of switch S 12, the top crown of capacitor C 4 is connected with the input of switch S 12, and the top crown of capacitor C 4 is connected on common mode electrical level Vcm by switch S 8.
2. a kind of streamline gradually-appoximant analog-digital converter according to claim 1, is characterized in that described capacitor C 1 and the size of capacitor C 2 are 2
nic, C is the size of a specific capacitance.
3. a kind of streamline gradually-appoximant analog-digital converter according to claim 1, is characterized in that described capacitor C 3 and the size of capacitor C 4 are C, and C is the size of a specific capacitance.
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|---|---|---|---|
| CN201410298216.0A CN104092466B (en) | 2014-06-26 | 2014-06-26 | Assembly line successive approximation analog-to-digital converter |
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|---|---|---|---|
| CN201410298216.0A CN104092466B (en) | 2014-06-26 | 2014-06-26 | Assembly line successive approximation analog-to-digital converter |
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|---|---|---|---|---|
| CN105119603A (en) * | 2015-09-06 | 2015-12-02 | 西北工业大学 | Pipeline successive-approximation analog-to-digital converter |
| CN106888017A (en) * | 2015-12-15 | 2017-06-23 | 财团法人成大研究发展基金会 | Switched-capacitor circuit and its compensation method, analog-digital converter |
| CN107528594A (en) * | 2017-08-25 | 2017-12-29 | 中国电子科技集团公司第二十四研究所 | Charge type streamline gradual approaching A/D converter and its control method |
| CN107896112A (en) * | 2016-10-04 | 2018-04-10 | 联发科技股份有限公司 | Comparator and signal output method |
| CN109217874A (en) * | 2018-11-16 | 2019-01-15 | 深圳锐越微技术有限公司 | Surplus shifts loop, gradual approaching A/D converter and gain calibration methods thereof |
| CN113452371A (en) * | 2020-03-25 | 2021-09-28 | 智原微电子(苏州)有限公司 | Successive approximation temporary storage type analog-digital converter and related control method |
| CN113572475A (en) * | 2021-09-23 | 2021-10-29 | 微龛(广州)半导体有限公司 | Cyclic conversion SAR ADC circuit and SAR ADC method |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105119603A (en) * | 2015-09-06 | 2015-12-02 | 西北工业大学 | Pipeline successive-approximation analog-to-digital converter |
| CN105119603B (en) * | 2015-09-06 | 2018-04-06 | 西北工业大学 | Streamline gradually-appoximant analog-digital converter |
| CN106888017A (en) * | 2015-12-15 | 2017-06-23 | 财团法人成大研究发展基金会 | Switched-capacitor circuit and its compensation method, analog-digital converter |
| CN107896112A (en) * | 2016-10-04 | 2018-04-10 | 联发科技股份有限公司 | Comparator and signal output method |
| CN107528594A (en) * | 2017-08-25 | 2017-12-29 | 中国电子科技集团公司第二十四研究所 | Charge type streamline gradual approaching A/D converter and its control method |
| CN109217874A (en) * | 2018-11-16 | 2019-01-15 | 深圳锐越微技术有限公司 | Surplus shifts loop, gradual approaching A/D converter and gain calibration methods thereof |
| CN109217874B (en) * | 2018-11-16 | 2020-11-17 | 深圳锐越微技术有限公司 | Margin transfer loop, successive approximation type analog-to-digital converter and gain calibration method |
| US11296714B2 (en) | 2018-11-16 | 2022-04-05 | Radiawave Technologies Co., Ltd. | Residue transfer loop, successive approximation register analog-to-digital converter, and gain calibration method |
| CN113452371A (en) * | 2020-03-25 | 2021-09-28 | 智原微电子(苏州)有限公司 | Successive approximation temporary storage type analog-digital converter and related control method |
| CN113452371B (en) * | 2020-03-25 | 2023-07-04 | 智原微电子(苏州)有限公司 | Successive approximation register analog-to-digital converter and related control method |
| CN113572475A (en) * | 2021-09-23 | 2021-10-29 | 微龛(广州)半导体有限公司 | Cyclic conversion SAR ADC circuit and SAR ADC method |
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