CN113595550B - Successive approximation analog-to-digital converter with digital calibration - Google Patents
Successive approximation analog-to-digital converter with digital calibration Download PDFInfo
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- CN113595550B CN113595550B CN202110790055.7A CN202110790055A CN113595550B CN 113595550 B CN113595550 B CN 113595550B CN 202110790055 A CN202110790055 A CN 202110790055A CN 113595550 B CN113595550 B CN 113595550B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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Abstract
The invention belongs to the technical field of digital-to-analog conversion, and discloses a successive approximation analog-to-digital converter with digital calibration, which is characterized in that: the digital calibration circuit is used for mapping K results of 1 in M triggering of the comparator into a probability estimation model of voltage allowance, outputting a digital calibration code, and obtaining a voltage allowance function based on the probability estimation model, wherein the voltage allowance function isWherein G and B are constants, M is the number of comparisons, D [ N ]] i For each output of the comparator.
Description
Technical Field
The invention relates to the technical field of visual digital-to-analog conversion, in particular to a successive approximation analog-to-digital converter with digital calibration.
Background
Analog-to-digital converters (ADCs) are interfaces between analog front ends and digital processing units, the resolution, area of which are important design considerations, and the latest successive approximation register analog-to-digital converters provide a power-efficient solution (< 10 fJ/conversion step) with medium resolution (< 12-bit).
As resolution increases, the input load capacitance and area of conventional binary weighted analog-to-digital converter (Digital to Analog Converter, DAC) arrays in successive approximation register analog-to-digital converters increases exponentially, making good capacitor matching beyond 12-bit resolution more difficult, resulting in a decrease in the effective resolution of the analog-to-digital converter. Successive approximation register analog-to-digital converters with segmented DAC architecture provide an attractive solution in order for the digital converter to achieve high accuracy while having low area overhead and good performance.
In recent years, as CMOS devices enter the nanoscale region, with increased device variability, it has become increasingly difficult to do the dimensions, and calibration techniques are therefore required. Since scaling of CMOS device dimensions provides significant advantages to digital circuits in terms of density, speed, and integration, it is advantageous to advance calibration to the digital domain, and digital calibration techniques have the characteristics of high integration and small area overhead compared to analog calibration techniques. To improve the SNDR of successive approximation register analog-to-digital converters, various types of digital calibration techniques have been proposed, which can be further divided into three main categories:
a digital calibration technique based on digital output correlation injects a pseudorandom noise (Pseudorandom Noise, PN) sequence into an input signal in a superimposed manner, then digitally deletes it from the quantized output, the remainder after deletion being the final digital output, and then the digital structure is bits that are individually correlated to the pseudorandom noise sequence, thereby guiding the subsequent algorithm.
In the method based on differential input, each sample is converted twice, if the output transfer curves of the ADCs are not matched, the difference between the results of the two conversions is non-zero, and if the output transfer curves of the ADCs are completely matched, no difference exists between the results of the two conversions. Since the differential signal in these methods is highly correlated with the input error source, calibration can be achieved with many fewer samples than the PN injection method.
Digital calibration techniques based on probabilistic models require that successive approximation register analog-to-digital converters perform an additional M comparisons after the end of conversion (EOC) in order to use these results for more accurate quantization of the estimated input signal by probabilistic model algorithms. .
Among the three methods, the former two methods modify the structure of the analog-digital converter and have larger time cost, the digital calibration method based on the probability model has the characteristics of portability, no influence on the structure of the analog-digital converter and high speed, however, the range of the voltage margin estimated value obtained by the traditional digital calibration technology based on the probability model is fixed and is irrelevant to resolution, and the estimation precision of residues is limited, so that a new successive approximation type analog-digital converter is urgently designed to overcome the problems.
Disclosure of Invention
In order to solve the above problems, the invention provides a successive approximation analog-to-digital converter with digital calibration, wherein after a successive approximation control logic circuit sends out a termination quantization signal, a comparator is triggered for additional M times, a digital calibration circuit outputs a pre-estimated voltage margin after analyzing the output result of the comparator for M times based on a probability model, and the sum of DAC digital output and the pre-estimated voltage margin is the final output. The calibration of the successive approximation type analog-to-digital converter adopting the segmented DAC is realized by the digital calibration technology based on the probability model, the scheme is simple, the hardware units required by the calibration are effectively reduced, and the noise of the comparator, the capacitance mismatch, the parasitic capacitance and other non-ideal noise are taken into consideration, reflected in the noise and then eliminated at the output end, so that the influence of the noise on the analog-to-digital converter circuit is reduced, and the signal-to-noise distortion ratio of the ADC is improved.
The invention can be realized by the following technical scheme:
the successive approximation analog-to-digital converter with digital calibration comprises a comparator, wherein the positive end of the comparator is connected with the output end of a segmented DAC, the negative end of the comparator is connected with an analog input quantity through a sampling/holding circuit, the output end of the comparator is connected with the input ends of a successive approximation circuit and a digital calibration circuit, the output end of the successive approximation circuit is connected with the input end of the digital calibration circuit and is also connected with an adder together with the output end of the digital calibration circuit, the output of the adder is the digital output quantity of the successive approximation analog-to-digital converter, the digital calibration circuit is used for mapping K results of 1 in M triggering results of the comparator into a probability estimation model of voltage margin to output a digital calibration code,
the voltage margin function obtained based on the probability estimation model isWherein G and B are constants, M is the number of comparisons, D [ N ]] i For each output of the comparator.
Further, the segmented DAC uses one or more bridge capacitors that are fractional capacitors or integer multiples of a unit capacitor.
Further, the device also comprises a clock circuit which is connected with the comparator, the successive approximation circuit and the digital calibration circuit and is used for providing a clock signal.
The beneficial technical effects of the invention are as follows:
(1) Most background pixels are filtered out by using the prediction result of the image segmentation module, so that the number of preset text boxes to be predicted is greatly reduced, and the model efficiency is improved.
(2) And carrying out regression prediction on the datum points on the edges of the preset text box, thereby being beneficial to detecting text areas with arbitrary directions and shapes.
(3) And the data enhancement is performed by using the scale transformation and the space transformation, and the feature with strong expressive power is extracted from the text image by using the feature similarity constraint strategy, so that the robustness of the model to the recognition of the curved text and the low-resolution text image is improved.
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Fig. 1 is a schematic view of the overall structure of the present invention.
Detailed Description
The following detailed description of the invention refers to the accompanying drawings and preferred embodiments.
As shown in fig. 1, the invention provides a successive approximation analog-to-digital converter with digital calibration, comprising a comparator, wherein the positive end of the comparator is connected with the output end of a segmented DAC, the negative end of the comparator is connected with an analog input through a sample/hold circuit, the output end of the comparator is connected with a successive approximation circuit and the input end of a digital calibration circuit, the output end of the successive approximation circuit is connected with the input end of the digital calibration circuit and also connected with an adder, the output of the adder is the digital output quantity of the successive approximation analog-to-digital converter, the digital calibration circuit is used for mapping the K times of trigger results of 1 in the M times of trigger results of the comparator into a probability estimation model of voltage allowance, outputting a digital calibration code,
the voltage margin function obtained based on the probability estimation model isWherein G and B are constants, M is the number of comparisons, D [ N ]] i For each output result of the comparator,
the sample/hold circuit acquires the analog input voltage Vin by a track or hold technique. Ideally, when the sample-and-hold circuit is in a sampling state, the output signal changes along with the change of the input signal by tracking the input signal; when the sample hold circuit is in the hold state, the sample hold circuit receives a hold command to keep the level value of the analog input signal unchanged. From the perspective of charging and discharging the capacitor, when the sampling hold circuit is in the sampling state, the switch is turned on, and the capacitor is charged. Wherein the capacitor charge-discharge speed is related to the capacitor capacitance value, and if the capacitor capacitance value becomes smaller, the capacitor charge-discharge speed is correspondingly increased, when the sample-and-hold circuit is in the hold state, the switch is opened, and the capacitor is slowly discharged, because the switch is opened, the operational amplifier in the integrated circuit is in a high impedance state, and thus the output signal basically maintains the level value of the signal in the hold phase.
The successive approximation circuit is used for controlling digital logic of the SAR ADC, and is used for providing a digital quantization result of Vin for the segmented DAC so as to indicate a capacitor charging and discharging process of the DAC, and meanwhile, N-bit conversion results of an analog input quantity are stored in a register. First, an initialization operation is performed to make the most significant bit(Most Significant Bit, MSB) is equal to the number 1, this code is fed into the segmented DAC, which then provides the analog equivalent voltage of this digital code to the comparator circuit for comparison with the sampled input voltage. If the analog voltage exceeds Vin, the comparator causes the successive approximation circuit to reset the bit; otherwise, the bit remains 1; the same operation as described above is then repeated with the next bit set to 1, and this binary search is continued until such operation is performed for each bit in the successive approximation circuit. The generated code is a digital approximation of the sample-and-hold circuit input Vin, which is ultimately output by the successive approximation circuit at the end of the conversion (End of Conversion, EOC). After the conversion is completed, the comparator is triggered an additional M times to generate digital output D [ N ]] 1 ,D[N] 2 ,...,D[N] M And transmit these digital outputs to a digital calibration circuit.
After calibration starts, the comparator is triggered to input additional M times of results into the digital calibration circuit, the digital calibration circuit collects the comparator results, then a corresponding voltage margin is generated based on the probability model, and the calibration process is finished. The digital calibration mode depends on the formulaWhere f (x) is a function based on a probabilistic model, the purpose is to map K results of 1 out of M triggering results of the comparator to a probabilistic model estimate of a voltage margin, so the choice of f (x) directly affects the accuracy of the digital calibration estimate.
The maximum likelihood estimation method belongs to the frequency school in statistics as one of the methods of parameter estimation. The basic principle is that a random sample is known to meet a specific probability distribution, but unknown parameters exist, the parameter estimation is carried out through repeated experiments for a plurality of times, the result distribution is observed, and the estimated value of the parameters is deduced through the result distribution, so that the maximum likelihood estimation method is applied to a digital calibration technology, and the voltage margin can be effectively estimated.
The invention is based on maximum likelihood estimation method, uses linear fitting technology, and adopts the assumption that the standard deviation of the comparator output isμ＝G(V res -B) to obtain a better estimate of μ, where G and B are the variables to be solved for, as a function of resolution.
The maximum likelihood function found from the hypothesis is,the likelihood function in logarithmic form is +.>Solving for the partial derivative of the log-likelihood function>Let the bias guide be 0, i.e. lnL (G (V res -B)|D[N] i ) =0, the expression that can find the estimated voltage margin is +.>Wherein G and B are constants, M is the comparison frequency, D [ N ] depending on non-ideal characteristics such as comparator noise, capacitance mismatch, parasitic capacitance and the like in the circuit] i For each output result of the comparator, outputting the estimated voltage margin +.>And the sum of the digital outputs of the successive approximation circuit is the final output. Compared with other formulas, the formula has the advantages that the estimated margin voltage range is larger, and the non-ideal characteristic in the circuit can be better estimated and processed from the output end.
The constants G and B in the formula are affected by the following variables: the resolution of the analog-to-digital converter and the supply voltage, thermal noise and other non-ideal characteristics. According to formula V res ＝n th +q1, where n th Is ADC thermal noise, q1 is the quantization noise of the ADC. Since the ideal range of quantization noise isThe ideal range from which the voltage margin can be deduced is [ -LSB, LSB]。
In order to bring the range of the estimated voltage margin close to the ideal range, V res The two boundary values of (2) are as follows:
by solving unknown parameters G and B in the formula, and then substituting the unknown parameters into the formulaWe can get the final expression of the estimated headroom voltage:
in the analysis of boundary conditions, in order to derive boundary conditions, the method comprises the steps ofEqual to 0 or 1, can be +.>Simplified to->Or->Therefore, the final range of the estimated margin voltage is +.>
The above table gives a comparison of four digital calibration schemes.
Compared with majority voting, the algorithm provided by the invention can obtain better estimation by using a finer estimator, thereby obtaining comparisonSign and magnitude information of the filter, whereas bayesian algorithms require a priori knowledge of the probability distribution of the noise distribution. When the noise standard deviation changes along with the change of PVT, the Bayesian algorithm performance is unstable under the changing condition, and the method provided by the invention does not need to know the standard deviation of noise distribution in advance, thereby improving the robustness to PVT change. Compared with the maximum likelihood estimation method, the invention can estimate the residual error range fromIncrease to [ -LSB, LSB]。
Also, the estimation range of the voltage margin by the conventional maximum likelihood estimation method is fixed and independent of resolution. Thus, improvements to SNDR using maximum likelihood estimation may not be considered as an effective solution with improved resolution due to the fixed estimation range of the headroom voltage, limiting the accuracy of the estimation of the headroom voltage. The final range of the estimated residual voltage is
As resolution increases, maximum likelihood estimationThe range of (2) remains unchanged and does not converge, whereas +.>Is closer to the range of the actual voltage margin, and tends to converge. It can be seen that the algorithm adopted in the invention has remarkable advantages in theory compared with the existing digital calibration technology based on the probability model.
The segmented DAC uses one or more attenuation capacitances that are integer multiples of the unit capacitance. The entire DAC array is divided into three sub-arrays, MSB, LMSB, LSB each, with a segmentation ratio of m: n: l. In each subarray, the capacitance value is 2 according to the weight ratioThe principle is set. For attenuation capacitance C a1 The value is set to the equivalent capacitance of all capacitances within the LSB subarray. At the same time, the leftmost capacitor of the LMSB word array is set to C a1 Half of (b), this ensures LSB sub-array and C a1 Is connected with C in series 1 Equivalent. Similarly, C a2 The value of (2) is set to the equivalent capacitance of all capacitances on the left side. Capacitor C corresponding to MSB capacitor sub-array n+1 ～C n+m A capacitance value of 2 i-2 C u The sub-high capacitance array LMSB subarray has n-bit capacitance with capacitance value of 2 i-1 C u . In this structure, the LSB sub-array uses 1-bit LSB segmentation to obtain the best DNL. The capacitance value of the LSB array is C u 。
In addition, the device also comprises a clock circuit which is connected with the comparator, the successive approximation circuit and the digital calibration circuit and is used for providing a clock signal.
It will be appreciated by those skilled in the art that these are merely illustrative and that various changes and modifications can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.
Claims (3)
1. A successive approximation analog-to-digital converter comprising a digital calibration, characterized by: the digital calibration circuit comprises a comparator, wherein the positive end of the comparator is connected with the output end of a segmented DAC, the negative end of the comparator is connected with an analog input quantity through a sampling/holding circuit, the output end of the comparator is connected with the input ends of a successive approximation circuit and a digital calibration circuit, the output end of the successive approximation circuit is connected with the input end of the digital calibration circuit and is also connected with an adder together with the output end of the digital calibration circuit, the output of the adder is the digital output quantity of the successive approximation analog-digital converter, the digital calibration circuit is used for mapping K results of 1 in M triggering results of the comparator into a probability estimation model of voltage allowance, outputting digital calibration codes,
the voltage margin function obtained based on the probability estimation model isWherein G and B are constants, M is the number of comparisons, D [ N ]] i The output result of the comparator is obtained for each time; wherein the method comprises the steps of
Substituting B and G into the voltage margin function to obtain a final expression of the voltage margin function:
2. the successive approximation analog-to-digital converter with digital calibration according to claim 1, wherein: the segmented DAC uses one or more bridge capacitors that are either fractional capacitors or integer multiples of a unit capacitance.
3. The successive approximation analog-to-digital converter with digital calibration according to claim 2, wherein: the device also comprises a clock circuit which is connected with the comparator, the successive approximation circuit and the digital calibration circuit and is used for providing a clock signal.
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