CN114070311A

CN114070311A - Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Info

Publication number: CN114070311A
Application number: CN202010786827.5A
Authority: CN
Inventors: 殷秀梅; 杨培; 白蓉蓉; 韩钢
Original assignee: Beijing Tebang Microelectronic Technology Co ltd
Current assignee: Beijing Tebang Microelectronic Technology Co ltd
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2022-02-18
Anticipated expiration: 2040-08-07
Also published as: CN114070311B

Abstract

The disclosure relates to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter. The circuit is a stage of a pipeline analog-to-digital converter, and comprises: the system comprises an SADC module, an MDAC module (which can internally comprise a redundant DAC), a control and measurement module, a MUX module and a correction module, wherein the MUX module is connected between the SADC module and the MDAC module; the control and measurement module is connected with the MUX module and outputs a first control signal, a second control signal, an enabling signal and a correcting signal; the correction module is connected with the control and measurement module. Under the control of the enable signal, the MUX module outputs a digital signal or a control signal to the switch unit and the correction module; when the MUX module outputs the digital signal, the correction module corrects the output digital signal according to the capacitor mismatch parameter. According to the embodiment of the disclosure, the capacitance mismatch parameter of the pipeline analog-to-digital converter can be obtained and the output digital signal can be corrected, so that the high-precision pipeline analog-to-digital converter is realized with lower circuit complexity.

Description

Analog-to-digital conversion circuit and pipeline analog-to-digital converter

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an analog-to-digital conversion circuit and a pipeline analog-to-digital converter.

Background

The pipeline Analog-to-Digital Converter (ADC) is composed of several stages of modules with similar functions, each module including a sub Analog-to-Digital conversion (SADC) module and a Digital-to-Analog conversion and amplification (MDAC) module, etc.

The precision of the pipeline ADC is closely related to the signal processing precision of the MDAC module, and the working parameters of the MDAC module influence the signal processing precision of the MDAC module. For example, non-idealities in the capacitance matching in the MDAC module have a large impact on the accuracy of the MDAC module. The effect of capacitance mismatch on MDAC output error has two aspects: one is a mismatch term independent of the SADC quantization result, i.e., gain error; the other is a mismatch term related to the SADC quantization result. Both errors can cause the influence of reduction of precision of the pipeline ADC, rising of each subharmonic and the like. In the multi-bit MDAC structure, the mismatch term effect on the quantization result of SADC is more significant. In order to ensure the precision of the pipeline ADC, the capacitance matching precision is required to meet the design requirement.

In the related art, a large design margin (for example, an increase in capacitance area) is generally left, or capacitance compensation is performed by an analog or digital manner. However, increasing the capacitance area increases the input load and the operational amplifier (OPA) load of the pipeline ADC, which not only increases the power consumption of the pipeline ADC, but also significantly increases the design difficulty of other modules such as the sampling switch and the OPA; the adoption of the analog capacitance compensation mode needs a complex switched capacitor network, thereby obviously increasing the complexity of an analog circuit and improving the difficulty of layout; the digital capacitance compensation mode has high requirement on the measurement precision of MDAC capacitance mismatch, a traditional measurement scheme needs to input a plurality of high-precision direct-current voltages to an ADC (analog to digital converter) of a production line, and the test environment cost is high.

Disclosure of Invention

In view of this, the present disclosure provides an analog-to-digital conversion circuit, which can measure and correct a capacitance mismatch error at a low cost, and implement a high-precision pipeline analog-to-digital converter.

According to an aspect of the present disclosure, there is provided an analog-to-digital conversion circuit, the circuit being a stage of a pipelined analog-to-digital converter, the circuit comprising: the device comprises a sub-analog-digital conversion (SADC) module, a digital-analog conversion and amplification (MDAC) module (the interior of the module can comprise a redundant DAC), a control and measurement module, a Multiplexer (MUX) module and a correction module, wherein the input end of the SADC module is used for inputting an analog signal, and the output end of the SADC module is used for outputting a first digital signal after analog-digital conversion; the MUX module is electrically connected between the SADC module and the MDAC module, one input end of the MUX module is used for inputting the first digital signal, the other input end of the MUX module is used for inputting a first control signal, the enable end of the MUX module is used for inputting an enable signal, and the MUX module is used for outputting the first digital signal or the first control signal to the MDAC module according to the enable signal; the MDAC module comprises a capacitor unit and a switch unit, the capacitor unit comprises a plurality of sampling capacitors and a plurality of feedback capacitors, a first input end of the MDAC module is used for inputting the analog signal, a second input end of the MDAC module is electrically connected with an output end of the MUX module, a third input end of the MDAC module is used for inputting a second control signal, and an output end of the MDAC module is used for outputting a residual error signal; the switch unit comprises a plurality of switches, a first end of the switch unit is electrically connected to the output end of the MUX module and is used for inputting the first control signal or the first digital signal, a second end of the switch unit is used for inputting a second control signal, a third end of the switch unit is electrically connected to the capacitor unit, and the switch unit is used for switching according to the second control signal so as to change the electrical connection relation of a plurality of sampling capacitors and/or a plurality of feedback capacitors in the MDAC module; the control and measurement module is electrically connected to the MUX module and the switch unit, a first output end is used for outputting the first control signal, a second output end is used for outputting the enable signal, a third output end is used for outputting a correction signal, a fourth output end is used for outputting the second control signal, and the correction signal is used for representing capacitance mismatch parameters of a plurality of sampling capacitors and a plurality of feedback capacitors of the MDAC module; the correction module is electrically connected to the control and measurement module, one input end of the correction module is electrically connected to the output end of the MUX module or the output end of the SADC module, the other input end of the correction module is used for inputting the correction signal, the correction module is used for correcting the first digital signal according to the correction signal and outputting a corrected second digital signal through the output end, wherein, under the condition that the output end of the MUX module outputs the first control signal, the control and measurement module is used for: and controlling a switch unit to change the connection relation of the plurality of sampling capacitors and/or the plurality of feedback capacitors according to the second control signal at different time periods, determining the capacitor mismatch parameter and generating a correction signal.

In a possible implementation, the capacitance mismatch parameters include a mismatch parameter of each sampling capacitance with respect to any one of the plurality of sampling capacitances or a capacitance average value of the plurality of sampling capacitances, and a mismatch parameter of each feedback capacitance with respect to any one of the plurality of sampling capacitances or a capacitance average value of the plurality of sampling capacitances.

In a possible implementation manner, the circuit further includes an analog-to-digital conversion ADC module, where the ADC module is electrically connected to the MDAC module and the control and measurement module, an input end is used to input the residual error signal, and an output end is used to output a third digital signal obtained by performing analog-to-digital conversion on the residual error signal.

In a possible embodiment, the controlling the switch unit to change the connection relationship of the plurality of sampling capacitors and/or the plurality of feedback capacitors according to the second control signal at different time periods includes: controlling a switch unit according to the second control signal to switch a first number of sampling capacitors in the plurality of sampling capacitors into sampling phases and switch a first number of feedback capacitors in the plurality of feedback capacitors into feedback phases; and/or controlling a switch unit according to the second control signal to switch a first number of sampling capacitors in the plurality of sampling capacitors into feedback phases and switch a first number of feedback capacitors in the plurality of feedback capacitors into sampling phases.

In a possible embodiment, the first number is 1, 2 or more.

In a possible implementation manner, the controlling the switch unit to change the connection relationship between the plurality of sampling capacitors and the plurality of feedback capacitors according to the second control signal at different time periods includes: in a first time period, controlling a switch unit according to the second control signal, switching a switch to connect a first sampling capacitor and a second sampling capacitor to a sampling phase, and connecting a first feedback capacitor and a second feedback capacitor to a feedback phase, wherein the first sampling capacitor and the second sampling capacitor are any two of the plurality of sampling capacitors, and the first feedback capacitor and the second feedback capacitor are any two of the plurality of feedback capacitors; and in a second time period, controlling a switch unit according to the second control signal to switch the first sampling capacitor and the second feedback capacitor into a feedback phase and switch the second sampling capacitor and the first feedback capacitor into a sampling phase, wherein the first time period is not overlapped in the second time period.

In one possible embodiment, the determining the capacitance mismatch parameter includes: receiving a plurality of third digital signals output by the ADC module in a first time period, and determining a first mismatch parameter of a plurality of sampling capacitors relative to a first capacitor in the plurality of sampling capacitors by using the plurality of third digital signals; receiving a plurality of third digital signals output by the ADC module in a second time period, and determining a second mismatch parameter of a plurality of feedback capacitors relative to the first capacitor by using the plurality of third digital signals; determining the capacitive mismatch parameter using the first mismatch parameter and the second mismatch parameter.

In a possible implementation, the MDAC module includes a gain unit, the switch unit includes 3K feedback switches and 3K sampling switches, where K is greater than or equal to 1 and less than or equal to M, K represents the first number, M represents a total number of sampling capacitors, any one of the K sampling capacitors includes 3 corresponding sampling switches, and any one of the K feedback capacitors includes 3 corresponding feedback switches, where: the first ends of K sampling capacitors are electrically connected to the first ends of K feedback capacitors and the negative input end of the gain unit, the second end of any one of the K sampling capacitors is electrically connected to the first ends of the corresponding 3 sampling switches, the second end of any one of the K feedback capacitors is electrically connected to the first ends of the corresponding 3 feedback switches, the second end of the first sampling switch corresponding to the sampling capacitor is electrically connected to the second end of the first feedback switch corresponding to the feedback capacitor, the second end of the second sampling switch corresponding to the sampling capacitor and the second end of the second feedback switch corresponding to the feedback capacitor are electrically connected to the first preset voltage or the second preset voltage, and the second end of the third sampling switch corresponding to the sampling capacitor is electrically connected to the second end of the third feedback switch corresponding to the feedback capacitor and the output end of the gain unit, the positive input end of the gain unit is grounded.

In a possible implementation manner, when the first number K is 2, the sampling capacitor includes a first sampling capacitor and a second sampling capacitor, the feedback capacitor includes a first feedback capacitor and a second feedback capacitor, and the switch unit includes a first feedback switch, a second feedback switch, a third feedback switch, a fourth feedback switch, a fifth feedback switch, a sixth feedback switch, a first sampling switch, a second sampling switch, a third sampling switch, a fourth sampling switch, a fifth sampling switch and a sixth sampling switch, wherein a first end of the first sampling capacitor, a first end of the second sampling capacitor, a first end of the first feedback capacitor and a first end of the second feedback capacitor are electrically connected to the negative input terminal of the gain unit, and a second end of the first sampling capacitor is electrically connected to the first end of the first sampling switch, A first end of a second sampling switch and a first end of a third sampling switch, a second end of the second sampling capacitor is electrically connected to a first end of the fourth sampling switch, a first end of a fifth sampling switch and a first end of a sixth sampling switch, a second end of the first sampling switch is electrically connected to a second end of the fourth sampling switch, a second end of the first feedback switch and a second end of the sixth feedback switch, a second end of the second sampling switch, a second end of the fifth sampling switch, a second end of the second feedback switch and a second end of the fifth feedback switch are electrically connected to a first preset voltage or a second preset voltage, a second end of the third sampling switch and a second end of the sixth sampling switch are electrically connected to a second end of the third feedback switch, a second end of the fourth feedback switch and an output end of the gain unit, a second end of the first feedback capacitor is electrically connected to a first end of the first feedback switch, a first end of the second feedback switch, and a first end of the third feedback switch, and a second end of the second feedback capacitor is electrically connected to a first end of the fourth feedback switch, a first end of the fifth feedback switch, and a first end of the sixth feedback switch.

In a possible implementation manner, the capacitance unit further includes a redundant capacitance, and in the case that the output end of the MUX module outputs the first control signal, the control and measurement module is further configured to: and controlling the switch unit according to the second control signal at different time periods, changing the connection relation of the redundant capacitor, one or more feedback capacitors and one or more sampling capacitors, and determining the capacitor mismatch parameter.

In a possible embodiment, the controlling the switch unit according to the second control signal at different time periods to change the connection relationship of the redundant capacitor, the one or more feedback capacitors and the one or more sampling capacitors includes: and controlling the switch unit according to the second control signal so as to connect a first feedback capacitor and a second feedback capacitor to a feedback phase and connect one end of the redundant capacitor to a first analog voltage, wherein the first feedback capacitor and the second feedback capacitor are any 2 of the plurality of feedback capacitors.

In a possible embodiment, the controlling the switch unit according to the second control signal at different time periods to change the connection relationship of the redundant capacitor, the one or more feedback capacitors and the one or more sampling capacitors includes: controlling the switch unit according to the second control signal to switch the first feedback capacitor and the redundant capacitor into a sampling phase and switch the second feedback capacitor into a feedback phase; and/or controlling the switch unit according to the second control signal to switch the second feedback capacitor and the redundant capacitor into a sampling phase and switch the first feedback capacitor into a feedback phase.

In a possible embodiment, the controlling the switch unit according to the second control signal at different time periods to change the connection relationship of the redundant capacitor, the one or more feedback capacitors and the one or more sampling capacitors includes: and controlling the switch unit according to the second control signal so as to access the first feedback capacitor and the second feedback capacitor to a sampling phase and access the redundant capacitor to a feedback phase.

In one possible embodiment, the MDAC module includes a gain unit, and the switching unit includes a first redundant switch, a second redundant switch, a first feedback switch, a second feedback switch, a third feedback switch, a fourth feedback switch, a fifth feedback switch, and a sixth feedback switch, wherein: the first ends of the redundant capacitors, the first ends of the first feedback capacitors, and the first ends of the second feedback capacitors are electrically connected to the first ends of the sampling capacitors and the negative input end of the gain unit, the second ends of the redundant capacitors are electrically connected to the first ends of the first redundant switch and the first end of the second redundant switch, the second end of the first feedback switch, and the second end of the sixth feedback switch are electrically connected to a first analog voltage, the second ends of the second redundant switch, the second end of the second feedback switch, and the second end of the fifth feedback switch are electrically connected to a first preset voltage or a second preset voltage, the second end of the first feedback capacitor is electrically connected to the first end of the first feedback switch, the first end of the second feedback switch, and the first end of the third feedback switch, a second end of the second feedback capacitor is electrically connected to a first end of the fourth feedback switch, a first end of the fifth feedback switch, and a first end of the sixth feedback switch, a second end of the third feedback switch and a second end of the fourth feedback switch are electrically connected to an output end of the gain unit, and a positive input end of the gain unit is grounded.

In one possible embodiment, the MDAC module includes a gain unit, and the switching unit includes a first redundant switch, a second redundant switch, a first feedback switch, a second feedback switch, a third feedback switch, a fourth feedback switch, a fifth feedback switch, and a sixth feedback switch, wherein: the first ends of the redundant capacitors, the first ends of the first feedback capacitors and the first ends of the second feedback capacitors are electrically connected to the first ends of the sampling capacitors and the negative input end of the gain unit, the second ends of the redundant capacitors are electrically connected to the first ends of the first redundant switch and the first end of the second redundant switch, the second ends of the second redundant switch, the first feedback switch and the sixth feedback switch are electrically connected to a first analog voltage, the second ends of the second feedback switch and the fifth feedback switch are electrically connected to a first preset voltage or a second preset voltage, the second end of the first feedback capacitor is electrically connected to the first end of the first feedback switch, the first end of the second feedback switch and the first end of the third feedback switch, and the second end of the second feedback capacitor is electrically connected to the first end of the fourth feedback switch, A first end of the fifth feedback switch and a first end of the sixth feedback switch, a second end of the first redundant switch, a second end of the third feedback switch, and a second end of the fourth feedback switch are electrically connected to an output end of the gain unit, and a positive input end of the gain unit is grounded.

According to another aspect of the embodiments of the present disclosure, a pipeline analog-to-digital converter is provided, where each stage of the pipeline analog-to-digital converter includes the analog-to-digital conversion circuit.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, the capacitance mismatch parameter of the pipeline analog-to-digital converter can be obtained through the control and measurement module, the first digital signal output by the SADC module is corrected through the correction module, the mismatch of the sampling capacitor and the feedback capacitor is eliminated, and the corrected second digital signal is output, so that the high-precision pipeline analog-to-digital converter is realized with lower circuit complexity.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1a shows a schematic diagram of a first stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter according to the related art.

Fig. 1b and 1c respectively show a circuit configuration diagram of an MDAC module of an analog-to-digital conversion circuit according to the related art and a circuit timing diagram thereof.

Fig. 1d shows a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 2a shows a schematic diagram of an analog-to-digital conversion circuit shown according to an exemplary embodiment of the present disclosure.

Fig. 2b and 2c respectively show a schematic diagram of a circuit structure of an MDAC module of an analog-to-digital conversion circuit and a schematic diagram of a circuit timing sequence thereof according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram illustrating an MDAC module transmission curve of an analog-to-digital conversion circuit according to an exemplary embodiment of the present disclosure.

Fig. 4 shows a schematic diagram of obtaining a capacitance mismatch parameter according to an embodiment of the present disclosure.

Fig. 5 shows a schematic circuit diagram of an MDAC module according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of obtaining a capacitance mismatch parameter according to an embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of obtaining a capacitance mismatch parameter according to an embodiment of the present disclosure.

Fig. 8 shows a schematic circuit diagram of an MDAC module according to an embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of obtaining a capacitance mismatch parameter according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Fig. 1a shows a schematic diagram of a first stage analog-to-digital conversion circuit of a pipeline analog-to-digital converter according to the related art. For example, the pipelined ADC may include several stages of analog-to-digital conversion circuits with similar functions, as shown in fig. 1a, the analog-to-digital conversion circuit 10 according to the related art may include:

a sub-analog-to-digital conversion (SADC) module 101, wherein an initial signal V is input to an input terminal of the SADC module 101_in0The output end outputs a digital signal Dout0 after analog-to-digital conversion; wherein if the first stage analog-to-digital conversion circuit is not adopted, V_in0Is an analog signal provided by a former-stage analog-to-digital conversion circuit;

a digital-to-analog conversion and amplification (MDAC) module 102, the MDAC module 102 being connected to the SADC module 101, an input terminal of which inputs the initial signal V_in0The other input end inputs a digital signal Dout0, and the output end outputs a residual difference signal V_res0。

In one possible implementation, as shown in fig. 1a, the MDAC module 102 may include a digital-to-analog converter (DAC), an adder, and a Gain unit Gain. The input end of the DAC inputs a digital signal Dout0, and the output end of the DAC is connected with one input end of the adder; the other input end of the adder inputs an initial signal V_in0The output end of the Gain unit Gain is connected with the input end of the Gain unit; the output end of the Gain unit Gain outputs a residual signal V_res0。

For example, the initial signal V_in0Simultaneously enters the SADC module 101 and the MDAC module 102, coarse quantization (i.e. preliminary analog-to-digital conversion) is performed in the SADC module 101, for example, 1-4 bits are quantized, and the quantization result (digital signal Dout0) is sent to the MDAC module 102. MDAC module 102 converts the output of SADC module 101 into a different reference voltage, the initial signal V_in0After subtracting the difference signal, the Gain unit Gain amplifies the difference signal by several times to obtain a residual signal V_res0And sending to the next stage for treatment.

In one example, the Gain unit Gain may include an operational amplifier OPA.

In one example, the Gain cell Gain may be a single-ended Gain cell, a differential Gain cell. The following description takes a single-ended gain cell as an example, and so on for a differential gain cell.

Fig. 1b and 1c respectively show a circuit configuration diagram of an MDAC module of an analog-to-digital conversion circuit according to the related art and a circuit timing diagram thereof. Fig. 1d shows a schematic diagram of a transmission curve of an MDAC module of an analog-to-digital conversion circuit according to the related art.

Fig. 1b shows an exemplary specific circuit structure of the MDAC module 102, and fig. 1c shows a clock signal of the MDAC module 102 shown in fig. 1 b. The clock signal may comprise two inverted clocks Φ₁And phi₂Wherein T is_clkIndicating the period of the system clock, C_S0,1-C_S0,nRepresenting the sampling capacitance, n represents the number of sampling capacitances (the number of sampling capacitances n is the same as the number of bits of the digital signal Dout0), C_stg02Representing the sampling capacitance of the second stage, C_F0Representing the feedback capacitance, V_rpAnd V_rnRespectively representing a positive reference voltage and a negative reference voltage.

In one possible implementation, as shown in FIG. 1b, at Φ₁Phase (e.g. phi)₁1/2 clock period T being high_clk)，V_in0Is sampled into each sampling capacitor C_S0,1-C_S0,nIn (1). End of sample (e.g., #)₁Low) is phi₁The respective switches are turned off. Phi₂Phase (e.g. phi)₂1/2 clock period T being high_clk) The switch is closed, at which time each capacitor C_S0,1-C_S0,nThe voltage of the lower plate is controlled by the output signal of the SADC module 101, and V is selected according to the output signal (quantization result) of the SADC module 101_rpOr V_rnThis allows a digital-to-analog conversion in the MDAC, which results in the transmission curve shown in fig. 1 d. The OPA of the operational amplifier in the Gain cell Gain works in a closed-loop negative feedback state, and according to the charge conservation and the working principle of an ideal OPA, the following results can be obtained:

in the formula (1), V_res0Representing the residual signal, V, output by the MDAC module 102_in0Representing the input initial signal, d0_kRepresenting the k-th bit, d0, of the digital signal Dout0 of the SADC module 101_kIs in the range of [ -1, 1 [)]，C_S0,kRepresents the capacitance value of the kth sampling capacitor, k is an integer between 1 and n, C_F0Representing the capacitance value, V, of the feedback capacitor_refRepresenting the full-scale voltage of the pipeline ADC, the input signal range of the pipeline ADC should be [ -V ]_ref，V_ref]Within the range of (1).

The effect of capacitance mismatch on MDAC output error has two aspects: one is a mismatch term independent of the SADC quantization result, i.e. gain error

The other is a mismatch term related to SADC quantization result

Both errors can cause the influence of reduction of precision of the pipeline ADC, rising of each subharmonic and the like. In the multi-bit MDAC structure, the mismatch term effect on the quantization result of SADC is more significant. In order to ensure the precision of the pipeline ADC, the capacitance matching precision is required to meet the design requirement.

However, the related art cannot correct the capacitance mismatch phenomenon, and cannot simultaneously correct the capacitance mismatch between the sampling capacitors and the capacitance mismatch of the feedback capacitor.

Fig. 2a shows a schematic diagram of an analog-to-digital conversion circuit shown according to an exemplary embodiment of the present disclosure. This circuit 40 is any stage of a pipelined ADC. As shown in fig. 2a, the circuit 40 includes: a sub analog to digital conversion SADC module 401, a digital to analog conversion and amplification MDAC module 402, a control and measurement module 405, a multiplexer MUX module 404, and a correction module 403.

Wherein, the input end of the SADC module 401 inputs the analog signal V_inThe output end outputs a first digital signal D after analog-to-digital conversion₁；

The MUX module 404 is connected between the SADC module 401 and the MDAC module 402, and has an input terminal for inputting the first digital signal D₁The other input end inputs a first control signal D_ctrlThe enable end inputs an enable signal Cali _ en, and the MUX module is used for outputting the first digital signal D according to the enable signal Cali _ en₁Or the first control signal D_ctrlTo the MDAC block, for example, when the enable signal Cali _ en is 0, the first digital signal D is gated₁(ii) a When the enable signal Cali _ en is 1, the first control signal D is gated_ctrl. Wherein the first control signal D_ctrlMay be the same as the number of sampling capacitors of the MDAC module 402;

the MDAC module 402 includes a capacitor unit including a plurality of sampling capacitors and a plurality of feedback capacitors (not shown in fig. 2 a), and a switch unit, and a first input terminal of the MDAC module 402 is used for inputting the analog signal V_inA second input end electrically connected to the output end of the MUX module 404, and an output end for outputting a residual signal V_res；

The switch unit comprises a plurality of switches, a first end of the switch unit is electrically connected to the output end of the MUX module and is used for inputting the first control signal or the first digital signal, a second end of the switch unit is used for inputting a second control signal Cali _ sel, a third end of the switch unit is electrically connected to the capacitor unit, and the switch unit is used for switching according to the second control signal Cali _ sel so as to change the electrical connection relationship of the plurality of sampling capacitors and/or the plurality of feedback capacitors in the MDAC module 402;

the control and measurement module 405 is electrically connected to the MUX module 404 and the switch unit, and a first output end is used for outputting the first control signal D_ctrlOf 1 atTwo output ends are used for outputting the enable signal Cali _ en, and a third output end is used for outputting a correction signal D₄A fourth output terminal for outputting the second control signal, the correction signal D₄A capacitance mismatch parameter for characterizing a plurality of sampling capacitances and a plurality of feedback capacitances of the MDAC module 402;

the calibration module 403 is electrically connected to the control and measurement module 405, one input end of the calibration module 403 is electrically connected to the output end of the MUX module 404 or the output end of the SADC module 401, and the other input end is used for inputting the calibration signal D₄The correction module 403 is configured to correct the signal D according to the correction signal₄For the first digital signal D₁Correcting and outputting the corrected second digital signal D via the output terminal₂，

Wherein the first control signal D is output at the output terminal of the MUX module 404_ctrlIn case of (2), the control and measurement module 405 is configured to:

and controlling a switch unit to change the connection relation of the plurality of sampling capacitors and/or the plurality of feedback capacitors according to the second control signal Cali _ sel at different time periods, determining the capacitor mismatch parameter and generating a correction signal.

Fig. 2b shows an exemplary specific circuit structure of the MDAC module 402, and fig. 2c shows a clock signal of the MDAC module 402 shown in fig. 2 b.

In one example, the MDAC module in the related art may be improved to obtain an MDAC module as shown in fig. 2 b. The clock signal may comprise two inverted clocks Φ₁And phi₂Wherein T is_clkIndicating the period of the system clock, C_S0,1-C_S0,nRepresenting the sampling capacitances, n representing the number of sampling capacitances (the number n of sampling capacitances is the same as the number of bits of the first digital signal D1), C_stg02Representing the sampling capacitance of the second stage, C_F0,1And C_F0,2Representing the feedback capacitance, V_rpAnd V_rnRespectively representing a positive reference voltage and a negative reference voltage.

In one possible implementation manner, the controlling the switch unit to change the connection relationship of the plurality of sampling capacitors and/or the plurality of feedback capacitors according to the second control signal at different time periods may include:

controlling a switch unit according to the second control signal to switch a first number of sampling capacitors in the plurality of sampling capacitors into sampling phases and switch a first number of feedback capacitors in the plurality of feedback capacitors into feedback phases; and/or

And controlling a switch unit according to the second control signal so as to switch a first number of sampling capacitors in the plurality of sampling capacitors into feedback phases and switch a first number of feedback capacitors in the plurality of feedback capacitors into sampling phases.

In a possible embodiment, the above control manner may be performed in a first time period and a second time period respectively, for example, the switch unit may be controlled according to the second control signal in the first time period to switch a first number of sampling capacitors in the plurality of sampling capacitors into a sampling phase and a first number of feedback capacitors in the plurality of feedback capacitors into a feedback phase; and controlling a switch unit according to the second control signal in a second time period to switch a first number of sampling capacitors in the plurality of sampling capacitors into feedback phases and switch a first number of feedback capacitors in the plurality of feedback capacitors into sampling phases, wherein the first time period is not overlapped in the second time period.

It should be noted that, in the embodiments of the present disclosure, the descriptions of the "first time period", "second time period", "nth time period", etc. are provided to distinguish different time periods, and the sequence of the time periods is not limited in the embodiments of the present disclosure.

In a possible embodiment, the first number is 1, 2 or more.

For example, the exchange position of one sampling capacitor of the plurality of sampling capacitors and the first feedback capacitor of the plurality of feedback capacitors may be set to implement the determination of the parameter, or the exchange positions of two sampling capacitors of the plurality of sampling capacitors and two feedback capacitors of the plurality of feedback capacitors may be set to implement the determination of the parameter.

In a possible implementation manner, the number of switches in the switch unit can be set according to different capacitance number configurations, so as to realize position exchange of the feedback capacitance and the sampling capacitance.

In a possible implementation manner, the switch unit may include a plurality of switches, as shown in fig. 2b, a switch may be added to the lower plate of the sampling capacitor and the feedback capacitor, and a control signal of the original switch may be changed. It should be noted that the embodiment of the present disclosure does not limit the type of the switch, and a person skilled in the art can select an appropriate switch according to needs and practical situations.

In one example, as shown in fig. 2b, a plurality of feedback capacitors may be provided (fig. 2b takes two feedback capacitors as an example, and may also take 1 feedback capacitor, or more than 2 feedback capacitors).

In one example, the switch unit may include 3K feedback switches and 3K sampling switches, where K is greater than or equal to 1 and less than or equal to M, K represents the first number, M represents a total number of sampling capacitors, any one of the K sampling capacitors includes 3 corresponding sampling switches, and any one of the K feedback capacitors includes 3 corresponding feedback switches, where:

the first ends of the K sampling capacitors are electrically connected to the first ends of the K feedback capacitors and the negative input end of the gain unit,

the second end of any one of the K sampling capacitors is electrically connected with the first ends of the corresponding 3 sampling switches, the second end of any one of the K feedback capacitors is electrically connected with the first ends of the corresponding 3 feedback switches,

the second end of the first sampling switch corresponding to the sampling capacitor is electrically connected to the second end of the first feedback switch corresponding to the feedback capacitor, the second end of the second sampling switch corresponding to the sampling capacitor and the second end of the second feedback switch corresponding to the feedback capacitor are electrically connected to a first preset voltage or a second preset voltage, the second end of the third sampling switch corresponding to the sampling capacitor is electrically connected to the second end of the third feedback switch corresponding to the feedback capacitor and the output end of the gain unit,

the positive input end of the gain unit is grounded.

For example, when K is 2, a first feedback capacitor C may be provided_F0,1And a second feedback capacitor C_F0,2(the capacitance value of each feedback capacitor is close to or equal to C) and a plurality of switches are inserted inside the MDAC module, including, for example, a first feedback switch SWf1, a second feedback switch SWf2, a third feedback switch SWf3, a fourth feedback switch SWf4, a fifth feedback switch SWf5, and a sixth feedback switch SWf 6.

A first sampling capacitor C comprising the following sampling capacitors_S0,1A second sampling capacitor C_S0,2The description is given for the sake of example.

In an example, as shown in fig. 2b, the switch unit may further include a first sampling switch SWs1, a second sampling switch SWs2, a third sampling switch SWs3, a fourth sampling switch SWs4, a fifth sampling switch SWs5 and a sixth sampling switch SWs6, and of course, other sampling capacitors may be provided corresponding to the sampling switches, and only the first sampling capacitor C is used here_S0,1A second sampling capacitor C_S0,2By way of example, the disclosure is not so limited.

In one example, as shown in FIG. 2b, the first sampling capacitor C_S0,1The first terminal of (C), the second sampling capacitor C_S0,2First terminal of, the first feedback capacitance C_F0,1First terminal of, the second feedback capacitance C_F0,2Is electrically connected to the negative input terminal of the gain cell (operational amplifier OPA), the positive input terminal of the gain cell is grounded,

the first sampling capacitor C_S0,1Is electrically connected to a first terminal of the first sampling switch SWs1, a first terminal of the second sampling switch SWs2, a first terminal of the third sampling switch SWs3,

the second sampling capacitor C_S0,2Is electrically connected to a first terminal of the fourth sampling switch SWs4, a first terminal of the fifth sampling switch SWs5, a first terminal of the sixth sampling switch SWs6,

a second terminal of the first sampling switch SWs1 is electrically connected to a second terminal of the fourth sampling switch SWs4, a second terminal of a first feedback switch SWf1, and a second terminal of a sixth feedback switch SWf6,

a second terminal of the second sampling switch SWs2, a second terminal of the fifth sampling switch SWs5, a second terminal of the second feedback switch SWf2, and a second terminal of the fifth feedback switch SWf5 are electrically connected to a first preset voltage V_rpOr a second predetermined voltage V_rn，

A second terminal of the third sampling switch SWs3 and a second terminal of the sixth sampling switch SWs6 are electrically connected to a second terminal of the third feedback switch SWf3, a second terminal of the fourth feedback switch SWf4 and an output terminal of the gain unit,

the first feedback capacitor C_F0,1Is electrically connected to a first terminal of the first feedback switch SWf1, a first terminal of the second feedback switch SWf2, a first terminal of the third feedback switch SWf3,

the second feedback capacitor C_F0,2Is electrically connected to the first end of the fourth feedback switch SWf4 and the first end of the fifth feedback switch SWf5A first terminal of the sixth feedback switch SWf 6.

Of course, the first number K may also be 1, for example, the feedback capacitors may only include the first feedback capacitor, and the sampling capacitors may only select the first sampling capacitor for determining the parameter.

Of course, the first number K may be other (for example, greater than 2), and the embodiment of the disclosure is not limited thereto.

Under different first numbers, a corresponding number of feedback switches and sampling switches may be configured according to the number of feedback capacitors and the number of sampling capacitors, as shown in fig. 2 b.

In a possible embodiment, the switch unit is controlled according to the second control signal to switch the first sampling capacitor C_S0,1A second sampling capacitor C_S0,2A sampling phase is switched in, and a first feedback capacitor C is connected_F0,1A second feedback capacitor C_F0,2An access feedback phase, which may include:

in a first time period, the third and sixth sampling switches SWs3 and SWs6 are turned off according to the second control signal, the first and fourth sampling switches SWs1 and SWs4 are turned on in a first phase (for example, phase Φ 1) and turned off in a second phase (for example, phase Φ 2), and the second and fifth sampling switches SWs2 and SWs5 are turned on in the second phase and turned off in the first phase, so as to turn off the first sampling capacitor C_S0,1The second sampling capacitor C_S0,2Switching on a sampling phase, switching off the first feedback switch SWf1, the second feedback switch SWf2, the fifth feedback switch SWf5 and the sixth feedback switch SWf6 according to the second control signal, and switching on the third feedback switch SWf3 and the fourth feedback switch SWf4 to switch on the first feedback capacitor C_F0,1The second feedback capacitor C_F0,2Connecting a feedback phase;

in a possible embodiment, the control unit controls the switch unit according to the second control signal to switch the first sampling capacitor C_S0,1The second sampling capacitor C_S0,2A feedback phase is connected to the second feedback capacitor C_F0,2And saidA first feedback capacitor C_F0,1Accessing a sampling phase may include:

in a second time period, the third and sixth sampling switches SWs3 and SWs6 are turned on and the first, second, fourth and fifth sampling switches SWs1, SWs2 and SWs4 and SWs5 are turned off according to the second control signal to turn off the first sampling capacitor C_S0,1The second sampling capacitor C_S0,2A feedback phase is switched on, the third feedback switch SWf3 and the fourth feedback switch SWf4 are switched off according to the second control signal, the first feedback switch SWf1 and the sixth feedback switch SWf6 are switched on in a first phase and switched off in a second phase, the second feedback switch SWf2 and the fifth feedback switch SWf5 are switched on in the second phase and switched off in the first phase, and the first feedback capacitor C is switched on_F0,1The second feedback capacitor C_F0,2And accessing a sampling phase.

In summary, in the test phase, the embodiments of the present disclosure may connect the first feedback capacitor and the second feedback capacitor to the sampling phase through respective switches, and any two of the plurality of sampling capacitors (e.g., C) may be connected through the switch units (switch SWs1, switch SWs2, switch SWs3, switch SWs4, switch SWs5 and switch SWs6)_S0,1And C_S0,2) Connected to the feedback phase. Through the design, the lower plate switches of the feedback capacitor and the sampling capacitor can be switched through the second control signal, so that the positions of the sampling capacitor and the feedback capacitor in the feedback phase and the sampling phase are interchanged, and the capacitor mismatch between the sampling capacitor and the feedback capacitor is tested.

When the circuit is in the normal operation mode, the output terminal of the MUX module 404 outputs the first digital signal D₁The first digital signal D is input to an input terminal of the calibration module 403₁The output end outputs a second digital signal D₂。

In one example, the correction module 403 may also be connected to an output of the SADC module 401, directly inputting the first digital signal D₁The output end outputs a second digital signal D₂。

Correcting dieBlock 403 may be based on the calibration signal D output by the control and measurement module₄Or stored capacitance mismatch parameter versus first digital signal D₁Correcting to output corrected second digital signal D₂。

A possible implementation of obtaining the capacitance mismatch parameter will be exemplarily described below.

In one possible implementation, the capacitance mismatch parameter of the analog-to-digital conversion circuit may be determined by a calibration test. The MUX module 404 may be controlled by the control and measurement module 405 such that the MUX module 404 outputs the first control signal D during the test mode_ctrlAnd during the calibration test, the control and measurement module 405 may output a second control signal Cali _ sel to switch the switches of the lower plates of the sampling capacitors and the feedback capacitors.

In one possible implementation, when the output terminal of the MUX module 404 outputs the first control signal D_ctrlTime, analog signal V_inSwitched to the first analog voltage, and the control and measurement module 405 controls the voltage according to the control signal D_ctrlAnd a third digital signal D₃Determining a capacitance mismatch parameter and generating a correction signal D comprising the capacitance mismatch parameter₄. Wherein, the first analog voltage may be at a zero level.

In the correction test, the analog signal V input to the analog-to-digital conversion circuit may be input_inShort-circuited to zero level (first analog voltage). Considering the DC offset at the input of an operational amplifier (OPA), the actual input analog signal V_inIt will be a static voltage close to zero level.

Fig. 3 is a schematic diagram illustrating an MDAC module transmission curve of an analog-to-digital conversion circuit according to an exemplary embodiment of the present disclosure. As shown in the transmission curve of fig. 3, the analog signal V_inCan be divided into intervals of-4, -3, -2, -1, 0, 1, 2, 3, 4 and the like. Wherein, for the first stage analog-to-digital conversion circuit, the analog signal V_inNamely zero level; if not, the analog signal V is_inIs an analog signal (residual signal V) output by the previous stage analog-to-digital conversion circuit_res) The analog signal may be due to the presence of a preceding stageDc mismatch produces an offset.

In a possible implementation, the first control signal D_ctrlThe device comprises a plurality of digital signals which are sequentially output, and the number of the digital signals is the same as that of sampling capacitors of the MDAC module.

In one possible implementation, the sum of the digits of the normalized control signal is in the same interval as the value of the normalized analog signal.

During the calibration test, the control and measurement module 405 may generate a plurality of digital signals sequentially output through an internal state machine as the first control signal D_ctrlAnd (6) outputting. The number of digital signals may be greater than or equal to the number of bits of the first control signal (i.e., the number of sampling capacitors in the MDAC module 402) in order to enable the calculation of the capacitance mismatch parameter. For example, the first control signal D_ctrlThere are m digital signals D_ctrl，jWherein j takes the value of 1-m, m>1; each digital signal D_ctrl，jComprising an n-bit number d_ijWherein i takes the value of 1-n, n>1, and m is more than or equal to n.

As mentioned above, the analog signal V actually input by the first stage analog-to-digital conversion circuit_inIt will be a static voltage close to zero level. In this case, to ensure that the MDAC module 402 has a minimal effect on the measurement accuracy, the first control signal D_ctrl，jThe value of each digit of (A) is required to ensure the residual signal V_resAs close to 0V as possible (e.g., V may be made_resLess than or equal to 0.5V). Therefore, the signal input by the ADC module of the next stage is also in the range close to 0V, so that the linearity and the precision of the ADC module of the next stage are better.

In this case, the normalized first control signal D may be made_ctrl，jEach digit of (d)_ijSum of (1)_j(d_ij) With the normalized analog signal V_inWithin the same interval. For the first stage analog-to-digital conversion circuit, the analog signal V_inI.e. the quiescent voltage close to zero level, sum of the stage_j(d_ij) Can take the value of 0 and the normalized analog signal V_inIn the same interval, thereby ensuring the optimal working state of the MDAC module; if not the first stage analog to digital conversion circuit, there may be an input offset (residual signal V)_resOffset), normalized analog signal V_inPossibly in the

interval

1, 0 or-1 of FIG. 3, then sum of the stage_j(d_ij) The value can be correspondingly set to 1, 0 or-1, thereby ensuring the optimal working state of the MDAC module.

According to the circuit structure of the MDAC module, and the residual difference signal is compared with the reference voltage (full-amplitude input voltage) V_refBy performing the normalization, the following formula (2) can be obtained:

in the formula (2), V_res，jIndicating that the control signal is D_ctrl，jResidual signal, V, output by time MDAC module 402_inRepresenting an input analogue signal, d_ijRepresenting a digital signal D_ctrl，jI is an integer of 1 to n, d_ijIs in the range of [ -1, 1 [)]，C_S,iRepresenting the capacitance value of the ith sampling capacitor (e.g. sampling capacitor C)_S0,iMay be represented as C_S,i)，C_F,iIndicating the capacitance of the ith feedback capacitor (e.g. feedback capacitor C)_F0,iMay be represented as C_F,iSize is, for example, C), V_refRepresents the full input voltage (e.g., 1V) of the pipelined ADC;

in the formula (2), the first and second groups,

the dc gain a and the capacitance mismatch of the OPA can be expressed as the influence coefficients on the transmission characteristics of the stage.

As shown in fig. 2a, in one possible implementation, the circuit 40 may further include an analog-to-digital conversion ADC module 406, where the ADC module 406 is connected to the MDAC module 402 and the control and measurement module 405, and the input end of the ADC module 406 inputs the residual difference signal V_resAnd the output end outputs a third digital signal D after analog-to-digital conversion₃；

Wherein, the input end of the control and measurement module 405 inputs a third digital signal D₃。

For example, the ADC module 406 may be used to correct the residual signal V_resQuantization (analog-to-digital conversion) is performed to obtain a third digital signal D₃Is inputted into the control and measurement module 405 so that the control and measurement module 405 is based on the third digital signal D₃Calculating the capacitor mismatch parameter and generating a correction signal D₄。

In one possible implementation, the ADC module 406 may include an SADC module 401 of a next stage analog-to-digital conversion circuit of the pipeline analog-to-digital converter. That is, when the currently tested analog-to-digital conversion circuit is not the last stage of the pipeline ADC, the ADC module 406 may multiplex the SADC module 401 of the next stage analog-to-digital conversion circuit, and if the current analog-to-digital conversion circuit is not the last stage of the pipeline ADC, the ADC module 406 may multiplex the SADC module 401 of the next stage analog-to-digital conversion circuit, and may also use the whole of each stage after the current stage of the pipeline ADC as the ADC module 406, so as to implement the compensation signal V_resQuantization of (2); if the current analog-to-digital conversion circuit is the last stage of a pipelined ADC, a separate ADC block 406 may be employed to implement the residual signal V_resQuantization of (2). ADC module 406 may also be added to each stage of the analog-to-digital conversion circuit of the pipelined ADC, which is not limited by this disclosure.

Due to the third digital signal D₃I.e. residual signal V_resIf m residual signals V exist as the quantization result of (1)_res，jIn this case, equation (2) can be expressed as:

in the formula (3), D_3，jRepresenting the residual signal V_res，jThe quantized digital signal (third digital signal).

In a possible implementation manner, when the output end of the MUX module outputs the first control signal, the control and measurement module may determine the capacitance mismatch parameter according to the control signal and the third digital signal.

In a possible implementation manner, the controlling, according to the second control signal, the connection relationship of the plurality of sampling capacitors and/or the plurality of feedback capacitors of the switching unit at different time periods may include:

as shown in fig. 2b, in a first time period, controlling a switch unit according to the second control signal to switch a first sampling capacitor and a second sampling capacitor into a sampling phase and switch a first feedback capacitor and a second feedback capacitor into a feedback phase, where the first sampling capacitor and the second sampling capacitor are any two of the plurality of sampling capacitors, and the first feedback capacitor and the second feedback capacitor are any two of the plurality of feedback capacitors;

and in a second time period, controlling a switch unit according to the second control signal so as to switch the first sampling capacitor and the second sampling capacitor into a feedback phase and switch the second feedback capacitor and the first feedback capacitor into a sampling phase.

Wherein the first time period does not overlap in the second time period.

In one example, the second control signal Cali _ sel may include the first period

Referring to fig. 2b, in the first time period, under the action of the second control signal, the switch SWs3 and the switch SWs6 are turned off, the switch SWs1 and the switch SWs4 are turned on in the phase Φ 1, turned off in the phase Φ 2, the switch SWs2 and the switch SWs5 are turned on in the phase Φ 2, and turned off in the phase Φ 1, so that the first sampling capacitor C is sampled_S0,1Second sampling capacitor C_S0,2Switching in a sampling phase, switching SWf1, switching SWf2, switching SWf5 and switching SWf6 are switched off, switching SWf3 and switching SWf4 are switched on, and a first feedback capacitor C_F0,1And a second feedback capacitor C_F0,2And switching in a feedback phase.

In one example, the second control signal may be during the second time period

Referring to fig. 2b, in the second time period, under the effect of the second control signal, the switches SWs3 and SWs6 are turned on, the switches SWs1, SWs2, SWs4 and SWs5 are turned off, and the first sampling capacitor C is turned on_S0,1Second sampling capacitor C_S0,2The feedback phase is switched on, the switches SWf3 and SWf4 are switched off, the switches SWf1 and SWf6 are switched on in the phase phi 1 and switched off in the phase phi 2, the switches SWf2 and SWf5 are switched on in the phase phi 2 and switched off in the phase phi 1, and the first feedback capacitor C is connected with the first feedback capacitor C_F0,1And a second feedback capacitor C_F0,2And accessing a sampling phase.

In the test phase (the first time period and the second time period), the enable signal of the control and measurement module 405 changes (for example, the enable signal Cali _ en is 1), and the control signal D is gated_ctrl. In this case, the control and measurement module 405 may generate a plurality of digital signals D sequentially output through a state machine therein_ctrl，j(j takes a value of 1-m) and inputs it into the MDAC module 402. Wherein each digital signal D_ctrl，jThe output is held for a certain time. At different time periods, the digital signal D_ctrl，_jIt should be understood that the time of each time period can be preset according to actual needs, and the disclosure does not limit this.

In one possible embodiment, the determining the capacitance mismatch parameter includes:

receiving a plurality of third digital signals output by the ADC module in a first time period, and determining a first mismatch parameter of a plurality of sampling capacitors relative to a first capacitor in the plurality of sampling capacitors by using the plurality of third digital signals;

receiving a plurality of third digital signals output by the ADC module in a second time period, and determining a second mismatch parameter of a plurality of feedback capacitors relative to the first capacitor by using the plurality of third digital signals;

determining the capacitive mismatch parameter using the first mismatch parameter and the second mismatch parameter.

In one example, during a first time period, the current is output at the MUX module 404Digital signal D_ctrl，jMeanwhile, the MDAC module 402 outputs a corresponding residual signal V_res，jThe ADC module 406 then processes the residual signal V_res，jQuantizing to obtain quantized third digital signal D_3，j。

In a possible implementation manner, the control and measurement module 405 may measure the third digital signal output by the ADC module 406 for multiple times to obtain multiple measurement signal values; further, an average value of a plurality of measurement signal values may be obtained, and the average value may be used as a final measurement signal (third digital signal D)_3，j). In this way, the accuracy of the measurement signal can be improved.

In one example, at the time of test, for a plurality of digital signals D sequentially output_ctrl，j(j takes a value of 1 to m), and can be applied to each digital signal D_ctrl，jThe measurements were performed separately. If the number of the measured digital signals is less than the total number (m) of the digital signals, not completing the measurement of all the digital signals; if the number of the measured digital signals has reached the total number of the digital signals (m), the measurement of all the digital signals has been completed. By measuring cyclically, a plurality of digital signals D output in sequence can be measured_ctrl，j(j takes a value of 1 to m) are measured separately, so the control and measurement module 405 can acquire m control signals D_ctrl，jCorresponding m measurement signals (third digital signal D)_3，j) And can be based on m first control signals D_ctrl，jAnd m third digital signals D_3，jA capacitance mismatch parameter is determined.

The following is a pipelined ADC with an effective precision of 2-bit, where m is 8 and the sampling capacitor C_S,iThe capacitance nominal value of C is taken as an example to illustrate a specific calculation manner of the capacitance mismatch parameter of the analog-to-digital conversion circuit according to the present disclosure.

Determining a first mismatch parameter of the plurality of sampling capacitances with respect to a first capacitance of the plurality of sampling capacitances during the first time period using the plurality of third digital signals will be exemplarily described below.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating obtaining a capacitance mismatch parameter according to an embodiment of the disclosure.

As shown in fig. 4, during the first period of time, the control and measurement module may set the second control signal Cali _ sel to 1, i.e., Φ_sel＝1，Φ_selWhen the number of the switches SWs1 to SWs6 and SWf1 to SWf6 is 0, the first sampling capacitor C is turned on or off_S0,1A second sampling capacitor C_S0,2A sampling phase is switched in, and a first feedback capacitor C is connected_F0,1A second feedback capacitor C_F0,2The feedback phase is switched in, i.e. in this case the first sampling capacitor C_S0,1A second sampling capacitor C_S0,2For sampling the capacitor, a first feedback capacitor C_F0,1A second feedback capacitor C_F0,2Is a feedback capacitance.

According to the capacitor mismatch test plan, 8 groups of first control signals D can be set in sequence_ctrl，j(1. ltoreq. j. ltoreq.8) as shown in Table 1:

TABLE 1

In one possible implementation, the first control signal D may be made_ctrl，jEach digit of (d)_ijValues are sequentially taken according to the table 1 and substituted into the formula (3), so that the following can be obtained:

in practical circuits, the operational amplifier has a DC gain A>>1, thus having K _A1, and C_S,iC, so that:

in one example, as shown in fig. 4, in the second period of time, the second control signal may be set to 0, i.e., Φ_sel＝0，

Therefore, the on-off of the switches SWs 1-SWs 6 and the switches SWf 1-SWf 6 are controlled to connect the first sampling capacitor C_S0,1And a second sampling capacitor C_S0,2A feedback phase is connected to the first feedback capacitor C_F0，₁And a second feedback capacitor C_F0，₂The sampling phase is switched in, i.e. in this case the first sampling capacitor C_S0,1And a second sampling capacitor C_S0,2As a feedback capacitor, a first feedback capacitor C_F0，1And a second feedback capacitor C_F0，2Is the sampling capacitance.

In the second period of time, equation (3) may be expressed as

Wherein,

according to the capacitor mismatch test plan, 3 sets of the first control signals D can be sequentially set_ctrl，j(9. ltoreq. j. ltoreq.11), as shown in Table 2:

TABLE 2

In one possible implementation, the control signal D may be made_ctrl，jEach digit of (d)_ijValues are sequentially taken according to the table 2 and substituted into the formula (6), so that the following can be obtained:

in practical circuits, the operational amplifier has a DC gain A>>1, thus there is K'_A1, and C_S,iC', so that:

according to the formula (4), the formula (5), the formula (7) and the formula (8), the sampling capacitance C can be obtained_S0,iAnd a feedback capacitor C_F0,iRatio B relative to the average of all sampled capacitances_iAnd the ratio B can be determined_iAs a sampling capacitor C_S0,iAnd a feedback capacitor C_F0,iThe capacitance mismatch parameter of (a).

It will be understood by those skilled in the art that the foregoing is merely illustrative of the principles of calculating the capacitance mismatch parameter according to the present disclosure and is not to be construed as limiting the present disclosure.

It will be understood by those skilled in the art that the control and measurement module may implement the mismatch parameter B in various hardware or software manners known in the art_iThe present disclosure is not limited thereto.

In one possible implementation, the control and measurement module 405 obtains the capacitance mismatch parameter B_iThen, the capacitance mismatch parameter B can be determined_iGenerating a correction signal D₄And will correct the signal D₄To the correction module 403. The calibration module 403 receives the calibration signal D₄Then, the capacitance mismatch parameter B can be stored therein_i。

In one example, as shown in fig. 4, after the calibration test is completed, the enable signal of the control and measurement module 405 may be changed (e.g., the enable signal Cali _ en ═ 0) and the input analog signal V may be changed_inWhen the analog voltage is changed to the normal analog voltage, the analog-to-digital conversion circuit exits the correction test mode.

In this case, the control and measurement module 405 may configure the second control signal Cali _ sel to be 1, i.e., Φ_sel＝1，

The switch SWs3 and the switch SWs6 are turned off, the switch SWs1 and the switch SWs4 are turned on at the phi 1 phase and turned off at the phi 2 phase, the switch SWs2 and the switch SWs5 are turned on at the phi 2 phase and turned on at the phi 1 phaseThe circuit is switched off, the switch SWf3 and the switch SWf4 are switched on, the switch SWf1, the switch SWf2, the switch SWf5 and the switch SWf6 are switched off, so that the first feedback capacitor and the second feedback capacitor are connected into a feedback phase, each sampling capacitor is connected into a sampling phase, the circuit can enter a normal working mode, and the analog signal V is generated by the analog signal V_inConverted into a first digital signal D by an SADC module 401₁(ii) a D of MUX module 404_out1For outputting a first digital signal D₁(ii) a First digital signal D₁After entering the calibration module 403, the calibration module 403 is configured to calibrate the capacitor mismatch parameter B_iFor the first digital signals D respectively₁Each bit is correspondingly corrected. After being corrected, the corrected second digital signal D can be output₂. The present disclosure is not limited to a particular manner of correction. By the method, the precision of the pipeline analog-to-digital converter can be effectively improved.

The embodiments of the present disclosure may also implement the test of the capacitance mismatch parameter of each capacitor in other ways, which is described as an example below.

Referring to fig. 5, fig. 5 is a schematic circuit diagram of an MDAC module according to an embodiment of the present disclosure.

In one possible embodiment, as shown in fig. 5, an MDAC module in the related art may be improved, in which a redundancy capacitor C is provided in a capacitor unit of the MDAC module_dmyC and a plurality of switches are provided in the switch unit, and the plurality of switches are controlled by outputting different second control signals at different time periods, so that the redundant capacitor C can be made_dmyA first feedback capacitor C_F0，1A second feedback capacitor C_F0，2The combination of (a) and (b) is switched into either the sampling phase or the feedback phase to enable determination of the capacitance mismatch parameter.

In one example, as shown in FIG. 5, when a redundant capacitor C is provided_dmyEach sampled capacitance (e.g., capacitance C) is used to determine a capacitance mismatch parameter_S0,1) Is electrically connected to the redundant capacitor C_dmyFirst terminal, first feedback capacitor C_F0,1First terminal, second feedback capacitor C_F0,2And a negative input terminal of the operational amplifier OPA, and a second terminal of the sampling capacitor is electrically connected to the first terminalA sampling control switch

First terminal, second sampling control switch

And a second terminal of the second sampling control switch is connected to the first preset voltage or the second preset voltage.

In one example, as shown in FIG. 5, a redundant capacitor C_dmyIs connected to a first analog voltage V via a first redundant switch SWd1_cmConnected to a first analog voltage V by a second redundant switch SWd2_cmAnd to the first preset voltage or the second preset voltage, respectively, through the third redundant switch SWd 3.

In one example, as shown in FIG. 5, a first feedback capacitance C_F0,1Is connected to a first analog voltage V via a first feedback switch SWf1_cmAnd is connected to the first preset voltage or the second preset voltage through the second feedback switch SWf2, and is connected to the output terminal of the operational amplifier through the third feedback switch SWf 3.

In one example, as shown in FIG. 5, a second feedback capacitance C_F0,2Is connected to the output terminal of the operational amplifier through a fourth feedback switch SWf4, is connected to the first preset voltage or the second preset voltage through a fifth feedback switch SWf5, and is connected to the first analog voltage V through a sixth feedback switch SWf6_cm。

In one example, as shown in FIG. 5, the redundant capacitance C_dmyFirst terminal of, the first feedback capacitance C_F0,1First terminal of, the second feedback capacitance C_F0,2Is electrically connected to the plurality of sampling capacitors (C)_S0,1～C_S0,8) And a negative input of said gain unit (operational amplifier OPA),

the redundant capacitor C_dmyIs electrically connected to a first terminal of the first redundant switch SWd1, a first terminal of the second redundant switch SWd2, a second terminal of the first redundant switch SWd1, and the first redundant switch SWd2A second terminal of the feedback switch SWf1 and a second terminal of the sixth feedback switch SWf6 are electrically connected to the first analog voltage V_cmA second terminal of the third redundant switch SWd2, a second terminal of the second feedback switch SWf2, and a second terminal of the fifth feedback switch SWf5 are electrically connected to a first preset voltage or a second preset voltage,

a second terminal of the first feedback capacitor is electrically connected to a first terminal of the first feedback switch SWf1, a first terminal of the second feedback switch SWf2, and a first terminal of the third feedback switch SWf3,

a second end of the second feedback capacitor is electrically connected to a first end of the fourth feedback switch SWf4, a first end of the fifth feedback switch SWf5, and a first end of the sixth feedback switch SWf6,

a second terminal of the third feedback switch SWf3 and a second terminal of the fourth feedback switch SWf4 are electrically connected to the output terminal of the gain cell,

the positive input end of the gain unit is grounded.

It should be noted that the first feedback capacitor C is used in the above description_F0，1A second feedback capacitor C_F0，2The above circuit has been described for the purpose of example, however, it should be understood that the embodiments of the present disclosure are not limited thereto, and the number of feedback capacitors may be set according to actual needs, for example, only one feedback capacitor (e.g., the first feedback capacitor C) may be included_F0，1) More than 2 feedback capacitors may be included. In the case of different numbers of feedback capacitances, the feedback switches may be adaptively set according to the number of feedback capacitances, for example, when the number of feedback capacitances is set to 1, the number of feedback switches is 3; when the number of the feedback capacitors is 3, the number of the feedback switches is 9; when the number of feedback capacitors is T, the number of feedback switches is 3 × T.

In one example, in the case that the output terminal of the MUX module outputs the first control signal, the control and measurement module may be further configured to:

controlling a switching unit to change the redundant capacitance C according to the second control signal at different time periods_dmyOne or more feedback capacitors and oneOr the connection relation of a plurality of sampling capacitors, and determining the capacitor mismatch parameter.

In a possible embodiment, the control of the switching unit to change the redundant capacitance C according to the second control signal at different time periods_dmyThe connection relationship between the one or more feedback capacitors and the one or more sampling capacitors may include:

controlling a switch unit to switch according to the second control signal to enable the first feedback capacitor C_F0，1A second feedback capacitor C_F0，2A feedback phase is connected, one end of the redundant capacitor is connected with a first analog voltage, and the first feedback capacitor and the second feedback capacitor C_F0，2Any 2 of the plurality of feedback capacitors;

controlling a switch unit to switch according to the second control signal to switch the first feedback capacitor C_F0，1And the redundant capacitor C_dmyA sampling phase is switched in, and the second feedback capacitor C is connected_F0，2Connecting a feedback phase;

controlling a switch unit to switch according to the second control signal to switch the second feedback capacitor C_F0，2And the redundant capacitor C_dmyA sampling phase is switched in, and the first feedback capacitor C is connected_F0，1And switching in a feedback phase.

In one example, the above steps can be implemented in different time periods, for example, in a third time period, the switch unit is controlled to switch the first feedback capacitor C according to the second control signal_F0，1A second feedback capacitor C_F0，2A feedback phase is connected, one end of the redundant capacitor is connected with a first analog voltage, and the first feedback capacitor and the second feedback capacitor C_F0，2Any 2 of the plurality of feedback capacitors; the first feedback capacitor C can be switched on or off according to the second control signal during a fourth period_F0，1And the redundant capacitor C_dmyA sampling phase is switched in, and the second feedback capacitor C is connected_F0，2Connecting a feedback phase; the switch sheet can be controlled according to the second control signal in a fifth time periodA unit switching switch for switching the second feedback capacitor C_F0，2And the redundant capacitor C_dmyA sampling phase is switched in, and the first feedback capacitor C is connected_F0，1An access feedback phase, wherein the third time period, the fourth time period, and the fifth time period do not overlap with each other.

In one example, the second control signal may include Φ during the third time period_sel,f1＝0，Φ _sel,f20. In this case, the switch SWf1, the switch SWf2, the switch SWf5 and the switch SWf6 are turned off, the switch SWf3 and the switch SWf4 are turned on, and the first feedback capacitor C is turned on_F0,1A second feedback capacitor C_F0,2When the feedback phase is switched on, the switch SWd2 is switched off, the switch SWd1 is switched on, and the redundant capacitor C is connected_dmyThe lower polar plate is connected with a first analog voltage V_cmI.e. the first feedback capacitor C_F0,1A second feedback capacitor C_F0,2As feedback capacitors, redundant capacitors C_dmyThe sampling phase and the feedback phase are not affected.

In one example, during the fourth time period, the second control signal may include Φ_sel,f1＝1，Φ _sel,f20. In this case, the switch SWf3, the switch SWf5, and the switch SWf6 are turned off, the switch SWf1 is turned on at Φ 1, the switch SWf2 is turned off, the switch SWf2 and the switch SWf4 are turned on, the switch SWd1 is turned on at Φ 1, the switch SWd2 is turned on at Φ 2, the switch SWf2 is turned off at Φ 1, and the first feedback capacitor C is turned on_F0,1And a redundant capacitor C_dmyA sampling phase is connected, and a second feedback capacitor C_F0,2Switching in a feedback phase, i.e. a first feedback capacitor C_F0,1And a redundant capacitor C_dmyAs a sampling capacitor, a second feedback capacitor C_F0,2As a feedback capacitor.

In one example, in the fifth period of time, the second control signal may be Φ_sel,f1＝0，Φ _sel,f21. In this case, the switch SWf1, the switch SWf2 and the switch SWf4 are turned off, the switch SWf3 and the switch SWf5 are turned on, the switch SWf6 is turned on at Φ 1, turned off at Φ 2, the switch SWd1 is turned on at Φ 1, turned off at Φ 2, the switch SWd2 is turned on at Φ 2, and turned off at Φ 1, and the second feedback capacitor C is turned off_F0,2And a redundant capacitor C_dmyA sampling phase is connected, and a first feedback capacitor C_F0,1Switching in a feedback phase, i.e. a second feedback capacitor C_F0,2And a redundant capacitor C_dmyAs a sampling capacitor, a first feedback capacitor C_F0,1As a feedback capacitor.

In a possible implementation, the determining the capacitance mismatch parameter may include:

receiving a plurality of third digital signals output by the ADC module in a third time period, and determining a third mismatch parameter of a plurality of sampling capacitors relative to a first capacitor in the plurality of sampling capacitors by using the plurality of third digital signals;

receiving a plurality of third digital signals output by the ADC module during a fourth time period, and determining the first feedback capacitor C by using the plurality of third digital signals_F0，1A fourth mismatch parameter with respect to the first capacitance;

receiving a plurality of third digital signals output by the ADC module in a fifth time period, and determining the second feedback capacitor C by using the plurality of third digital signals_F0，2A fifth mismatch parameter with respect to the first capacitance;

and determining the capacitance mismatch parameter by using the third mismatch parameter, the fourth mismatch parameter and the fifth mismatch parameter.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating obtaining a capacitance mismatch parameter according to an embodiment of the disclosure.

In one example, as shown in fig. 6, in the third period of time, the second control signals may be set to all 0, i.e., Φ_sel,f1＝0，Φ_sel,f2When the capacitance is 0, the on/off of the switches SWf1 to SWf6 and the switches SWd1 to SWd3 are controlled to connect the first feedback capacitor C to the ground_F0,1A second feedback capacitor C_F0,2A feedback phase is connected to a redundant capacitor C_dmyThe lower polar plate is connected with a first analog voltage V_cmIn this case, the calculation manner of the third mismatch parameter of the third time period may refer to the aforementioned calculation manner of the first mismatch parameter of the first time period.

During a fourth time period, by configuring the second control signal (phi)_sel,f1＝1，Φ_sel,f20), the on/off of the switches SWf1 to SWf6 and SWd1 to SWd3 are controlled, and the first feedback capacitor C is connected to the first feedback capacitor C_F0,1A redundant capacitor C_dmyA sampling phase is connected, and a second feedback capacitor C_F0,2Feedback phase is connected, and residual signal V is subjected to post-stage alignment by pipeline ADC_resQuantizing to obtain a third digital signal D₃In the presence of m residual signals V_res，jIn this case, equation (3) can be expressed as:

wherein

According to the capacitor mismatch test plan, 2 sets of the first control signals D can be sequentially set_ctrl，j(9≤j≤10)，

TABLE 3

in one example, as shown in fig. 6, in the fifth period of time, the second control signal (Φ) may be configured_sel,f1＝0，Φ_sel,f21), the on/off of the switches SWf1 to SWf6 and SWd1 to SWd2 are controlled to connect and disconnect the second feedback capacitor C_F0,2And a redundant capacitor C_dmyAccess a sampling phase, willA first feedback capacitor C_F0,1And switching in a feedback phase.

At this time, the pipeline ADC later stage is used for comparing residual difference signal V_resQuantizing to obtain digital signal D₄In the presence of m residual signals V_res，jIn this case, equation (3) can be expressed as:

wherein

According to the capacitor mismatch test plan, 2 sets of control signals D can be set in sequence_ctrl，j(11. ltoreq. j. ltoreq.12) as shown in Table 4.

TABLE 4

In practical circuits, the operational amplifier has a DC gain A>>1, thus having K ″)_A1, and C_S,iC ", therefore:

in one example, referring to the foregoing manner of calculating the first mismatch parameter for the first time period, and combining equation (10), and equations (11) and (13), and equation (14), the sampling capacitance C can be obtained_S0,iAnd a feedback capacitor C_F0,iRatio B relative to the average of all sampling capacitances and feedback capacitances_i。

In one possible implementation, the control and measurement module 405 obtains the capacitance mismatch parameter B_iThen, the capacitance mismatch parameter B can be determined_iGenerating a correction signal D_4cAnd will correct the signal D_4cTo the correction module 403. The calibration module 403 receives the calibration signal D_4cThen, the capacitance mismatch parameter B can be stored therein_i。

In one example, as shown in fig. 6, after the calibration test is completed, the enable signal of the control and measurement module 405 may be changed (e.g., the enable signal Cali _ en ═ 0), and the first digital signal D may be gated₁And make the input analog signal V_inWhen the analog voltage is changed to the normal analog voltage, the analog-to-digital conversion circuit exits the correction test mode.

In this case, the control and measurement module 405 may configure the second control signals Cali _ sel, f1 and Cali _ sel, f2 to be both 0, i.e., Φ_sel,f1＝0，Φ _sel,f20, so that the circuit enters a normal operating mode, the analog signal V_inConverted into a first digital signal D by an SADC module 401₁(ii) a D of MUX module 404_out1For outputting a first digital signal D₁(ii) a First digital signal D₁After entering the calibration module 403, the calibration module 403 is configured to calibrate the capacitor mismatch parameter B_iFor the first digital signals D respectively₁Each bit is correspondingly corrected. After being corrected, the corrected second digital signal D can be output₂. The present disclosure is not limited to a particular manner of correction. By the method, the precision of the pipeline analog-to-digital converter can be effectively improved.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating obtaining a capacitance mismatch parameter according to an embodiment of the disclosure.

In one possible embodiment, as shown in FIG. 5, aBy inserting multiple switches in the MDAC module, the redundant capacitor C can be made_dmyA first feedback capacitor C_F0，1A second feedback capacitor C_F0，2The combination of (a) and (b) is switched into either the sampling phase or the feedback phase to enable determination of the capacitance mismatch parameter.

controlling a switch unit to switch according to the second control signal to switch the first feedback capacitor C_F0，1And the redundant capacitor C_dmyA sampling phase is switched in, and the second feedback capacitor C is connected_F0，2Connecting a feedback phase; and/or

In a possible embodiment, the above steps may be performed at different time periods to determine the mismatch parameter, for example, the switching unit may be controlled to switch the first feedback capacitor C according to the second control signal at the sixth time period_F0，1And the redundant capacitor C_dmyA sampling phase is switched in, and the second feedback capacitor C is connected_F0，2Connecting a feedback phase; the second feedback capacitor C can be switched on or off according to the second control signal in a seventh time period_F0，2And the redundant capacitor C_dmyA sampling phase is switched in, and the first feedback capacitor C is connected_F0，1And accessing a feedback phase, wherein the sixth time period and the seventh time period are not overlapped with each other.

In one example, during the sixth time period, the second control signal may include Φ_sel,f1＝1，Φ _sel,f20. In this case, the switch SWf3, the switch SWf5, and the switch SWf6 are off, the switch SWf1 is on at Φ 1, and off at Φ 2, and the switch is onThe switch SWf2 is turned on at phi 2, turned off at phi 1, the switch SWf4 is turned on, the switch SWd1 is turned on at phi 1, turned off at phi 2, the switch SWd2 is turned on at phi 2, and turned off at phi 1, the first feedback capacitor C_F0,1And a redundant capacitor C_dmyA sampling phase is connected, and a second feedback capacitor C_F0,2Switching in a feedback phase, i.e. a first feedback capacitor C_F0,1And a redundant capacitor C_dmyAs a sampling capacitor, a second feedback capacitor C_F0,2As a feedback capacitor.

In one example, in the seventh period of time, the second control signal may be Φ_sel,f1＝0，Φ _sel,f21. In this case, the switch SWf1, the switch SWf2 and the switch SWf4 are turned off, the switch SWf3 is turned on at Φ 2, the switch SWf1 is turned off, the switch SWf5 is turned on, the switch SWf6 is turned on at Φ 1, the switch SWd1 is turned on at Φ 2, the switch SWd2 is turned on at Φ 1, the second feedback capacitor C is turned off at Φ 2, the switch SWf 3583 is turned on at Φ 1, and the switch SWf2 and the switch SWf4 are turned off_F0,2And a redundant capacitor C_dmyA sampling phase is connected, and a first feedback capacitor C_F0,1Switching in a feedback phase, i.e. a second feedback capacitor C_F0,2And a redundant capacitor C_dmyAs a sampling capacitor, a first feedback capacitor C_F0,1As a feedback capacitor.

in a sixth time period, a plurality of third digital signals output by the ADC module are received, and the first feedback capacitor C is determined by using the plurality of third digital signals_F0，1A sixth mismatch parameter with respect to the first capacitance;

in a seventh time period, receiving a plurality of third digital signals output by the ADC module, and determining the second feedback capacitor C by using the plurality of third digital signals_F0，2A seventh mismatch parameter with respect to the first capacitance;

and determining the capacitance mismatch parameter by using the sixth mismatch parameter and the seventh mismatch parameter.

In one example, as shown in fig. 7, in the sixth period of time, by configuring the second control signal (Φ)_sel,f1＝1，Φ_sel,f2＝0)，The first feedback capacitor C is connected with a switch SWd 1-SWd 2 and a switch SWf 1-SWf 6_F0,1A redundant capacitor C_dmyA sampling phase is connected, and a second feedback capacitor C_F0,2Feedback phase is switched in, and residual difference signal V is subjected to analog-to-digital conversion (ADC) module_resQuantizing to obtain a third digital signal D₅In the presence of m residual signals V_res，jIn this case, equation (3) can be expressed as:

wherein,

in one example, 10 sets of the first control signals D may be sequentially set according to a capacitance mismatch test plan_ctrl，j(1≤j≤10)，

TABLE 5

In one example, in the seventh period of time, the second control signal (Φ) may be configured_sel,f1＝0，Φ_sel,f21), switches SWd 1-SWd 2 and SWf 1-SWf 6 are switched to couple the second feedback capacitor C_F0,2And a redundant capacitor C_dmyA sampling phase is switched in, and a first feedback capacitor C is connected_F0,1And switching in a feedback phase.

At this time, the ADC module is used for correcting the residual difference signal V_resQuantizing to obtain digital signal D₅In the presence of m residual signals V_res，jIn this case, equation (3) can be expressed as:

wherein

According to the capacitor mismatch test plan, 10 sets of control signals D can be set in sequence_ctrl，j(1. ltoreq. j. ltoreq.10) as shown in Table 6.

TABLE 6

From the foregoing, the following approximation can be obtained:

from equation (15), equation (16), and equations (18), 19), the sampling capacitance C can be calculated_S0,iAnd a feedback capacitor C_F0,iThe capacitance mismatch parameter of (a).

In one possible implementation, the control and measurement module 405 obtains the capacitance mismatch parameter B_iThen, the capacitance mismatch parameter B can be determined_iGenerating a correction signal D_5cAnd will correct the signal D_5cTo the correction module 403. The calibration module 403 receives the calibration signal D_5cThen, the capacitance mismatch parameter B can be stored therein_i。

In one example, as shown in fig. 5, after the calibration test is completed, the enable signal of the control and measurement module 405 may be changed (e.g., the enable signal Cali _ en ═ 0), and the first digital signal D may be gated₁And make the input analog signal V_inWhen the analog voltage is changed to the normal analog voltage, the analog-to-digital conversion circuit exits the correction test mode.

In this case, the control and measurement module 405 may configure the second control signals Cali _ sel, f1 and Cali _ sel, f2 to both be 0, i.e., Φ_sel,f1＝0，Φ_sel,f2When the analog signal V is 0, the switches SWd1 to SWd2 and SWf1 to SWf6 are controlled to make the circuit enter a normal operation mode_inConverted into a first digital signal D by an SADC module 401₁(ii) a D of MUX module 404_out1For outputting a first digital signal D₁(ii) a First digital signal D₁After entering the calibration module 403, the calibration module 403 is configured to calibrate the capacitor mismatch parameter B_iFor the first digital signals D respectively₁Each bit is correspondingly corrected. After being corrected, the corrected second digital signal D can be output₂. The present disclosure is not limited to a particular manner of correction. By the method, the precision of the pipeline analog-to-digital converter can be effectively improved.

controlling a switch unit according to the second control signal to switch the first feedback capacitor C_F0，1And the second feedback capacitor C_F0，2A sampling phase is connected, and the redundant capacitor C is connected_dmyAnd switching in a feedback phase.

In one example, the above steps may be performed during an eighth time period to determine the capacitance mismatch parameter.

In one example, the second control signal may include Φ _sel1. In this case, the first feedback capacitor C is switched by controlling the lower plate switch of the capacitor_F0,1A second feedback capacitor C_F0,2Connecting sampling phase and redundant capacitor C_dmySwitching in a feedback phase, i.e. a first feedback capacitor C_F0,1A second feedback capacitor C_F0,2As sampling capacitors, redundant capacitors C_dmyAs a feedback capacitor.

receiving a plurality of third digital signals output by the ADC module, and determining the sampling capacitor and the first feedback capacitor C by using the plurality of third digital signals_F0，1A second feedback capacitor C_F0，2An eighth mismatch parameter with respect to the first capacitance.

Determining the capacitance mismatch parameter using the eighth mismatch parameter.

The following description is made with reference to specific examples.

Referring to fig. 8, fig. 8 is a schematic circuit diagram of an MDAC module according to an embodiment of the present disclosure.

The MDAC module includes a gain unit (operational amplifier OPA), and the switching unit may include a first redundant switch SWd1, a second redundant switch SWd2, a first feedback switch SWf1, a second feedback switch SWf2, a third feedback switch SWf3, a fourth feedback switch SWf4, a fifth feedback switch SWf5, and a sixth feedback switch SWf6, wherein:

the redundant capacitor C_dmyFirst terminal of, the first feedback capacitance C_F0,1First terminal of, the second feedback capacitance C_F0,2Is electrically connected to the plurality of sampling capacitors (C)_S0,1～C_S0,8) And a negative input of said gain unit (operational amplifier OPA),

the redundant capacitor C_dmyIs electrically connected to a first terminal of the first redundant switch SWd1, a first terminal of the second redundant switch SWd2, a second terminal of the second redundant switch SWd2, a second terminal of the first feedback switch SWf1, and a second terminal of the sixth feedback switch SWf6 are electrically connected to a first analog voltage V_cmA second end of the second feedback switch SWf2 and a second end of the fifth feedback switch SWf5 are electrically connected to a first preset voltageThe voltage or a second predetermined voltage is set,

a second terminal of the first redundant switch SWd1, a second terminal of the third feedback switch SWf3, and a second terminal of the fourth feedback switch SWf4 are electrically connected to the output terminal of the gain cell,

the positive input end of the gain unit is grounded.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating obtaining a capacitance mismatch parameter according to an embodiment of the disclosure.

In one example, as shown in fig. 8, in the eighth period of time, by configuring the second control signal (Φ)_sel1), the switch SWf3 and the switch SWf4 are turned off, the switch SWf1 and the switch SWf6 are turned on in the Φ 1 phase and turned off in the Φ 2 phase, and the first feedback capacitor C is connected to the output terminal of the dc converter_F0,1A second feedback capacitor C_F0,2The sampling phase is switched on, the switch SWd2 is switched off, the switch SWd1 is switched on, and the redundant capacitor C_dmyFeedback phase is switched in, and residual difference signal V is subjected to analog-to-digital conversion (ADC) module_resQuantizing to obtain a third digital signal D₆In the presence of m residual signals V_res，jIn this case, equation (3) can be expressed as:

wherein

According to the capacitor mismatch test plan, 10 sets of the first control signals D may be sequentially set_ctrl，j(1. ltoreq. j. ltoreq.10) as shown in Table 7.

TABLE 7

From the foregoing, the following approximation can be obtained:

from equation (21), the sampling capacitance C can be calculated_S0,iAnd a feedback capacitor C_F0,iThe capacitance mismatch parameter of (a).

In one example, as shown in fig. 9, after the calibration test is completed, the enable signal of the control and measurement module 405 may be changed (e.g., the enable signal Cali _ en ═ 0), and the first digital signal D may be gated₁And make the input analog signal V_inWhen the analog voltage is changed to the normal analog voltage, the analog-to-digital conversion circuit exits the correction test mode.

In this case, the control and measurement module 405 may configure a secondThe control signal Cali _ sel is 0, i.e., Φ _sel0, so that the switch SWf1, the switch SWf2, the switch SWf5 and the switch SWf6 are turned off, the switch SWf3 and the switch SWf4 are turned on, the switch SWd2 is turned on, the switch SWd1 is turned off, the circuit enters a normal operation mode, and the analog signal V is output_inConverted into a first digital signal D by an SADC module 401₁(ii) a D of MUX module 404_out1For outputting a first digital signal D₁(ii) a First digital signal D₁After entering the calibration module 403, the calibration module 403 is configured to calibrate the capacitor mismatch parameter B_iFor the first digital signals D respectively₁Each bit is correspondingly corrected. After being corrected, the corrected second digital signal D can be output₂. The present disclosure is not limited to a particular manner of correction. By the method, the precision of the pipeline analog-to-digital converter can be effectively improved.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, when the measurement is corrected, the input analog signal only needs to be a high-precision direct-current voltage signal (such as zero level) which is easy to obtain, so that the circuit complexity is reduced; moreover, the circuit complexity of the correction module and the control and measurement module is low, and the circuit complexity of the whole analog-digital conversion circuit is reduced.

According to the analog-to-digital conversion circuit disclosed by the embodiment of the disclosure, during a correction test, the voltage of a residual difference signal output by an MDAC module of a front-stage analog-to-digital conversion circuit is near 0, so that the nonlinear influence of the gain of the MDAC operational amplifier of the current stage is effectively reduced, the nonlinear effect influence of the measurement of an ADC module of a rear-stage analog-to-digital conversion circuit is effectively reduced, and the precision of effective measurement is ensured.

The analog-to-digital conversion circuit according to the embodiment of the disclosure is not limited to the MDAC module of the first stage analog-to-digital conversion circuit of the pipeline ADC, and can be applied to the MDAC modules of the analog-to-digital conversion circuits of the pipeline ADC, so as to respectively correct the MDAC modules of the stages.

According to the analog-digital conversion circuit disclosed by the embodiment of the disclosure, the capacitance mismatch between the sampling capacitor and the feedback capacitor can be eliminated, so that the accuracy of analog-digital conversion is improved.

According to an embodiment of the present disclosure, there is also provided a pipeline analog-to-digital converter, each stage of which includes the analog-to-digital conversion circuit described above, respectively.

The specific manner in which the various blocks perform operations with respect to the pipelined analog-to-digital converter has been described in detail in relation to embodiments of the analog-to-digital conversion circuit and will not be elaborated upon here.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital conversion circuit, wherein the circuit is a stage of a pipelined analog-to-digital converter, the circuit comprising: a sub-analog-to-digital conversion SADC module, an analog-to-digital conversion and amplification MDAC module, a control and measurement module, a multiplexer MUX module and a correction module,

the input end of the SADC module is used for inputting an analog signal, and the output end of the SADC module is used for outputting a first digital signal after analog-to-digital conversion;

the MUX module is electrically connected between the SADC module and the MDAC module, one input end of the MUX module is used for inputting the first digital signal, the other input end of the MUX module is used for inputting a first control signal, the enable end of the MUX module is used for inputting an enable signal, and the MUX module is used for outputting the first digital signal or the first control signal to the MDAC module according to the enable signal;

the MDAC module comprises a capacitor unit and a switch unit, the capacitor unit comprises a plurality of sampling capacitors and a plurality of feedback capacitors, a first input end of the MDAC module is used for inputting the analog signal, a second input end of the MDAC module is electrically connected with an output end of the MUX module, a third input end of the MDAC module is used for inputting a second control signal, and an output end of the MDAC module is used for outputting a residual error signal; the switch unit comprises a plurality of switches, a first end of the switch unit is electrically connected to the output end of the MUX module and is used for inputting the first control signal or the first digital signal, a second end of the switch unit is used for inputting the second control signal, a third end of the switch unit is electrically connected to the capacitor unit, and the switch unit is used for switching according to the second control signal so as to change the electrical connection relation of a plurality of sampling capacitors and/or a plurality of feedback capacitors in the MDAC module;

the control and measurement module is electrically connected to the MUX module and the switch unit, a first output end is used for outputting the first control signal, a second output end is used for outputting the enable signal, a third output end is used for outputting a correction signal, a fourth output end is used for outputting the second control signal, and the correction signal is used for representing capacitance mismatch parameters of a plurality of sampling capacitors and a plurality of feedback capacitors of the MDAC module;

the correction module is electrically connected to the control and measurement module, one input end of the correction module is electrically connected to the output end of the MUX module or the output end of the SADC module, the other input end of the correction module is used for inputting the correction signal, the correction module is used for correcting the first digital signal according to the correction signal and outputting a corrected second digital signal through the output end,

wherein, under the condition that the output end of the MUX module outputs the first control signal, the control and measurement module is used for:

and controlling a switch unit to change the connection relation of the plurality of sampling capacitors and/or the plurality of feedback capacitors according to the second control signal at different time periods, determining the capacitor mismatch parameter and generating a correction signal.

2. The circuit of claim 1, further comprising an analog-to-digital (ADC) module electrically connected to the MDAC module and the control and measurement module, wherein an input terminal is configured to input the residual signal, and an output terminal is configured to output a third digital signal obtained by performing analog-to-digital conversion on the residual signal.

3. The circuit of claim 1, wherein the controlling the switch unit according to the second control signal at different time periods to change the connection relationship of the plurality of sampling capacitors and/or the plurality of feedback capacitors comprises:

4. The circuit of claim 3, wherein the first number is 1, 2, or more.

5. The circuit of claim 1, wherein the MDAC module comprises a gain unit, the switch unit comprises 3K feedback switches and 3K sampling switches, 1 ≦ K ≦ M, K indicating the first number, M indicating a total number of sampling capacitors, any one of the K sampling capacitors comprises a corresponding 3 sampling switches, any one of the K feedback capacitors comprises a corresponding 3 feedback switches, and wherein:

the positive input end of the gain unit is grounded.

6. The circuit of claim 5, wherein when the first number K is 2, the sampling capacitors comprise a first sampling capacitor and a second sampling capacitor, the feedback capacitors comprise a first feedback capacitor and a second feedback capacitor, and the switch unit comprises a first feedback switch, a second feedback switch, a third feedback switch, a fourth feedback switch, a fifth feedback switch, a sixth feedback switch, a first sampling switch, a second sampling switch, a third sampling switch, a fourth sampling switch, a fifth sampling switch and a sixth sampling switch,

the first end of the first sampling capacitor, the first end of the second sampling capacitor, the first end of the first feedback capacitor and the first end of the second feedback capacitor are electrically connected to the negative input end of the gain unit,

the second end of the first sampling capacitor is electrically connected with the first end of the first sampling switch, the first end of the second sampling switch and the first end of the third sampling switch,

the second end of the second sampling capacitor is electrically connected with the first end of the fourth sampling switch, the first end of the fifth sampling switch and the first end of the sixth sampling switch,

the second end of the first sampling switch is electrically connected to the second end of the fourth sampling switch, the second end of the first feedback switch and the second end of the sixth feedback switch,

the second end of the second sampling switch, the second end of the fifth sampling switch, the second end of the second feedback switch and the second end of the fifth feedback switch are electrically connected to a first preset voltage or a second preset voltage,

a second end of the third sampling switch and a second end of the sixth sampling switch are electrically connected to a second end of the third feedback switch, a second end of the fourth feedback switch and an output end of the gain unit,

the second end of the first feedback capacitor is electrically connected to the first end of the first feedback switch, the first end of the second feedback switch and the first end of the third feedback switch,

a second end of the second feedback capacitor is electrically connected to a first end of the fourth feedback switch, a first end of the fifth feedback switch, and a first end of the sixth feedback switch.

7. The circuit of claim 1, wherein the capacitance unit further comprises a redundant capacitance, and in the case that the output terminal of the MUX module outputs the first control signal, the control and measurement module is further configured to:

and controlling the switch unit according to the second control signal at different time periods, changing the connection relation of the redundant capacitor, one or more feedback capacitors and/or one or more sampling capacitors, and determining the capacitor mismatch parameter.

8. The circuit of claim 7, wherein the controlling the switch unit according to the second control signal at different time periods to change the connection relationship of the redundant capacitor, the one or more feedback capacitors and/or the one or more sampling capacitors comprises:

controlling the switch unit according to the second control signal to switch the first feedback capacitor and the redundant capacitor into a sampling phase and switch the second feedback capacitor into a feedback phase; and/or

And controlling the switch unit according to the second control signal so as to access the second feedback capacitor and the redundant capacitor to a sampling phase and access the first feedback capacitor to a feedback phase.

9. The circuit of claim 7, wherein the controlling the switch unit according to the second control signal at different time periods to change the connection relationship of the redundant capacitor, the one or more feedback capacitors and the one or more sampling capacitors comprises:

and controlling the switch unit according to the second control signal so as to access the first feedback capacitor and the second feedback capacitor to a sampling phase and access the redundant capacitor to a feedback phase.

10. The circuit of claim 7, wherein the MDAC module comprises a gain unit, and wherein the switching unit comprises a first redundant switch, a second redundant switch, a first feedback switch, a second feedback switch, a third feedback switch, a fourth feedback switch, a fifth feedback switch, and a sixth feedback switch, wherein:

the first ends of the redundant capacitors, the first ends of the first feedback capacitors and the first ends of the second feedback capacitors are electrically connected to the first ends of the plurality of sampling capacitors and the negative input end of the gain unit,

the second end of the redundant capacitor is electrically connected with the first end of the first redundant switch and the first end of the second redundant switch,

the second end of the first redundant switch, the second end of the first feedback switch and the second end of the sixth feedback switch are electrically connected to a first analog voltage, the second end of the second redundant switch, the second end of the second feedback switch and the second end of the fifth feedback switch are electrically connected to a first preset voltage or a second preset voltage,

a second end of the second feedback capacitor is electrically connected to a first end of the fourth feedback switch, a first end of the fifth feedback switch and a first end of the sixth feedback switch,

the second end of the third feedback switch and the second end of the fourth feedback switch are electrically connected to the output end of the gain unit,

the positive input end of the gain unit is grounded.

11. The circuit of claim 7, wherein the MDAC module comprises a gain unit, and wherein the switching unit comprises a first redundant switch, a second redundant switch, a first feedback switch, a second feedback switch, a third feedback switch, a fourth feedback switch, a fifth feedback switch, and a sixth feedback switch, wherein:

the second end of the second redundant switch, the second end of the first feedback switch and the second end of the sixth feedback switch are electrically connected to a first analog voltage, the second end of the second feedback switch and the second end of the fifth feedback switch are electrically connected to a first preset voltage or a second preset voltage,

the second end of the first redundant switch, the second end of the third feedback switch and the second end of the fourth feedback switch are electrically connected to the output end of the gain unit,

the positive input end of the gain unit is grounded.

12. A pipeline analog-to-digital converter, characterized in that each stage of the pipeline analog-to-digital converter comprises an analog-to-digital conversion circuit according to any one of claims 1 to 11, respectively.