CN115694487A - Digital correction method for high-speed high-precision data converter capacitor array errors - Google Patents

Abstract

The invention provides a digital detection and correction method for high-speed and high-precision data converter capacitor array errors, so as to effectively improve the precision of a data converter. The invention has the independent innovative idea of correcting the capacitor array matching error with the redundant capacitor position in a segmented manner, and respectively and independently correcting the capacitor array error on the left side and the capacitor array error on the right side of the redundant capacitor. The error correction problem caused by the redundant capacitor existing in the high-speed ADC capacitor array is solved.

Description

Digital correction method for high-speed high-precision data converter capacitor array errors

Technical Field

The invention relates to the technical field of high-speed high-precision data converters.

Background

The real-time and simple circuit structure of the sar adc (successive approximation type data converter) makes it widely applied to high-speed and high-precision data conversion occasions. However, the development of the sar adc towards high precision is restricted by the mismatch of components and parasitic parameters.

The method for adjusting the mismatch error of the capacitor array proposed in the early industry is to test a data converter, and correspondingly adjust each unit capacitor of the capacitor array according to test data, so that the matching degree of the adjusted capacitor array is improved. The disadvantage is that the test and repair time is long and the cost is high. A representative digital correction principle is shown in fig. 1.

ADC (analog to digital converter) a is a data converter to be corrected, and ADC B is another data converter of the same parameters. The two data converters are independent of each other, and sample the input signal Vin to generate respective output signals D _A And D _B . Ideally, the ADC outputs data of

Due to the fact that the actual circuit has circuit lossAccompany, weight W _i Not exactly 1/2 ⁱ And (4) sequencing. If the weight W estimated in the digital domain is used _i '＝W _i +ε _i Instead of the weight W in the analog domain _i The digital domain corrected value can be obtained

Thus, the device

Continuously updating the weighted values W of A and B by a minimum root mean square iterative algorithm according to the error value _i ' when the error is sufficiently small, the correction is considered to be complete. The method has good universality, but the speed and the precision of the background digital iterative algorithm need a DSP (digital signal processor) to participate in control, so that chip resources and power consumption are consumed.

Disclosure of Invention

The invention provides a digital detection and correction method for high-speed and high-precision data converter capacitor array errors, so as to effectively improve the precision of a data converter.

In order to achieve the purpose, the invention adopts the technical scheme as shown in figure 2.

A digital correction method for high-speed high-precision data converter capacitor array errors comprises the following steps:

the invention firstly tests the deviation of each capacitor relative to an ideal value, and then corrects ADC data in a digital domain in real time in a segmented manner, so that the finally corrected ADC output is equal to the output in an ideal condition. The invention idea is as follows: the invention discloses a method for correcting the matching error of a capacitor array with redundant capacitor bits in a segmented mode, and belongs to the innovation point of the invention. High speed data converters require the introduction of redundant capacitors in the capacitor array to tolerate larger setup time errors, which presents a challenge to the correction of capacitive errors. Located in a redundant capacitor C _2r Low-order capacitor array on right side, error of lowest order epsilon ₀ I.e. the error itself epsilon measured for the lowest order capacitor _c0 (ii) a Sub-low order error epsilon ₁ Due to the influence of the low-order capacitor array error during the charge sharing, the error epsilon ₁ ＝ε ₀ +ε _c1 (ii) a By analogy of this, ε _2r ＝ε ₀ +ε ₁ +ε _c2r . The high-order capacitor array positioned at the left side of the redundant capacitor does not hold the recursive error formula any more due to the existence of the redundant capacitor. Error correction is initiated from redundant capacitor bit errors, ε ₂ ＝ε _2r +ε _c2 And so on.

And after the original data output by the ADC is subtracted from each weight capacitance error, the corrected high-precision data is obtained.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of the background art of the present invention.

FIG. 2 is a schematic view of the structure of the present invention.

Fig. 3 is a schematic diagram of a capacitor array according to an embodiment of the invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for explaining the present invention and are not construed as limiting the present invention.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or coupled. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

For the convenience of understanding the embodiments of the present invention, the following description will be further explained by taking several specific embodiments as examples in conjunction with the drawings, and the embodiments are not to be construed as limiting the embodiments of the present invention.

The processing flow of the digital correction method for the high-speed high-precision data converter capacitor array error provided by the embodiment of the invention is shown in fig. 2, and comprises the following processing steps:

first, the capacitive array match error is measured. The input signal is grounded, and the successive approximation logic control module 104 controls the ADC to measure the matching error epsilon of each capacitor from the high-order capacitor to the low-order capacitor in sequence _ci And latches the error to the correction block 103. The core idea of the present invention is an error correction method, not a capacitance error measurement method, and thus the capacitance error measurement method is not within the scope of the present invention.

Then, analog-to-digital conversion and error correction. Fig. 3 is a schematic diagram of a capacitor array according to an embodiment of the invention. Fig. 3 shows the sar adc feedback branch DAC. While this example figure illustrates the design concept of the present invention using a 6-bit binary-weighted capacitor array, the actual circuit implementation is not limited to a 6-bit binary-weighted capacitor array. C in capacitor array _2R For redundant capacitance, in order to reduce electricityThe capacitance array high-order capacitance establishes error in the charge sharing stage. The transfer function is 1/2 × b ₅ +1/2 ² ×b ₄ +1/2 ³ ×b ₃ +1/2 ⁴ ×b ₂ +1/2 ⁴ ×(b _2r -0.5)+1/2 ⁵ ×b ₁ +1/2 ⁶ ×b ₀ This is the transfer function in the rational case. Each capacitance value in the actual capacitance array has deviation and parasitics, so that the weight of each capacitance value in the transfer function is no longer 1/2 of the accurate weight ⁱ Sequence, actual weight w _i '＝w _i +ε _i Error in transfer function

The error correction algorithm is as follows: the lowest bit error epsilon of the low-order capacitor array positioned at the right side of the redundant capacitor ₀ I.e. the error itself epsilon measured for the lowest order capacitor _c0 (ii) a Sub-low order error epsilon ₁ Due to the influence of the low-order capacitor array error during the charge sharing, the error epsilon ₁ ＝ε ₀ +ε _c1 (ii) a By analogy of this, ε _2r ＝ε ₀ +ε ₁ +ε _c2r . The high-order capacitor array, which is located on the left side of the redundant capacitor, makes the above recursive error formula no longer true due to the existence of the redundant capacitor bit, the error correction starts from the redundant capacitor bit error,

ε ₂ ＝ε _2r +ε _c2 ；

ε ₃ ＝ε ₂ +ε _2r +ε _3c ；

ε ₄ ＝ε ₃ +ε ₂ +ε _2r +ε _4c ；

ε ₅ ＝ε ₄ +ε ₃ +ε ₂ +ε _2r +ε _5c 。

Claims (4)

1. a method for digitally correcting errors in a capacitor array of a high accuracy data converter, comprising:

measuring the one-by-one capacitance error of the capacitor array, and latching the one-by-one capacitance error to the digital correction module; input mouldOriginal data D of analog signal after ADC conversion _{out_raw} And operating with the latched error value to cancel the error in the raw output data due to the capacitor array error.

2. The method of claim 1, wherein measuring the capacitance array by capacitance error and latching to a digital correction module comprises:

measuring and latching the capacitor array error to the digital correction module at the power-on position; an error measurement process can also be inserted between data conversions to update the capacitor array errors in real time to the digital correction module.

3. The method of claim 1, wherein the input analog signal is converted by the ADC to obtain raw data D _{out_raw} Operating with the latched error value, comprising:

the error operation algorithm is suitable for correcting errors of a binary capacitor array with a redundant capacitor; the algorithm can also be simplified into a binary capacitor array without a redundant capacitor; the capacitor array error correction algorithm is not limited to the 6-bit capacitor array of the implementation example, and can be popularized to a multi-bit capacitor array.

4. Method according to claim 1 or 3, characterized in that the input analog signal is converted by ADC into raw data D _{out_raw} Operating with the latched error value, comprising:

the segmented error correction algorithm is an innovative point of the invention, and has the core idea that the errors of the capacitor arrays positioned at two sides of the redundant capacitor are segmented and corrected, and the high-order capacitor error correction term is equal to the accumulation of the low-order capacitor error correction term; the segmented correction algorithm is also applicable to the error correction of the capacitor array with the separation capacitor.

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