CN107359878B - Pipeline ADC front-end calibration method based on minimum quantization error - Google Patents
Pipeline ADC front-end calibration method based on minimum quantization error Download PDFInfo
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- CN107359878B CN107359878B CN201710706638.0A CN201710706638A CN107359878B CN 107359878 B CN107359878 B CN 107359878B CN 201710706638 A CN201710706638 A CN 201710706638A CN 107359878 B CN107359878 B CN 107359878B
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Abstract
A front end calibration method for a pipeline ADC belongs to the technical field of analog integrated circuits. The method starts to correct from the first-stage gain of the pipeline ADC until the front N-1-stage gain of the pipeline ADC is corrected in sequence, and the error between a restored signal and an original signal can be obtained after the first-stage gain to the N-1-stage gain are obtained; before calibration, the digital output of the flash ADC is used to obtain the analog output of the front N-1 stage of the pipeline ADC; specifically searching each stage of gain of the pipeline ADC based on an MATLAB program in the calibration process, then reducing the output data of the pipeline ADC, carrying out fast Fourier transform analysis on the reduced signal, and considering that the gain is found correctly when indexes such as significant digits meet the requirements, thereby realizing the calibration of the pipeline ADC. The method overcomes the defect of low traditional calibration precision in the high-speed high-precision pipeline ADC, has the characteristics of high efficiency, rapidness and accuracy, and is relatively suitable for calibrating the high-speed high-precision pipeline ADC.
Description
Technical Field
The invention belongs to the field of analog integrated circuits, and particularly relates to a front-end calibration method of a pipeline ADC (analog to digital converter) based on a minimum quantization error.
Background
The pipeline ADC structure is shown in FIG. 1, an input signal is sampled by a sample-and-hold circuit and then is sent to the pipeline unit ADC, and each unit ADC alternately performs sampling and residue difference amplification under the control of a two-phase non-overlapping clock. In the unit ADC, sampling phase time signals are simultaneously sampled by a multiplication digital-to-analog converter MDAC and a sub-ADC, and the sub-ADC generates a digital code Di through comparison; when the phase is kept, Di is subtracted from the input signal through the MDAC to generate a residual difference, the MDAC amplifies the residual difference, and the amplified residual difference is sent to the next stage to be used as the input signal of the next stage. The MDAC input-output relationship is as follows:
wherein Gain is the Gain of MDAC, and A is the intermediate transit of MDACOpen loop gain of amplifier, VrefIs a reference voltage, CfFor feedback capacitance, CiTo sample the capacitance, CpThe parasitic capacitance of the input end of the operational amplifier comprises an input tube parasitic capacitance Cgs、CgbAnd Cgd. The traditional MDAC can realize the high Gain requirement of the operational amplifier in the low-speed low-precision pipeline ADC, so that the Gain of the MDAC is approximately equal to the ideal value, namely constant
However, as the pipeline ADC develops towards high speed and high precision, the high speed and high precision pipeline ADC has higher and higher requirements on the unit gain and bandwidth product of the operational amplifier, the high bandwidth and high gain operational amplifier is difficult to realize, and the MDAC gain is not equal to a constant any more
Thereby, gain errors occur, which brings nonlinearity and further affects the performance of the ADC. In recent years, high-speed and high-precision pipeline ADCs usually sacrifice operational amplifier gain, ensure the operational amplifier speed, determine each stage of gain through a calibration algorithm, and further reduce the nonlinearity of the pipeline ADC.
Disclosure of Invention
The invention aims to provide a front-end calibration method of a pipeline ADC based on a minimum quantization error for the pipeline ADC, which is used for calibrating the front N-1-level gain of the ADC, and has the advantages of less analog quantity required by calibration, high calibration speed and high precision. The method can be used in the field of high-speed high-precision pipeline ADC calibration.
The technical scheme of the invention is as follows:
a front-end calibration method of a pipeline ADC based on minimum quantization error is disclosed, wherein the pipeline ADC has N stages, wherein N is a positive integer greater than 1; the pipeline ADC comprises a sub-stage ADC of the first N-1 stages and a flash memory type ADC of the Nth stage;
before calibration, obtaining the digital output D of each stage in the pipeline ADC by simulating the pipeline ADC circuitout；
Obtaining the digital output D of the flash memory type ADC of the Nth level according to simulationout(Flash)Computing the pipelineThe analog output of the front N-1 stage of the ADC comprises the following specific steps:
1.1 digital output D of flash ADC obtained by simulationout(Flash)Analog input V restored to flash ADC by restoring formulain(Flash)Analog input V of the flash ADCin(Flash)I.e. the analog output V of the N-1 stage of the pipeline ADCout(N-1)；
The reduction formula is
Where m is the number of bits of the flash ADC, VrefIs a reference voltage of the pipelined ADC;
1.2 setting the Gain (N-1) of the N-1 st stage as an ideal value, and then outputting the digital output D of the N-1 st stage obtained by simulationout(N-1)And 1.1 obtaining the analog output V of the N-1 th stageout(N-1)Reducing by using a calibration formula to obtain the N-1 stage input voltage Vin(N-1)The input voltage of the N-1 th stage is the analog output V of the N-2 nd stageout(N-2)；
The calibration formula is
Wherein C isiA sub-stage ADC internal sampling capacitor of the pipeline ADC;
1.3 sequentially obtaining analog output of N-1 stages in front of the pipeline ADC according to the method in the step 1.2;
calibrating the gain of the front N-1 stage of the pipeline ADC according to the analog output of the front N-1 stage of the pipeline ADC and the digital output obtained by simulation obtained in the above steps, and starting to correct the gain from the first stage of the pipeline ADC until the front N-1 stage of the pipeline ADC is corrected in sequence, wherein the front end is calibrated once;
the step of correcting the nth stage gain of the pipeline ADC comprises the following steps, wherein N is any one positive integer from 1 to N-1:
2.1: setting gains of other stages except the gain from the first stage to the nth stage in the pipeline ADC to be ideal values, wherein the gain from the first stage to the nth-1 stage is calibrated gain;
2.2: sequentially taking values of the nth gain from the left side and the right side of the ideal value of the nth gain in a fixed step length, and taking one nth gain value gain (n) every time to output the nth analog output V according to a calibration formulaout(n)And an nth order digital output Dout(n)Reducing to obtain nth-stage input voltage Vin(n)Said obtained nth stage input voltage Vin(n)Is an analog output V of the (n-1) th stageout(n-1)；
The calibration formula is
2.3: outputting the n-1 level digital output D obtained by simulationout(n-1)And the n-1 th stage analog output V obtained in step 2.2out(n-1)Reducing according to a calibration formula to obtain the n-1 th-level input voltage Vin(n-1)I.e. the analog output V of the (n-2) th stageout(n-2)When the gain of the (n-1) th stage in the formula is the gain of the (n-1) th stage after calibration;
2.4: sequentially reducing according to the step 2.2 and the step 2.3 to obtain a first-stage input voltage Vin(1)；
2.5: to the first-stage input voltage V obtained by reductionin(1)Carrying out fast Fourier transform analysis and calculation to obtain the effective digit;
2.6: and analyzing the significand obtained by calculating each nth gain value gain (n) obtained in the step 2.2, wherein the value gain (n) of the nth gain corresponding to the maximum value of the significand is the nth gain after calibration.
The invention has the beneficial effects that: the calibration method provided by the invention can obviously reduce the nonlinearity of the pipeline ADC, improves the defect of low traditional calibration precision in the high-speed high-precision pipeline ADC, and has the characteristics of high efficiency, rapidness and accuracy.
Drawings
FIG. 1 is a block diagram of a pipelined ADC;
FIG. 2 is a first stage quantization error model of a pipeline ADC;
FIG. 3 is a model of the total quantization error of a pipeline ADC;
fig. 4 is a flowchart of a front-end calibration method of a pipelined ADC based on a minimum quantization error according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and specific embodiments:
as shown in fig. 2, for the N-bit pipeline ADC, the signal flows into the Stage1 through the sample-and-hold circuit, the sampling phase time signal is simultaneously sampled by the sub-ADC and the MDAC, and the signal is compared by the sub-ADC to generate a digital output Di; when the phase is kept, the digital code Di is restored by a DAC in the MDAC and is differed with the input signal, and then the digital code Di is amplified to generate a residual difference voltage Vres. In this process, the sub-ADC quantizes the input signal to generate a quantization error epsilonq. The input-output relationship is as follows:
D＝Vin+εq(3)
Vres＝Gain*εq(4)
in FIG. 2, the quantization errors of the stages other than the first stage are represented by εqbShows that the first-stage gain G is found when the calibration algorithm is used for calibration as shown in formula (5)d1＝G1Then, the error between the restored signal and the original signal is obtained as
In FIG. 3, the quantization error per stage is represented by εqiShowing that i takes 1 to N-1, and when the gain G of the first to N-1 stages is found through calibration of a calibration algorithmdi＝GiThen, the error between the restored signal and the original signal is obtained as
As can be seen from the formula (4), when the calibration is performedAfter calibration, calibrating gain G of each stage of pipeline ADCdiAnd the actual gain GiThe closer, DoutAnd VinThe smaller the error between, the higher the calibration accuracy.
From equation (6), the quantization error ε of the first stage can be foundq1Quantization error epsilon of second stageq2To DoutLarge influence, third-level quantization error epsilonq3More than second-stage quantization error epsilonq2Difference pair DoutThe influence is large, and so on in the following stages. Therefore, we calibrate each stage of Gain starting with calibrating the first stage of Gain 1.
The invention searches the gain of each stage of the pipeline ADC based on the MATLAB program.
Before calibration, the digital output D of each stage in the pipeline ADC is obtained by an analog simulation pipeline ADC circuitoutAnd then according to the digital output D of the flash memory type ADC of the Nth level obtained by simulationout(Flash)Calculating the analog output of the front N-1 stage of the pipeline ADC, which comprises the following specific steps: the digital output D of the flash memory ADC obtained by simulationout(Flash)Analog input V restored to flash ADC by restoring formulain(Flash)Analog input V of flash ADCin(Flash)I.e. the analog output V of the N-1 stage of the pipeline ADCout(N-1)(ii) a Reduction formula is
Where m is the number of bits of the flash ADC, VrefIs the reference voltage of the pipelined ADC. Setting the Gain (N-1) of the (N-1) th stage as an ideal value, and outputting the digital output D of the (N-1) th stage obtained by simulationout(N-1)And 1.1 obtaining the analog output V of the N-1 th stageout(N-1)Obtaining the N-1 stage input voltage V by using a calibration formulain(N-1)I.e. the analog output V of the N-2 th stageout(N-2)(ii) a The calibration formula is
Wherein C isiA sub-stage ADC internal sampling capacitor of the pipeline ADC; and sequentially obtaining the analog output of the front N-1 stages of the pipeline ADC according to the method.
When the first-stage Gain1 of the pipeline ADC is calibrated, the gains of other stages are set to be ideal Gain values, the first-stage Gain1 takes values from the left side and the right side of the ideal values in fixed step length, and the ideal value of each stage of Gain passes through
Determining; using the resulting analog output V of the first stageout1And a digital output D of the first stageout1Reducing to obtain a first-stage input voltage Vin1For the restored first stage input voltage Vin1And performing Fast Fourier Transform (FFT) analysis to calculate the effective digit ENOB. And storing ENOB obtained by calculating each value of the first-stage Gain 1. And finally, analyzing ENOB corresponding to all the first-stage Gain values, wherein the Gain value corresponding to the maximum value of the ENOB is the first-stage Gain 1. The first-stage gain is considered to be the first-stage actual gain at this time.
For the value of the fixed step length, the smaller the step length, the more times of calibration are needed, the more accurate the calibration is, but the longer the time is needed, the one in ten thousand is taken in the embodiment; for the times of each level of gain values from the left side and the right side of the ideal value in fixed step length, errors generally do not occur when the number of the gain values is not less than ten thousand, and the tolerance range of the errors is also large.
Similar calibration is done for the second stage Gain 2. When the second-stage Gain is calibrated, the gains of other stages except the first stage are set as ideal Gain values, the second-stage Gain2 is obtained from the left side and the right side of the ideal value in fixed step length, and the second-stage analog output V is utilizedout2And a second stage digital output Dout2Reducing to obtain a first-stage analog output Vout1Then continuing to output V to the first-stage simulation by using the calibration formulaout1Reducing to obtain a first-stage input voltage Vin1To V pairout1Reduction is carried out to obtain Vin1The first stage Gain1 is obtained by using Gain1 which has been calibrated. For V after reductionin1An FFT analysis was performed to calculate ENOB. And storing ENOB obtained by calculating each value of Gain 2. Finally, ENOB corresponding to all second-stage gain values is analyzed, and the increase corresponding to the maximum value of ENOBThe Gain value is the second stage Gain 2. The second-stage gain is considered to be the second-stage actual gain at this time.
For the third stage, the fourth stage and the N-1 th stage gain calibration methods are similar to the second stage gain calibration method.
When the front N-1 stage gain of the pipeline ADC is calibrated, the input signal V of the pipeline ADC is obtained by restoringinFor V after reductioninAnd performing FFT analysis, and calculating to obtain an effective digit total harmonic distortion spurious-free dynamic range ENOB THD SFDR so as to obtain the performance of the pipeline ADC system.
In summary, the gain calibration algorithm is used for calibrating the gain of each stage of the pipeline ADC, the method has the characteristics of high efficiency, rapidness and accuracy, can help pipeline ADC designers to rapidly and accurately obtain the design performance of the analog part of the ADC, and saves a large amount of time.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (1)
1. A front-end calibration method of a pipeline ADC based on minimum quantization error is disclosed, wherein the pipeline ADC has N stages, wherein N is a positive integer greater than 1; the pipeline ADC comprises a sub-stage ADC of the first N-1 stages and a flash memory type ADC of the Nth stage; it is characterized in that the preparation method is characterized in that,
before calibration, obtaining the digital output D of each stage in the pipeline ADC by simulating the pipeline ADC circuitout；
Obtaining the digital output D of the flash memory type ADC of the Nth level according to simulationout(Flash)Calculating the analog output of the front N-1 stage of the pipeline ADC, which comprises the following specific steps:
1.1 digital output D of flash ADC obtained by simulationout(Flash)Analog input V restored to flash ADC by restoring formulain(Flash)Analog input V of the flash ADCin(Flash)I.e. the analog output V of the N-1 stage of the pipeline ADCout(N-1)；
The reduction formula is
Where m is the number of bits of the flash ADC, VrefIs a reference voltage of the pipelined ADC;
1.2 setting the Gain (N-1) of the N-1 st stage to an ideal value and outputting the simulated digital output D of the N-1 st stageout(N-1)And 1.1 obtaining the analog output V of the N-1 th stageout(N-1)Reducing by using a calibration formula to obtain the N-1 stage input voltage Vin(N-1)The N-1 th stage input voltage Vin(N-1)I.e. the analog output V of the N-2 th stageout(N-2)；
The calibration formula is
Wherein C isiA sub-stage ADC internal sampling capacitor of the pipeline ADC;
1.3 sequentially obtaining analog output of N-1 stages in front of the pipeline ADC according to the method in the step 1.2;
calibrating the gain of the front N-1 stage of the pipeline ADC according to the analog output of the front N-1 stage of the pipeline ADC and the digital output obtained by simulation obtained in the above steps, and starting to correct the gain from the first stage of the pipeline ADC until the front N-1 stage of the pipeline ADC is corrected in sequence, wherein the front end is calibrated once;
the step of correcting the nth stage gain of the pipeline ADC comprises the following steps, wherein N is any one positive integer from 1 to N-1:
2.1: setting gains of other stages except the gain from the first stage to the nth stage in the pipeline ADC to be ideal values, wherein the gain from the first stage to the nth-1 stage is calibrated gain;
2.2: sequentially taking values of the nth gain from the left side and the right side of the ideal value of the nth gain in a fixed step length, and taking one nth gain value gain (n) every time to output the nth analog output V according to a calibration formulaout(n)And an nth order digital output Dout(n)Reducing to obtain nth-stage input voltage Vin(n)Said obtained nth stage input voltage Vin(n)Is as followsn-1 stage analog output Vout(n-1)；
The calibration formula is
2.3: outputting the n-1 level digital output D obtained by simulationout(n-1)And the n-1 th stage analog output V obtained in step 2.2out(n-1)Reducing according to a calibration formula to obtain the n-1 th-level input voltage Vin(n-1)I.e. the analog output V of the (n-2) th stageout(n-2)When the gain of the (n-1) th stage in the formula is the gain of the (n-1) th stage after calibration;
2.4: sequentially reducing according to the step 2.2 and the step 2.3 to obtain a first-stage input voltage Vin(1)；
2.5: to the first-stage input voltage V obtained by reductionin(1)Carrying out fast Fourier transform analysis and calculation to obtain the effective digit;
2.6: and analyzing the significand obtained by calculating each nth gain value gain (n) obtained in the step 2.2, wherein the value gain (n) of the nth gain corresponding to the maximum value of the significand is the nth gain after calibration.
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| CN108134606B (en) * | 2018-01-15 | 2021-03-30 | 电子科技大学 | Assembly line ADC based on digital calibration |
| CN108233927A (en) * | 2018-02-05 | 2018-06-29 | 电子科技大学 | A kind of high-precision pipeline ADC front-end calibration method |
| CN108647406A (en) * | 2018-04-24 | 2018-10-12 | 北京新岸线移动多媒体技术有限公司 | The design method of circuits at different levels in a kind of production line analog-digital converter |
| CN109084931B (en) * | 2018-07-19 | 2020-05-01 | 电子科技大学 | Sensor maladjustment calibration method |
| CN110061743B (en) | 2019-04-17 | 2021-01-22 | 中国电子科技集团公司第二十四研究所 | Error extraction method for foreground digital calibration of pipeline analog-to-digital converter |
| CN110531296B (en) * | 2019-08-09 | 2022-05-10 | 格威半导体(厦门)有限公司 | Gain calibration method of battery management system |
| CN110504967B (en) * | 2019-08-30 | 2022-04-22 | 电子科技大学 | Interstage gain mismatch correction method of pipeline ADC (analog to digital converter) |
| CN112600557B (en) * | 2020-12-16 | 2023-08-01 | 东南大学 | Pipelined ADC digital domain gain calibration method |
| CN112737583B (en) * | 2020-12-28 | 2022-10-25 | 南京邮电大学 | High-precision assembly line ADC and front-end calibration method |
| CN113114247B (en) * | 2021-04-19 | 2022-05-24 | 电子科技大学 | Pipeline ADC interstage gain calibration method based on comparison time detector |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100834A (en) * | 1998-05-15 | 2000-08-08 | Pairgain Technologies, Inc. | Recursive multi-bit ADC with predictor |
| CN1322404A (en) * | 1999-09-20 | 2001-11-14 | 诺基亚网络有限公司 | Method of calibrating analog-to-digital converter, and calibration equipment |
| CN102177657A (en) * | 2008-08-12 | 2011-09-07 | 美国亚德诺半导体公司 | Correlation-based background calibration of pipelined converters with reduced power penalty |
-
2017
- 2017-08-17 CN CN201710706638.0A patent/CN107359878B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100834A (en) * | 1998-05-15 | 2000-08-08 | Pairgain Technologies, Inc. | Recursive multi-bit ADC with predictor |
| CN1322404A (en) * | 1999-09-20 | 2001-11-14 | 诺基亚网络有限公司 | Method of calibrating analog-to-digital converter, and calibration equipment |
| CN102177657A (en) * | 2008-08-12 | 2011-09-07 | 美国亚德诺半导体公司 | Correlation-based background calibration of pipelined converters with reduced power penalty |
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