CN1716772A

CN1716772A - Gate clock circuit and relative method

Info

Publication number: CN1716772A
Application number: CN 200510087422
Authority: CN
Inventors: 曾柏谕
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2005-07-22
Filing date: 2005-07-22
Publication date: 2006-01-04

Abstract

The gate clock circuit provides one gate clock based on one clock and one enable signal. In the implementation example of the present invention, the gate clock circuit includes one transmission unit, one latch unit and one arithmetic unit. When the clock is in low level, the transmission unit transmits the enable signal to the latch unit to make the latch signal of the latch unit follow the inverted enable signal. When the clock is in high level, the transmission unit stops transmitting the enable signal to make the latch signal latched in the latch unit. The arithmetic unit performs NOR operation on the latch signal and the reverted clock signal to generate the gate clock.

Description

Door control clock circuit and correlation technique

Technical field

The present invention relates to a kind of door control clock circuit (clock gating circuit) and correlation technique, particularly relate to and a kind ofly can prevent surging (glitch) and the door control clock circuit of realizing with the circuit arrangement of simplifying.

Background technology

Electronic circuit is one of most important hardware foundation of modernized information-intensive society.In order to realize complicated various function, modern electronic circuit compiles a plurality of circuit blocks (block), and each circuit block can be used for realizing the function on basis.Integrate the discrete function of each circuit block, electronic circuit just can be realized out complicated allomeric function.For instance, optionally some circuit blocks of activation come into operation and make other circuit anergies and do not operate under different situations, just can change the operating mode of electronic circuit, thereby bring into play various function.

In general, each circuit block in the electronic circuit can be controlled by a corresponding enable signal respectively to determine whether to want activation.For instance, as if the enable signal that a circuit block is sent a high level, but this circuit block comes into operation with regard to activation; Otherwise if send low level enable signal, this circuit block will anergy and decommission.

On the other hand, those skilled in the art knows, and make the different circuit blocks integrating operation successfully in the same electronic circuit, and available clock triggers the time sequences of each piece, the opportunity that makes each circuit block coordinate to operate each other according to clock.But, if also continue to trigger its running with clock behind a certain circuit block anergy, this circuit block still can continue consumed power usually.This is that if trigger this circuit block with clock constantly, some circuit unit in this circuit block still can operate, and has also just caused meaningless power consumption because the circuit block of anergy may just suspend the reception signal, suspend and send signal.

For fear of the meaningless power consumption of anergy circuit block, can adopt the technology of gated clock, when a circuit block anergy, synchronously stop to trigger this circuit block with clock.More particularly, when when a circuit block is realized Clock Gating Technique, will be according to the enable signal and clock generating one gated clock originally of this circuit block, and change with gated clock and trigger this circuit block.When enable signal during this circuit block of activation, this gated clock just and clock synchronization originally, the rolling country that changes with height periodically triggers this circuit block and follows the sequential running.During enable signal made this circuit block anergy, gated clock can be maintained at fixing level (for example being low level), no longer triggers this circuit block.So just can be at this circuit block anergy reducing power consumption during.

In the prior art, known door control clock circuit be with a trigger and one and door produce a gated clock according to an activation signal and a clock.Trigger can receive enable signal, and provides an output signal under the triggering of clock.That is to say that trigger can be the rising that edge triggers and to the enable signal sampling, and sampling result kept one-period (one-period of clock) in output signal of clock, when sub-sampling down, upgrade output signal according to new sampling result again.With door then to the output signal of trigger and clock carry out with computing to draw gated clock.

Yet, in existing door control clock circuit, because trigger can be kept the sampling result of enable signal one whole clock cycle, when carrying out with computing with door, former and later two cycles in the gated clock are interfered with each other, form surging (glitch), influence the clock quality of gated clock, also cause the running mistake of circuit easily.In addition, the layout area of trigger is big, circuit arrangement also comparatively complicated (general trigger may need 4 or more gate, and the CMOS (Complementary Metal Oxide Semiconductor) transistor of many groups is arranged in each gate again).This also becomes a shortcoming of existing door control clock circuit.

Summary of the invention

Therefore, the present invention proposes the door control clock circuit that the surging phenomenon was simplified and can be avoided to a kind of circuit structure, to overcome the shortcoming of prior art.

In preferred embodiment of the present invention, door control clock circuit of the present invention can be provided with a transmission unit (similarly being transmission gate), and a latch units and an arithmetic element are to provide a gated clock according to a clock and an activation signal.Wherein, transmission unit is controlled by clock; When the level of clock was low level, transmission unit can transfer to latch units with enable signal, and the latching signal and will follow anti-phase enable signal of latch units output.When clock was high level, transmission unit will stop enable signal being transferred to latch units, and latch units will latch the level that this latchs signal, and it is remained unchanged; Become low level once again up to clock, transmission unit begins enable signal is transferred to latch units once again, also can follow anti-phase enable signal once again and latch signal.And arithmetic element promptly can be used as gated clock to inversion clock and latch the result that signal is done NOR-operation.

In the present invention, latch signal to enable signal sampling keep during can contain clock be maintained at high level during, so just can avoid surging of the prior art.And all available circuit arrangement of simplifying of the transmission unit among the present invention, latch units and arithmetic element realizes, this makes that also the shared layout area of door control clock circuit of the present invention is littler, easier circuit block and the electronic circuit that is implemented in high aggregation degree.

Description of drawings

Fig. 1 is the function block schematic diagram of a typical door control clock circuit.

Fig. 2 is the schematic diagram of each related signal waveform sequential in Fig. 1 door control clock circuit.

Fig. 3 is the function block schematic diagram of door control clock circuit of the present invention.

Fig. 4 is the schematic diagram of each related signal waveform sequential in Fig. 3 door control clock circuit.

Fig. 5 is the truth table of door control clock circuit of the present invention among Fig. 3.

The schematic diagram that Fig. 6 uses for the present invention.

The reference numeral explanation

10,20 door control clock circuits

12 triggers

14 with the door 16 circuit blocks

22 transmission units, 24 latch units

26 arithmetic elements, 28 inverters

30 transmission gates, 32 anti-or devices

EN0, EN enable signal Op signal

GCK, GCLK gated clock CK, CLK clock

CLKX inversion clock LT latchs signal

T0-t9, t0 '-t6 ' time point

The N1-N2 node

Embodiment

Please refer to Fig. 1; Fig. 1 is that a typical door control clock circuit 10 is the function block schematic diagram that a circuit block 16 produces gated clock.Circuit block 16 is controlled by an activation signal EN0 with according to the high/low and activation/anergy of the level in this activation signal; Circuit block 16 also is provided with a clock end to accept the triggering of clock.And door control clock circuit 10 can be realized the technology of gated clock at circuit block 16, to produce gated clock GCK according to enable signal EN0 and cycle clock CK; Come circuits for triggering piece 16 with gated clock CGK, just can realize the technology of gated clock circuit block 16.

As shown in Figure 1, be provided with in the typical door control clock circuit 10 trigger 12 (for example being a d type flip flop) and one and the door 14.Trigger 12 is an input signal with enable signal EN0, and under the triggering of clock CK output signal op.With 14 at door signal op and clock CK are carried out and computing, with the result of computing be exactly gated clock GCK.The operation principle of door control clock circuit 10 and situation then can be illustrated by Fig. 2.

Please refer to Fig. 2, and in the lump with reference to figure 1; Fig. 2 is the schematic diagram of typical door control clock circuit 10 related signal waveform sequential when running.The transverse axis of Fig. 2 is the time, and the level (similarly being voltage level) that the longitudinal axis of each signal is then represented signal waveform just.In enable signal EN0, enable signal EN0 keep high level during just representative to make circuit block 16 (Fig. 1) activation during; Otherwise, enable signal EN0 be maintained at low level during, 16 of circuit blocks can be controlled and anergy.Clock CK then is periodically variable standard time clock.

Along with the edge that rises of clock CK triggers, trigger 12 can be extracted/take a sample enable signal EN0 at the edge that rises of clock CK, and in its output signal op, the result that will extract keeps a clock cycle, upgrades the result that extracts when another clock rises edge once again.As shown in Figure 2, at time point t0 ', the edge that rises of clock CK triggers the extract level of enable signal EN0 of trigger 12; Because this moment, enable signal EN0 was a high level, trigger 12 will will be elevated to high level for low level output signal op at time point t0, and continue to be maintained at high level after the delay of one running period originally.Up to time point t1 ', clock CK triggers trigger 12 to rise edge once again, extract the once again again level of enable signal EN0 of trigger 12; At this moment, because enable signal EN0 has changed low level into, trigger 12 will transfer output signal op to low level at time point t1 after the delay of one running period.

In other words, under the running of trigger 12, can be in signal op during the activation among the enable signal EN0 form with the clock cycle synchronous during.The picture in Fig. 2, just become among the signal op during the activation of enable signal EN0 between time point t2-t4 and contained between the high period of two clock cycle, also with regard to signal op between the high period between time point t3-t5.In like manner, enable signal EN0 has also just become between the high period that contained for two clock cycle among the signal op (put in real time t7-t9 during) during the activation of time point t6-t8.Because signal op can will be synchronized with the cycle of clock during activation/anergy, after with signal op and clock CK work and computing, the gated clock GCK that it generated should just can keep the cycle during the activation, and the cycle during the anergy is restrained, and realizes the purpose of gated clock.Just as the example among Fig. 2, signal op can via and the running of door 12 and in gated clock GCK, keep two cycles between time point t3-t5, with corresponding enable signal EN0 during the activation between time point t2-t4.Signal op also can keep two cycles between time point t7-t9 in gated clock GCK, corresponding enable signal EN0 is during the activation between time point t6-t8.Relatively, signal op also can restrain the one-period (making gated clock GCK be maintained at low level) between time point t5-t7 in gated clock GCK, comes corresponding enable signal EN0 during the anergy between time point t4-t6, by that analogy.

Yet when 10 runnings of typical door control clock circuit, regular meeting causes the generation of surging, especially when signal op will change low level into by high level (just change during activation/anergy during).As shown in Figure 2, during because of the rising edge and trigger the low level of the enable signal EN0 that extracts of clock CK, just can make signal op change low level at time point t1 ' when trigger 12 through one section running time delay by original high level.But, during this section, clock CK has been raised to high level, so signal op just can't during this period of time restrain clock CK, causes the generation of surging phenomenon.In like manner, near time point t5, t9, equally also can stay surging because of signal op can not restrain clock CK in real time.Surging will influence the clock quality of gated clock GCK, also causes circuit erroneous action easily, forms the interference to circuit.

If will overcome surging with typical door control clock circuit 10, can in typical gate control circuit 10, set up a delayer, after being postponed, clock CK inputs to again and door 12, come to do and computing with the clock after postponing with signal op.The clock after postponing, it rises the period that edge can be avoided signal op level transitions, avoids the generation of surging.But, delayed clock need increase delayer, and the layout area of door control clock circuit and power consumption are increased.And using delayed clock that gated clock is postponed in clock originally, this can reduce the nargin (margin) on the sequencing control, is unfavorable for that high clock or sequential require comparatively strict application.

Please refer to Fig. 3.Fig. 3 is the function block schematic diagram of door control clock circuit one embodiment 20 of the present invention.Door control clock circuit 20 can provide a gated clock GCLK according to a clock CLK and enable signal EN; Be provided with a transmission unit 22, a latch units 24 and an arithmetic element 26 in the door control clock circuit 20.Transmission unit 22 can realize with a transmission gate 30, and it can control the node N1 that whether enable signal EN will be transferred to latch units 24 according to clock CLK (with inversion clock CLKX, just the anti-phase signal of clock CLK).The inverter 28 of 24 available two back-to-back (back-to-back) connections of latch units is realized; Latch units 24 is at the signal of node N2 and latchs signal LT.Then can be provided with a NOR gate 32 in the arithmetic element 26.NOR gate 32 can and latch signal LT and do NOR-operation inversion clock CLKX, and produces gated clock GCLK.

The situation of door control clock circuit 20 runnings of the present invention can be described below.When clock CLK was low level, transmission unit 22 transferred to enable signal EN the node N1 of latch units 24 with regard to conducting; When clock CLK was high level, transmission unit 22 stopped enable signal EN is transferred to latch units 24 with regard to stop conducting.When transmission unit 22 transmission enable signal EN, node N2 latchs signal LT and will follow anti-phase enable signal EN; When transmission unit 22 stops to transmit enable signal EN, latch units 24 will latch the level of signal LT, it is kept necessarily and no longer changes with anti-phase enable signal EN, begin once again enable signal EN is transferred to node N1 up to transmission unit 22, latch the level variation that signal LT just can follow anti-phase enable signal EN once again.NOR gate 32 in the arithmetic element 26 be exactly with inversion clock CLKX with latch signal LT and do NOR-operation, with the result of NOR-operation as gated clock GCLK.In the equivalence, when the level that latchs signal LT was latched fixedly, arithmetic element 26 will be according to latching the variation that level that signal is latched decides gated clock GCLK whether will follow clock CLK.When clock CLK is maintained at the positive half period of high level (CLK=1), latchs signal LT and be latched.If latching signal LT is latched in low level (LT=0), the result of arithmetic element 26 NOR-operations will make gated clock GCLK follow clock CLK.Otherwise if latching signal LT is latched in high level (LT=1), the result of arithmetic element 26 NOR-operations will restrain the positive half period among the gated clock GCLK, makes it can not change high level into.

The operation situation of above-mentioned each assembly/unit can be summarized in Fig. 5; The truth table that is door control clock circuit 20 of the present invention that Fig. 5 shows.When clock CLK is high level (CLK=1), latchs signal LT and be latched.Be latched in low level (LT=0) when latching signal LT, then gated clock GCLK follows clock CLK (that is GCLK=1).Be latched in high level (LT=1) when latching signal LT, then gated clock GCLK can be suppressed (that is GCLK=0).

For further specifying the situation of door control clock circuit 20 runnings of the present invention, please refer to Fig. 4 (and in the lump with reference to figure 3); Fig. 4 signal be exactly door control clock circuit 20 runnings the time each related signal waveform sequential schematic diagram.The transverse axis of Fig. 4 is the time, and the longitudinal axis of each signal is represented the level height of signal waveform.As shown in Figure 4, enable signal EN be maintained at high level during be exactly activation during, be maintained at during low level be exactly anergy during.Clock CLK then is the periodically standard time clock of height variation of level.When clock CLK was low level, transmission unit 22 (Fig. 3) conducting made and latchs signal LT and follow anti-phase enable signal.Picture is in Fig. 4, and clock CLK keeps low level after time point t0, will change with the variation of enable signal EN and latch signal LT anti-phasely.Arrived time point t1, clock CLK is increased to high level, transmission unit 22 stop conductings, and latch units 24 will latch the level that latchs signal LT, makes it fixedly be maintained at the level of time point t1.In the example of Fig. 4, be low level owing to latch signal LT at time point t1, will after time point t1, be latched so latch signal LT in low level.Arrived time point t2 ', clock CLK changes low level once again into, transmission unit 22 begins conducting once again, latch units 24 can be after the delay of one running period, begin to make in time point t2 once again and latch signal LT and follow anti-phase enable signal EN, be increased to high level again once again up to clock CLK next time.In the example of Fig. 2,, can be converted to high level at time point t2 and follow enable signal EN so latch signal LT because time point t2 ' back enable signal EN has changed low level into.Control the cycle (just will latch signal LT and clock CLK does and computing) that whether will restrain among the clock CLK according to the high-low level that latchs signal LT, that obtain is exactly gated clock GCLK.

By foregoing description as can be known because the running of latch units 24 postpones, the present invention can with latch signal LT keep definite value during prolong, be enough to contain fully the positive half period (just clock CLK is the half period of high level) of clock CLK.So, the present invention just can avoid the generation of surging phenomenon.By the explanation of Fig. 2 as can be known, existing/typical door control clock circuit 10 when producing gated clock GCK with signal op since the time of signal op level transitions can and clock CK in the positive half period of high level overlap, so can form surging.In comparison, the present invention is according to latching signal LT when producing gated clock GCLK, latch signal LT only can be when clock CK be low level transition level.So, latch time of signal LT level transitions just must not can with clock CLK in the positive half period of high level overlap, also therefore, the present invention can avoid the interference of surging to gated clock GCLK.

In general, because the convention of sequencing control, enable signal is by being bound to when clock is low level the opportunity that low level changes high level into, so that keep fixing time (set-up time) with the edge that rises of a time clock.In the present invention, latch the anti-phase variation that signal LT can follow enable signal EN during for low level at clock CLK, so latch signal LT when changing by high level that also can to occur in clock CLK low level opportunity be low level into, the positive half period of a leading time clock anti-phasely.Just as in Fig. 4, enable signal EN changes high level into by low level between time point t0 to t1, latchs signal LT and also can anti-phasely accordingly change low level into by high level.On the other hand, when latching signal LT will change high level into by low level the time, all be usually, just as the situation that is taken place when the time point t2 because latch signal LT when after being latched, restarting again to follow enable signal EN.At this moment, because the running of latch units 24 postpones, latch signal LT and be bound to after clock CLK has become low level, just can begin transition level.Comprehensive above-mentioned two kinds of factors, the present invention latchs the certain only meeting of signal LT just change level when clock CLK is low level, and then has prevented the generation of surging.

Be that example illustrates once again with Fig. 4.Between time point t3, t4, enable signal EN begins to change into high level, latchs signal LT and also changes into low level thereupon anti-phasely.Arrived between the time point t5-t6, enable signal EN changes low level into, but during this because CLK be high level, so latch units 24 also can latch the level of signal LT, make it be unlikely change.When time point t6 ', clock CLK changes low level into, and latching that signal LT just can begin to prepare to raise anti-phasely is the low level of high level with reflection enable signal EN.So, latch signal LT rise edge and fall edge not can and the high period of clock CLK between overlap and take place, also avoided the phenomenon of surging.

In addition,, do not have the delay of great essence between gated clock GCLK that the present invention produced and the clock CLK,, can be applicable to that sequential requires comparatively strict circuit block/electronic circuit yet so the present invention can not influence the nargin of sequencing control by finding out among Fig. 4 yet.The present invention needn't introduce delayer and avoid surging, and its circuit framework is also more simplified than the typical case/prior art among Fig. 1.In Fig. 1, the trigger in typical case/available circuit needs 4 or more gate at least; In comparison, transmission unit of the present invention, latch units and arithmetic element all are the most basic logic modules, and its required layout area is littler, more can be applied to the electronic circuit of high aggregation degree.As seen from Figure 3, door control clock circuit 20 of the present invention only needs 6 pairs of CMOS (Complementary Metal Oxide Semiconductor) transistor (i.e. 6 p type metal oxide semiconductor transistors, 6 n-type metal oxide semiconductor transistor) just can realize the simplifying of sequitur door control clock circuit of the present invention.

Please refer to Fig. 6.The schematic diagram that Fig. 6 uses for the present invention.In not adopting the circuit block of Clock Gating Technique, each circuit unit (or secondary electronic circuit piece) all unifies to be subjected to the periodically triggering of clock, even enable signal is controlled some circuit unit anergy, the circuit unit of anergy still might be because of the triggering consumed energy and the power of clock.In order to reduce the power consumption during the anergy, can in circuit block, be integrated into door control clock circuit of the present invention (similarly being the door control clock circuit 20 among Fig. 3), going out gated clock, and change with gated clock and trigger each circuit unit according to enable signal and clock generating.When activation, gated clock is just the same with clock originally basically, the sequential that can periodically operate with each circuit unit of level height change triggers.When anergy, the cycle that level just changes in the gated clock will be restrained, and stops to trigger each circuit unit, also just can reduce the circuit power consumption during the anergy.

Generally speaking, compared to existing/typical door control clock circuit, door control clock circuit of the present invention can be avoided the surging phenomenon, circuit arrangement is also more simplified, the layout area that takies is also littler, also can in gated clock, not introduce the delay of essence, so the present invention is more suitable for being used for realizing Clock Gating Technique than existing door control clock circuit.Except embodiment shown in Figure 3, also available other the circuit of the transmission unit in the door control clock circuit of the present invention, latch units and arithmetic element is realized.For instance, transmission unit can be realized with single metal oxide semiconductor transistor.In addition, via the explanation of the aforementioned embodiment of the invention, those skilled in the art should can be extended to embodiments of the invention other application scenarios.For example, some circuit block is with the low level activation in the enable signal, high level anergy; Under this kind situation, can produce correct gate signal with the anti-phase back of enable signal as the signal EN among Fig. 3.Perhaps, having several different enable signals in some circuit block, similarly is to have in the static random-access memory circuit to read activation (read enable) and write two kinds of (or more kinds of) enable signals of activation (write enable); In this kind application, also can adopt technology of the present invention to come to produce the gated clock of a correspondence, or produce gated clock at the combination of enable signal for each enable signal.For example, if a certain circuit block can be accepted two enable signals, have only and when two enable signals all are high level, just understand the activation running.In this case, these two enable signals can be done and the result of computing to be used as be signal EN among Fig. 3, the gated clock that generates so just only can just have the cycle that height changes when two enable signals are all high level.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. door control clock circuit, in order to produce a gated clock signal, this door control clock circuit includes:

One transmission unit receives an activation signal, and a clock signal;

One latch units is connected to this transmission unit, latchs signal in order to produce one; And

One arithmetic element is carried out a logical operation in order to the anti-phase of this clock signal and this are latched signal, in order to produce this gated clock signal.

2. door control clock circuit as claimed in claim 1, wherein when this clock signal be that logic high and this latch signal when being logic low, this gated clock signal is followed this clock signal.

3. door control clock circuit as claimed in claim 1, wherein when this clock signal was logic low, this transmission unit was exported this enable signal to this latch units, and this latchs signal and follows the logic level of this enable signal and change.

4. the described door control clock circuit of claim 1, wherein when this clock signal is logic high, this transmission unit is not exported this enable signal to this latch units, this latchs signal and is maintained at a fixed logic level, and this fixed logic level is that this latchs the level of signal to a preceding clock signal when being logic low.

5. door control clock circuit according to claim 1, wherein this transmission unit is a transmission gate.

6. door control clock circuit according to claim 1, wherein this latch units includes the inverter of two back-to-back connections.

7. door control clock circuit according to claim 1, wherein this arithmetic element includes a NOR gate.

8. door control clock circuit according to claim 1, wherein this arithmetic element with this latch signal and this clock signal through a NOR-logic computing to produce this gated clock signal.

9. the method that produces of a gated clock signal, this method includes:

Receive an activation signal and a clock signal;

Latch signal according to this enable signal and this clock signal generation one;

This is latched the anti-phase of signal and this clock signal carry out a logical operation in order to produce this gated clock signal.

10. as gated clock signal production method as described in the claim 9, wherein when this clock signal is logic low, this latchs signal and follows the logic level of this enable signal and change; When this clock signal was logic high, this latched signal and is maintained at a fixed logic level, and this fixed logic level is that this latchs the level of signal to a preceding clock signal when being logic low.

11. as gated clock signal production method as described in the claim 9, wherein this arithmetic element with this latch signal and this clock signal through a NOR-logic computing in order to produce this gated clock signal.

12. as gated clock signal production method as described in the claim 9, wherein when this clock signal be that logic high and this latch signal when being logic low, this gated clock signal is followed this clock signal.