CN111613257B - Gating circuit and method for multi-phase clock signals and electronic equipment - Google Patents

Gating circuit and method for multi-phase clock signals and electronic equipment Download PDF

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CN111613257B
CN111613257B CN202010482043.3A CN202010482043A CN111613257B CN 111613257 B CN111613257 B CN 111613257B CN 202010482043 A CN202010482043 A CN 202010482043A CN 111613257 B CN111613257 B CN 111613257B
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signal
clock
gating
latch
enable
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CN111613257A (en
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马军亮
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Xian Unilc Semiconductors Co Ltd
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Xian Unilc Semiconductors Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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Abstract

The invention discloses a gate control circuit, a method and electronic equipment of multi-phase clock signals, wherein the gate control circuit comprises: the latch control circuit is used for latching the switch signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal; and the clock output circuit is used for performing gating processing on the multi-phase clock signals according to the at least one gating enabling signal so as to output the multi-phase clock gating signals. The invention can realize the gating of the multi-phase clock signal and avoid the direct high-frequency turnover of the multi-phase clock signal, so that a relevant circuit working by utilizing a four-phase frequency division clock generates turnover at the jumping edge of each clock, thereby causing unnecessary power consumption loss.

Description

Gating circuit and method of multi-phase clock signals and electronic equipment
Technical Field
The present invention relates to the field of digital circuits, and in particular, to a gate control circuit and method for multi-phase clock signals, and an electronic device.
Background
With the continuous update of DRAM (Dynamic Random Access Memory), the data frequency of DRAM is higher and higher, for example, the data frequency of the latest DRAM such as DDR4, LPDDR4, GDDR6 can reach up to 16 Gbps.
In a high frequency DRAM, in order to improve the quality of clock transmission, a clock is divided and clock tree transmission is often performed. To achieve high frequency data width, multiple frequency division clocks of different phases are required. Four-phase frequency division clocks (clock signals with the same frequency and 90-degree phase difference) are clock systems adopted by most high-frequency DRAMs at present, for example, a four-phase frequency division clock of 4GHz can realize a data transmission frequency of 16 Gbps. In addition, the four-phase clock provided by the four-phase clock system is utilized in many situations.
However, applicants have discovered that when a four-phase divided clock provided by a four-phase divided clock system is output directly to an associated circuit operating with the four-phase divided clock, for example: in high frequency DRAM, the four-phase frequency division clock is always inverted at high frequency, so that the relevant circuit is inverted at the transition edge of each clock, thereby causing unnecessary power consumption loss.
Disclosure of Invention
The embodiment of the application provides a gate control circuit, a gate control method and electronic equipment for multi-phase clock signals, and solves the technical problem that in the prior art, a four-phase frequency division clock always turns at a high frequency, so that a relevant circuit working by using the four-phase frequency division clock turns at the jumping edge of each clock, and unnecessary power consumption loss is caused.
In a first aspect, the present application provides the following technical solutions through an embodiment of the present application:
a gating circuit for a multi-phase clock signal, comprising: the latch control circuit is used for latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal; and the clock output circuit is used for performing gating processing on the multi-phase clock signals according to the at least one gating enabling signal so as to output the multi-phase clock gating signals.
In one embodiment, the multi-phase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, a phase difference between adjacent clock signals is 90 °, the switching signals of the clock gating at least include a first switching signal and/or a second switching signal, and the latch control circuit at least includes one latch module or two latch modules; the first latch module is configured to perform latch processing on the first switch signal under control of a first latch control signal to generate a first gating enable signal, and perform latch processing on the first gating enable signal under control of a second latch control signal to generate a second gating enable signal, where the first latch control signal includes the first clock signal and/or the third clock signal, and the second latch control signal includes the second clock signal and/or the fourth clock signal; the second latch module is configured to latch the second switch signal under the control of a third latch control signal to generate a third gating enable signal, and latch the third gating enable signal under the control of a fourth latch control signal to generate a fourth gating enable signal, where the third latch control signal includes the first clock signal and/or the third clock signal, and the fourth latch control signal includes the second clock signal and/or the fourth clock signal; the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal by a time lag or lead of one-half of the period of the first clock signal; the trigger level of the second latch control signal lags or leads the trigger level of the fourth latch control signal by a time lag or lead of one-half of the period of the first clock signal.
In one embodiment, the trigger level of the second latch control signal lags the trigger level of the first latch control signal by a quarter of the period of the first clock signal; the trigger level of the fourth latch control signal lags behind the trigger level of the third latch control signal by a time that is one-quarter of the period of the first clock signal.
In one embodiment, the latch module comprises two stages of latches, the two stages of latches being cascaded; the first-stage latch in the first latch module is used for latching the first switching signal under the control of the first latch control signal to generate a first gating enable signal; the second-stage latch in the first latch module is used for latching the first gating enable signal under the control of the second latch control signal to generate a second gating enable signal; the first-stage latch in the second latch module is configured to latch the second switching signal under the control of the third latch control signal to generate a third gating enable signal; and the second-stage latch in the second latch module is used for latching the third gating enable signal under the control of the fourth latch control signal to generate the fourth gating enable signal.
In one embodiment, the latch comprises a first tri-state not gate, a second tri-state not gate, and a first inverter; the input end of the first tri-state not gate is used as the input end of the latch, the output end of the first tri-state not gate is connected with the output end of the second tri-state not gate and the input end of the first inverter, and the output end of the first inverter is connected with the input end of the second tri-state not gate and is used as the output end of the latch; the low-level enabling end of the first tri-state not gate is used as a first enabling end of the latch, the high-level enabling end of the first tri-state not gate is used as a second enabling end of the latch, the low-level enabling end of the second tri-state not gate is used as a third enabling end of the latch, and the high-level enabling end of the second tri-state not gate is used as a fourth enabling end of the latch.
In one embodiment, an input terminal of the first stage latch of the first latch module is configured to receive the first switching signal, an output terminal of the first stage latch of the first latch module is configured to output the first gating enable signal, a first enable terminal of the first stage latch of the first latch module and a fourth enable terminal of the first stage latch of the first latch module are configured to receive the first clock signal, and a second enable terminal of the first stage latch of the first latch module and a third enable terminal of the first stage latch of the first latch module are configured to receive the third clock signal; the input end of the second-stage latch in the first latch module is used for receiving the first gating enable signal, the output end of the second-stage latch in the first latch module is used for outputting the second gating enable signal, the first enable end of the second-stage latch in the first latch module and the fourth enable end of the second-stage latch in the first latch module are used for receiving the second clock signal, and the second enable end of the second-stage latch in the first latch module and the third enable end of the second-stage latch in the first latch module are used for receiving the fourth clock signal; the input end of the first-stage latch in the second latch module is configured to receive the second switching signal, the output end of the first-stage latch in the second latch module is configured to output the third gating enable signal, the first enable end of the first-stage latch in the second latch module and the fourth enable end of the first-stage latch in the second latch module are configured to receive the third clock signal, and the second enable end of the first-stage latch in the second latch module and the third enable end of the first-stage latch in the second latch module are configured to receive the first clock signal; the input end of the second stage latch in the second latch module is configured to receive the third gating enable signal, the output end of the second stage latch in the second latch module is configured to output the fourth gating enable signal, the first enable end of the second stage latch in the second latch module and the fourth enable end of the second stage latch in the second latch module are configured to receive the fourth clock signal, and the second enable end of the second stage latch in the second latch module and the third enable end of the second stage latch in the second latch module are configured to receive the second clock signal.
In one embodiment, the latch control circuit comprises the first latch module, and the clock output circuit comprises two clock gating modules; the first clock gating module is used for gating the first clock signal to output a first clock gating signal and gating the third clock signal to output a third clock gating signal under the control of the first gating enable signal; the second clock gating module is used for gating the second clock signal to output a second clock gating signal and gating the fourth clock signal to output a fourth clock gating signal under the control of the second gating enable signal; the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
In one embodiment, the trigger level of the first latch control signal occurs at a low level of the first clock signal and/or a high level of the third clock signal; a trigger level of the second latch control signal occurs at a low level of the second clock signal and/or a high level of the fourth clock signal; the first clock gating module is used for copying the first clock signal when the first gating enable signal is high so as to enable the first clock gating signal to start to turn over, and outputting low level when the first gating enable signal is low so as to enable the first clock gating signal to stop turning over; the first clock gating module is further configured to copy the third clock signal when the first gating enable signal is high, so that the third clock gating signal starts to turn over, and output a high level when the first gating enable signal is low, so that the third clock gating signal stops turning over; the second clock gating module is used for copying the second clock signal when the second gating enable signal is high so as to enable the second clock gating signal to start to turn over, and outputting low level when the second gating enable signal is low so as to enable the second clock gating signal to stop turning over; the second clock gating module is further configured to copy the fourth clock signal when the second gating enable signal is high, so as to start to flip the fourth clock gating signal, and output a high level when the second gating enable signal is low, so as to stop the flip of the fourth clock gating signal.
In one embodiment, the clock gating module comprises a first nand gate, a second nand gate, a third nand gate and a fourth nand gate; a first input end of the first nand gate is used as a first signal input end of the clock gating module, a second input end of the first nand gate is used as a first gating enable end of the clock gating module, an output end of the first nand gate is connected with a first input end of the second nand gate, a second input end of the second nand gate is used for receiving high level, and an output end of the second nand gate is used as a first signal output end of the clock gating module; the first input end of the third nand gate is configured to receive a high level, the second input end of the third nand gate is used as the second signal input end of the clock gating module, the output end of the third nand gate is connected to the second input end of the fourth nand gate, the first input end of the fourth nand gate is used as the second gating enable end of the clock gating module, and the output end of the fourth nand gate is used as the second signal output end of the clock gating module.
In one embodiment, a first signal input terminal of the first clock gating module is configured to receive the first clock signal, a second signal input terminal of the first clock gating module is configured to receive the third clock signal, a first gate enable terminal and a second gate enable terminal of the first clock gating module are configured to receive the first gate enable signal, a first signal output terminal of the first clock gating module is configured to output the first clock gating signal, and a second signal output terminal of the first clock gating module is configured to output the third clock gating signal; a first signal input end of the second clock gating module is configured to receive the second clock signal, a second signal input end of the second clock gating module is configured to receive the fourth clock signal, a first gating enable end and a second gating enable end of the second clock gating module are configured to receive the second gating enable signal, a first signal output end of the second clock gating module is configured to output the second clock gating signal, and a second signal output end of the second clock gating module is configured to output the fourth clock gating signal.
In one embodiment, the latch control circuit comprises the second latch module, and the clock output circuit comprises two clock gating modules; the first clock gating module is used for gating the third clock signal to output a first clock gating signal and gating the first clock signal to output a third clock gating signal under the control of the third gating enable signal; the second clock gating module is used for gating the fourth clock signal to output a second clock gating signal and gating the second clock signal to output a fourth clock gating signal under the control of the fourth gating enable signal; the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
In one embodiment, the trigger level of the third latch control signal occurs at a high level of the first clock signal and/or a low level of the third clock signal; a trigger level of the fourth latch control signal occurs at a high level of the second clock signal and/or a low level of the fourth clock signal; the first clock gating module is used for copying the third clock signal when the third gating enable signal is high so as to enable the first clock gating signal to start to turn over, and outputting low level when the third gating enable signal is low so as to enable the first clock gating signal to stop turning over; the first clock gating module is further configured to copy the first clock signal when the third gating enable signal is high, so as to start the inversion of the third clock gating signal, and output a high level when the third gating enable signal is low, so as to stop the inversion of the third clock gating signal; the second clock gating module is configured to copy the fourth clock signal when the fourth gating enable signal is high, so as to start to flip the second clock gating signal, and output a low level when the fourth gating enable signal is low, so as to stop the flip of the second clock gating signal; the second clock gating module is further configured to copy the second clock signal when the fourth gating enable signal is high, so that the fourth clock gating signal starts to turn over, and output a high level when the fourth gating enable signal is low, so that the fourth clock gating signal stops turning over.
In one embodiment, the clock gating module comprises a first nand gate, a second nand gate, a third nand gate and a fourth nand gate; a first input end of the first nand gate is used as a first signal input end of the clock gating module, a second input end of the first nand gate is used as a first gating enable end of the clock gating module, an output end of the first nand gate is connected with a first input end of the second nand gate, a second input end of the second nand gate is used for receiving high level, and an output end of the second nand gate is used as a first signal output end of the clock gating module; the first input end of the third nand gate is configured to receive a high level, the second input end of the third nand gate is used as the second signal input end of the clock gating module, the output end of the third nand gate is connected to the second input end of the fourth nand gate, the first input end of the fourth nand gate is used as the second gating enable end of the clock gating module, and the output end of the fourth nand gate is used as the second signal output end of the clock gating module.
In one embodiment, the first signal input terminal of the first clock gating module is configured to receive the third clock signal, the second signal input terminal of the first clock gating module is configured to receive the first clock signal, the first and second gating enable terminals of the first clock gating module are configured to receive the third gating enable signal, the first signal output terminal of the first clock gating module is configured to output the first clock gating signal, and the second signal output terminal of the first clock gating module is configured to output the third clock gating signal; a first signal input end of the second clock gating module is configured to receive the fourth clock signal, a second signal input end of the second clock gating module is configured to receive the second clock signal, a first gating enable end and a second gating enable end of the second clock gating module are configured to receive the fourth gating enable signal, a first signal output end of the second clock gating module is configured to output the second clock gating signal, and a second signal output end of the second clock gating module is configured to output the fourth clock gating signal.
In one embodiment, the latch control circuit comprises the first latch module and the second latch module, and the clock output circuit comprises two first clock gating modules and two second clock gating modules; the first clock gating module is used for gating the first clock signal under the control of the first gating enable signal to output a first clock gating signal, or gating the third clock signal under the control of the third gating enable signal to output the first clock gating signal; the second first clock gating module is used for gating the second clock signal under the control of the second gating enable signal to output a second clock gating signal, or gating the fourth clock signal under the control of the fourth gating enable signal to output the second clock gating signal; the first second clock gating module is used for gating the third clock signal under the control of the first gating enable signal to output a third clock gating signal, or gating the first clock signal under the control of the third gating enable signal to output the third clock gating signal; the second clock gating module is configured to gate the fourth clock signal under the control of the second gating enable signal to output a fourth clock gating signal, or gate the second clock signal under the control of the fourth gating enable signal to output the fourth clock gating signal; the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
In one embodiment, the trigger level of the first latch control signal occurs at a low level of the first clock signal and/or a high level of the third clock signal; a trigger level of the second latch control signal occurs at a low level of the second clock signal and/or a high level of the fourth clock signal; a trigger level of the third latch control signal occurs at a high level of the first clock signal and/or a low level of the third clock signal; a trigger level of the fourth latch control signal occurs at a high level of the second clock signal and/or a low level of the fourth clock signal; the first clock gating module is used for copying the first clock signal when the first gating enable signal is high so as to enable the first clock gating signal to start to turn over, and outputting low level when the first gating enable signal is low so as to enable the first clock gating signal to stop turning over; the clock signal generating circuit is further configured to copy the third clock signal when the third gating enable signal is high, so as to start the first clock gating signal to be inverted, and output a high level when the third gating enable signal is low, so as to stop the first clock gating signal from being inverted; the second first clock gating module is used for copying the second clock signal when the second gating enable signal is high so as to enable the second clock gating signal to start to turn over, and outputting low level when the second gating enable signal is low so as to enable the second clock gating signal to stop turning over; the clock signal generator is further configured to copy the fourth clock signal when the fourth gating enable signal is high, so that the second clock gating signal starts to be inverted, and output a high level when the fourth gating enable signal is low, so that the second clock gating signal stops being inverted; the first second clock gating module is used for copying the third clock signal when the first gating enable signal is high so that the third clock gating signal starts to turn over, and outputting low level when the first gating enable signal is low so that the third clock gating signal stops turning over; the clock signal generating circuit is further configured to copy the first clock signal when the third gating enable signal is high, so that the third clock gating signal starts to turn over, and output a high level when the third gating enable signal is low, so that the third clock gating signal stops turning over; the second clock gating module is configured to copy the fourth clock signal to start outputting the second clock gating signal when the second gating enable signal is high, and output a low level to stop the second clock gating signal from being inverted when the second gating enable signal is low; and the clock signal generating unit is further configured to copy the second clock signal when the fourth gating enable signal is high, so that the fourth clock gating signal starts to flip, and output a high level when the fourth gating enable signal is low, so that the fourth clock gating signal stops flipping.
In one embodiment, the first clock gating module includes a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, and a second inverter, wherein a first input of the first nand gate is used as a first signal input of the first clock gating module, a second input of the first nand gate is used as a first gate enable of the first clock gating module, a first input of the second nand gate is used as a second signal input of the first clock gating module, a second input of the second nand gate is used as a second gate enable of the first clock gating module, an output of the first nand gate is connected to a first input of the third nand gate, an output of the second nand gate is connected to a second input of the third nand gate, and an output of the third nand gate is connected to a first input of the fourth nand gate, the second input end of the fourth nand gate is used for receiving high level, the output end of the fourth nand gate is connected with the input end of the second inverter, and the output end of the second inverter is used as the signal output end of the first clock gating module.
In one embodiment, a first signal input terminal of the first clock gating module is configured to receive the first clock signal, a second signal input terminal of the first clock gating module is configured to receive the third clock signal, a first gating enable terminal of the first clock gating module is configured to receive the first gating enable signal, a second gating enable terminal of the first clock gating module is configured to receive the third gating enable signal, and a signal output terminal of the first clock gating module is configured to output the first clock gating signal; a first signal input end of the second first clock gating module is configured to receive the second clock signal, a second signal input end of the second first clock gating module is configured to receive the fourth clock signal, a first gating enable end of the second first clock gating module is configured to receive the second gating enable signal, a second gating enable end of the second first clock gating module is configured to receive the fourth gating enable signal, and a signal output end of the second first clock gating module is configured to output the second clock gating signal.
In one embodiment, the second clock gating module includes a fifth nand gate, a sixth nand gate, a seventh nand gate, an eighth nand gate, a ninth nand gate, and a third inverter, a first input of the fifth nand gate is used as the first signal input of the second clock gating module, a second input of the fifth nand gate is used for receiving a high level, an output of the fifth nand gate is connected to the first input of the sixth nand gate, a second input of the sixth nand gate is used as the first gating enable terminal of the second clock gating module, a first input of the seventh nand gate is used as the second signal input of the second clock gating module, a second input of the seventh nand gate is used for receiving a high level, an output of the seventh nand gate is connected to the first input of the eighth nand gate, and a second input of the eighth nand gate is used as the second gating enable terminal of the second clock gating module, the output end of the sixth nand gate is connected with the first input end of the ninth nand gate, the output end of the eighth nand gate is connected with the second input end of the ninth nand gate, the output end of the ninth nand gate is connected with the input end of the third inverter, and the output end of the third inverter is used as the signal output end of the second clock gating module.
In one embodiment, the first signal input terminal of the first second clock gating module is configured to receive the third clock signal, the second signal input terminal of the first second clock gating module is configured to receive the first clock signal, the first gating enable terminal of the first second clock gating module is configured to receive the first gating enable signal, the second gating enable terminal of the first second clock gating module is configured to receive the third gating enable signal, and the signal output terminal of the first second clock gating module is configured to output the third clock gating signal; a first signal input end of the second clock gating module is configured to receive the fourth clock signal, a second signal input end of the second clock gating module is configured to receive the second clock signal, a first gating enable end of the second clock gating module is configured to receive the second gating enable signal, a second gating enable end of the second clock gating module is configured to receive the fourth gating enable signal, and a signal output end of the second clock gating module is configured to output the fourth clock gating signal.
In a second aspect, the present application provides the following technical solutions through an embodiment of the present application:
an electronic device, comprising: a controller; a memory; and a multi-phase clock signal gating circuit disposed between the controller and the memory, wherein the controller operates the memory through the multi-phase clock signal gating circuit; the gating circuit of the multi-phase clock signal comprises: the latch control circuit is used for latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal; and the clock output circuit is used for carrying out gating processing on the multiphase clock signals according to the at least one gating enabling signal so as to output the multiphase clock gating signals.
In one embodiment, the multi-phase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, a phase difference between adjacent clock signals is 90 °, the switching signals of the clock gating at least include a first switching signal and/or a second switching signal, and the latch control circuit at least includes one latch module or two latch modules; the first latch module is configured to perform latch processing on the first switch signal under control of a first latch control signal to generate a first gating enable signal, and perform latch processing on the first gating enable signal under control of a second latch control signal to generate a second gating enable signal, where the first latch control signal includes the first clock signal and/or the third clock signal, and the second latch control signal includes the second clock signal and/or the fourth clock signal; the second latch module is configured to latch the second switch signal under the control of a third latch control signal to generate a third gating enable signal, and latch the third gating enable signal under the control of a fourth latch control signal to generate a fourth gating enable signal, where the third latch control signal includes the first clock signal and/or the third clock signal, and the fourth latch control signal includes the second clock signal and/or the fourth clock signal; the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal, and the lag time or lead time is half of the period of the first clock signal; the trigger level of the second latch control signal lags or leads the trigger level of the fourth latch control signal by a time lag or lead of one-half of the period of the first clock signal.
In a third aspect, the present application provides the following technical solutions through an embodiment of the present application:
a method of gating a multi-phase clock signal, comprising: latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal;
and performing gating processing on the multi-phase clock signal according to the at least one gating enable signal to output a multi-phase clock gating signal.
In one embodiment, the multi-phase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, the phase difference between adjacent clock signals is 90 °, and the switching signals of the gated clock at least include a first switching signal and/or a second switching signal; the gating method comprises the following steps: performing latch processing on the first switch signal under the control of a first latch control signal to generate a first gate control enable signal, and performing latch processing on the first gate control enable signal under the control of a second latch control signal to generate a second gate control enable signal, wherein the first latch control signal comprises the first clock signal and/or the third clock signal, and the second latch control signal comprises the second clock signal and/or the fourth clock signal; or performing latch processing on the second switching signal under the control of a third latch control signal to generate a third gate control enable signal, and performing latch processing on the third gate control enable signal under the control of a fourth latch control signal to generate a fourth gate control enable signal, wherein the third latch control signal comprises the first clock signal and/or the third clock signal, and the fourth latch control signal comprises the second clock signal and/or the fourth clock signal; the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal by a time lag or lead of one-half of the period of the first clock signal; a trigger level of the second latch control signal lags or leads a trigger level of the fourth latch control signal by a time half of a period of the first clock signal.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
in the embodiment provided by the application, the latch control circuit performs latch processing on the switch signal of the gated clock through at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal, the clock output circuit performs gate control on the multi-phase clock signals by receiving at least one gated enable signal generated by the latch control circuit to output the multi-phase clock gated signals, when the switch signal of the gated clock changes from low to high, the gated enable signal changes from low to high at the trigger level of the latch control signal (i.e. at least one clock signal in the multi-phase clock signals) of the latch control circuit, at this time, the switch equivalent to the clock output circuit is closed, and the multi-phase clock gated signals start to be output; when the switch signal of the gating clock changes from high to low, the trigger level of the gating enable signal on the latch control signal (namely at least one clock signal in the multi-phase clock signals) of the latch control circuit changes from high to low, at the moment, the switch of the clock output circuit is equivalently switched off, the multi-phase clock gating signal stops outputting, and then gating of the multi-phase clock signals is realized, and the direct high-frequency turnover of the multi-phase clock signals is avoided, so that the relevant circuits which work by using the multi-phase frequency division clock generate turnover on the jumping edge of each clock, and unnecessary power consumption loss is caused.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gating circuit for multi-phase clock signals according to an embodiment of the present disclosure;
fig. 2 is a diagram illustrating a relationship between a gating enable signal and a switching signal of a gated clock according to an embodiment of the present application;
fig. 3 is a comparison graph of the effect of the gating enable signal and the switching signal of the gated clock on the gating signal of the multiphase clock provided in the embodiment of the present application;
fig. 4 is a schematic structural diagram of a gating circuit for multi-phase clock signals according to an embodiment of the present disclosure;
FIG. 5 is a timing chart of output multiphase clock gating signals when the second gating enable signal is formed with reference to the first gating enable signal and the first switch signal, respectively;
FIG. 6 is a comparison diagram of the first transition edge of the output multiphase clock gating signal when the relationship between the trigger level of the second latch control signal and the trigger level of the first latch signal is different;
FIG. 7 is a connection diagram of the electronic device of FIG. 4;
FIG. 8 is a timing diagram of the multiphase clock gating signals output from FIG. 7;
FIG. 9 is a schematic diagram of the effect of the multiphase clock gating signals generated in FIG. 7 before and after turn-on and turn-off when the first switching signal is turned off at different positions;
fig. 10 is a schematic structural diagram of another gate control circuit for multi-phase clock signals according to an embodiment of the present application;
FIG. 11 is a connection diagram of the electronic device of FIG. 10;
FIG. 12 is a timing diagram of the multiphase clock gating signals output from FIG. 11;
fig. 13 is a schematic structural diagram of another gate control circuit for multi-phase clock signals according to an embodiment of the present application;
FIG. 14 is a connection diagram of the electronic device of FIG. 13;
FIG. 15 is a timing diagram of the multiphase clock gating signals output from FIG. 14;
fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 17 is a flowchart of a gating method of multi-phase clock signals according to an embodiment of the present disclosure.
Detailed Description
The embodiment of the application provides a gating circuit and method for a multi-phase clock signal, and an electronic device, so that the technical problem that in the prior art, a four-phase frequency division clock always turns at a high frequency, so that a relevant circuit working by using the multi-phase frequency division clock turns at a transition edge of each clock, and unnecessary power consumption loss is caused is solved.
In order to solve the technical problems, the general idea of the embodiment of the application is as follows:
a gating circuit for a multi-phase clock signal, comprising: the latch control circuit is used for latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal; and the clock output circuit is used for carrying out gating processing on the multiphase clock signals according to the at least one gating enabling signal so as to output the multiphase clock gating signals.
In the embodiment provided by the application, the latch control circuit performs latch processing on the switch signal of the gated clock through at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal, the clock output circuit performs gate control on the multi-phase clock signals by receiving at least one gated enable signal generated by the latch control circuit to output the multi-phase clock gated signals, when the switch signal of the gated clock changes from low to high, the gated enable signal changes from low to high at the trigger level of the latch control signal (i.e. at least one clock signal in the multi-phase clock signals) of the latch control circuit, at this time, the switch equivalent to the clock output circuit is closed, and the multi-phase clock gated signals start to be output; when the switch signal of the gating clock changes from high to low, the trigger level of the gating enable signal on the latch control signal (namely at least one clock signal in the multi-phase clock signals) of the latch control circuit changes from high to low, at the moment, the switch of the clock output circuit is equivalently switched off, the multi-phase clock gating signal stops outputting, and then gating of the multi-phase clock signals is realized, and the direct high-frequency turnover of the multi-phase clock signals is avoided, so that the relevant circuits which work by using the multi-phase frequency division clock generate turnover on the jumping edge of each clock, and unnecessary power consumption loss is caused.
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
Example one
As shown in fig. 1, the present embodiment provides a gating circuit for multi-phase clock signals, comprising:
the latch control circuit 1 is configured to latch a switching signal EN of a gated clock according to at least one clock signal of the multi-phase clock signals, and generate at least one gated enable signal EN;
the clock output circuit 2 is configured to gate the multi-phase clock signal according to the at least one gate enable signal en to output a multi-phase clock gate control signal.
The gate control circuit for multi-phase clock signals is arranged between a clock generator (a device for generating multi-phase clock signals) and related circuits which need to work by using the clock signals generated by the clock generator.
The gating circuit for multiphase clock signals is suitable for two-phase clock signals, four-phase clock signals, eight-phase clock signals, and so on … … according to multiples of two, and generates a gating enable signal en for each group of clock signals in the multiphase clock signals having a differential relationship, and simultaneously gates the group of clock signals having the differential relationship by using the gating enable signal, for example:
when the gating circuit is used for gating the two-phase clock signal, the latch control circuit 1 generates a gating enable signal en, and the clock output circuit 2 simultaneously gates the two-phase clock signal having a differential relationship according to the gating enable signal en to output the two-phase clock gating signal.
When the gating circuit is used for gating four-phase clock signals, the latch control circuit 1 generates two gating enable signals en, the clock output circuit 2 simultaneously gates one group of clock signals with a differential relationship in the four-phase clock signals by using one gating enable signal en, and simultaneously gates the other group of clock signals with the differential relationship in the four-phase clock signals by using the other gating enable signal en to output the four-phase clock gating signals.
In the following embodiments, a four-phase clock signal gating circuit is described as an example.
In this embodiment, the clock gating switching signal EN is a signal externally used to control the gate control circuit to be "on" and "off", and indicates a state in which the gate control circuit is controlled to be "on" when the clock gating switching signal EN is "high", and indicates a state in which the gate control circuit is controlled to be "off" when the clock gating switching signal EN is "low".
The gate enable signal EN is a signal obtained by the latch control circuit 1 latching the switching signal EN of the gate clock under the control of the latch control signal, and is a signal actually used to control the "on" and "off" of the gate circuit inside the gate circuit.
The process of the above-mentioned latch process is described in detail here, and specifically includes the following two processes:
(1) the storage process is as follows: when the trigger level of the latch control signal arrives, the latch control circuit 1 is in an on state, the switch signal EN of the gate control clock is stored, and the gate control enable signal EN output by the latch control circuit 1 is consistent with the switch signal EN of the gate control clock;
(2) the locking process: when the trigger level of the latch control signal does not arrive, the latch control circuit 1 is in a "lock" state, the switch signal EN of the gate control clock is subjected to "lock" processing, the gate control enable signal EN output by the output end of the latch control circuit 1 maintains the level state output by the previous trigger level until the next trigger level arrives, and the state of the switch signal EN of the gate control clock is stored.
It should be noted here that, for the latch control circuit 1, the trigger level of the latch control signal has only two states of "high level" or "low level", and the trigger level of the latch control signal is provided by at least one of the latch control signal, i.e. the multi-phase clock signal, and since the multi-phase clock signal is not turned over continuously, the trigger level of the latch control signal appears intermittently, and correspondingly, the timing of the gate control enable signal EN jumping along with the switch signal EN of the gate control clock is also intermittent.
As shown in fig. 2, fig. 2 illustrates multi-phase clock signals including a first clock signal CK _00, a second clock signal CK _90, a third clock signal CK _180, and a fourth clock signal CK _270, wherein a phase difference between adjacent clock signals is 90 °, the first clock signal CK _00 and the third clock signal CK _180 are a pair of differential signals, the second clock signal CK _90 and the fourth clock signal CK _270 are a pair of differential signals, and further illustrates a transition process of a switching signal EN of a gated clock and a process of a gating enable signal EN following the transition. In the figure, the latch control signal is provided by the first clock signal CK _00, and the trigger level is at a high level, then the trigger level comes at a position corresponding to an odd numbered mark in fig. 2, the latch control circuit 1 performs the "storing" process at the position, and performs the "locking" process at a position corresponding to an even numbered mark in fig. 2, when the switching signal EN of the gate clock goes from low to high at a falling edge of a mark 3, the gate enable signal EN maintains a low level state because the trigger level "high" provided by the first clock signal CK _00 does not come at this time, and when a rising edge of a mark 5 corresponding position comes, the gate enable signal EN follows from low to high.
In summary, the gated enable signal EN obtained through the latch processing follows a transition of the clock-gated switch signal EN when the clock-gated switch signal EN transitions, but the gated enable signal EN does not immediately follow the transition, and the timing at which the gated enable signal EN follows the transition occurs when the trigger level of the latch control signal arrives.
In this embodiment, "gate control processing" refers to a process of turning on or off a multi-phase clock signal by using a gate control enable signal en as a switch signal for outputting the multi-phase clock gate control signal, and the "gate control processing" is specifically as follows:
when the gating enable signal en is high, the clock output circuit 2 is closed, the multi-phase clock gating signal starts to jump, and the multi-phase clock gating signal copies the multi-phase clock signal received by the input end, wherein the copying means that the multi-phase clock gating signal is consistent with the multi-phase clock signal;
when the gating enable signal en is low, the clock output circuit 2 is "off" and the multiphase clock gating signal stops jumping.
Because the timing of the gating enable signal EN following the transition occurs at the moment when the trigger level of the latch control signal arrives, when the gating enable signal EN is used for gating the multi-phase clock signal, the timing of the multi-phase clock gating signal starting to transition or stopping to transition can be generated when the trigger level of the multi-phase clock signal arrives, and therefore the problem that the switching signal EN of the gating clock is suddenly turned off or turned on when the trigger level of the latch control signal does not arrive and the multi-phase clock gating signal follows the sudden turn-off or turn-on to generate glitches can be avoided.
As shown in fig. 3, the second group of multiphase clock gating signals (respectively including the first clock gating signal CK00_ gate, the second clock gating signal CK90_ gate, the third clock gating signal CK180_ gate, and the fourth clock gating signal CK270_ gate) shows the state of the output multiphase clock gating signal, which is gated by the latch control circuit 1 after the latch control circuit 1 latches the switching signal EN of the gating clock when the trigger level of the latch control signal is the low level of the first clock signal CK _ 00. In this figure, even when the switching signal EN of the gate clock is abruptly turned off at the high level of reference numeral 11 (the high level of reference numeral 11 is not at the trigger level of the latch control signal), the multiphase clock gate signal can continue to maintain the current level state until the trigger level comes, which corresponds to reference numeral 12 in the first clock signal CK _00, and the output is stopped, although the switching signal EN of the gate clock is abruptly turned off during the level of reference numeral 11, the last level is not output until the trigger level comes, and the last level is identified by a dotted frame, belongs to a complete level, and no glitch is generated.
The first group of multiphase clock gating signals (respectively including the first clock gating signal CK00_ gate, the second clock gating signal CK90_ gate, the third clock gating signal CK180_ gate, and the fourth clock gating signal CK270_ gate) shows that the multiphase clock gating signals are directly gated by the clock gating switching signal EN, and when the clock gating switching signal EN is suddenly turned off (i.e., not at the trigger level of the latch control signal) during the level process with the reference number 11, the multiphase clock gating signals suddenly stop outputting the generated glitch, which is identified by the dashed box.
As an alternative embodiment, the switch signal EN of the gate clock includes a first switch signal EN _ EVEN and/or a second switch signal EN _ ODD, the latch control circuit 1 includes one latch module or two latch modules, as shown in fig. 4, fig. 4 illustrates a case where the switch signal EN of the gate clock includes the first switch signal EN _ EVEN, and the latch control circuit 1 includes the first latch module 10-1; as shown in fig. 10, fig. 10 illustrates a case where the clock gating switching signal EN includes the second switching signal EN _ ODD, and the latch control circuit 1 includes the second latch block 10-2; as shown in fig. 13, fig. 13 illustrates a case where the clock gating switch signal EN includes a first switch signal EN _ EVEN and a second switch signal EN _ ODD, and the latch control circuit 1 includes a first latch block 10-1 and a second latch block 10-2;
the first latch module 10-1 is configured to latch the first switch signal EN _ EVEN under the control of a first latch control signal CT1 to generate a first gating enable signal EN _0, and latch the first gating enable signal EN _0 under the control of a second latch control signal CT2 to generate a second gating enable signal EN _90, where the first latch control signal CT1 includes the first clock signal CK _00 and/or the third clock signal CK _180, and the second latch control signal CT2 includes the second clock signal CK _90 and/or the fourth clock signal CK _ 270;
the second latch module 10-2 is configured to latch the second switching signal EN _ ODD under the control of a third latch control signal CT3 to generate a third gating enable signal EN _180, and latch the third gating enable signal EN _180 under the control of a fourth latch control signal CT4 to generate a fourth gating enable signal EN _270, where the third latch control signal CT3 includes the first clock signal CK _00 and/or the third clock signal CK _180, and the fourth latch control signal CT4 includes the second clock signal CK _90 and/or the fourth clock signal CK _ 270;
the trigger level of the first latch control signal CT1 lags or leads the trigger level of the third latch control signal CT3 by a half of the period of the first clock signal CK _ 00; the trigger level of the second latch control signal CT2 lags or leads the trigger level of the fourth latch control signal CT4 by a half of the period of the first clock signal CK _ 00.
The clock output circuit 2 in the gate control circuit according to the present embodiment has the following three schemes:
when the latch control circuit 1 includes only the first latch block 10-1, the clock output circuit 2 is configured to gate the four-phase clock signal under the control of the first clock gating signal CK00_ gate and the second clock gating signal CK90_ gate generated by the first latch block 10-1 to output the four-phase clock gating signal.
Second, when the latch control circuit 1 includes only the second latch block 10-2, the clock output circuit 2 is configured to gate the four-phase clock signal under the control of the third clock gating signal CK180_ gate and the fourth clock gating signal CK270_ gate generated by the second latch block 10-2, so as to output the four-phase clock gating signal.
(III) when the latch control circuit 1 comprises a first latch block 10-1 and a second latch block 10-2, the clock output circuit 2 is configured to gate the four-phase clock signal under the control of the first clock gating signal CK00_ gate and the second clock gating signal CK90_ gate generated by the first latch block 10-1 to output the four-phase clock gating signal; or gate the four-phase clock signal under the control of the third clock gating signal CK180_ gate and the fourth clock gating signal CK270_ gate generated by the second latch module 10-2 to output the four-phase clock gating signal.
In this embodiment, the first gating enable signal EN _0 and the second gating enable signal EN _90 generated by the first latch module 10-1 gate the four-phase clock signal, so as to avoid the glitch problem that the four-phase clock gating signal is suddenly turned off or on when the trigger level of the latch control signal of the first latch module 10-1 is not reached, resulting in the sudden turn-off or turn-on of the four-phase clock gating signal. The third gating enable signal EN _180 and the fourth gating enable signal EN _270 generated by the second latch module 10-2 gate the four-phase clock signal, so that the problem of glitch caused by the fact that the four-phase clock gating signal is suddenly turned off or on when the trigger level of the latch control signal of the second latch module 10-2 is not reached is solved.
In this embodiment, the trigger levels of the latch control signals of the first latch module 10-1 and the second latch module 10-2 are distinguished by setting the trigger level of the first latch control signal CT1 and the trigger level of the third latch control signal CT3 and setting the trigger level of the second latch control signal CT2 and the trigger level of the fourth latch control signal CT4, and the trigger levels of the two are just complementary to each other, so that the trigger levels of the latch control signals are both high or low, and when the switch signal EN of the clock gate is suddenly turned off or on when the trigger level of the latch control signal is not reached, glitches of the output four-phase clock gate signal can be avoided.
In this embodiment, the first clock signal CK _00 and the third clock signal CK _180 are differential signals, the low level of the first clock signal CK _00 corresponds to the high level of the third clock signal CK _180, and the high level of the first clock signal CK _00 corresponds to the low level of the third clock signal CK _180, so that for the first latch module 10-1, the trigger level of the first latch control signal CT1 is the low level of the first clock signal CK _00, that is, the trigger level corresponds to the high level of the third clock signal CK _ 180. Therefore, in this embodiment, the trigger level of the first latch control signal CT1 and the trigger level of the third latch control signal CT3 include the following cases:
when the first latch control signal CT1 is the first clock signal CK _00 and the third latch control signal CT3 is the first clock signal CK _00, if the trigger level of the first latch control signal CT1 appears at the low level of the first clock signal CK _00, the trigger level of the third latch control signal CT3 appears at the high level of the first clock signal CK _ 00; if the toggle level of the first latch control signal CT1 appears at the high level of the first clock signal CK _00, the toggle level of the third latch control signal CT3 appears at the low level of the first clock signal CK _ 00;
when the first latch control signal CT1 is the third clock signal CK _180 and the third latch control signal CT3 is the third clock signal CK _180, if the toggle level of the first latch control signal CT1 appears at the low level of the third clock signal CK _180, the toggle level of the third latch control signal CT3 appears at the high level of the third clock signal CK _ 180; if the toggle level of the first latch control signal CT1 appears at the high level of the third clock signal CK _180, the toggle level of the third latch control signal CT3 appears at the low level of the third clock signal CK _ 180;
when the first latch control signal CT1 is the first clock signal CK _00 and the third latch control signal CT3 is the third clock signal CK _180, if the toggle level of the first latch control signal CT1 appears at the low level of the first clock signal CK _00, the toggle level of the third latch control signal CT3 appears at the low level of the third clock signal CK _ 180; if the toggle level of the first latch control signal CT1 appears at the high level of the first clock signal CK _00, the toggle level of the third latch control signal CT3 appears at the high level of the third clock signal CK _ 180;
when the first latch control signal CT1 is the third clock signal CK _180 and the third latch control signal CT3 is the first clock signal CK _00, if the toggle level of the first latch control signal CT1 appears at the low level of the third clock signal CK _180, the toggle level of the third latch control signal CT3 appears at the low level of the first clock signal CK _ 00; if the trigger level of the first latch control signal CT1 appears at the high level of the third clock signal CK _180, the trigger level of the third latch control signal CT3 appears at the high level of the first clock signal CK _ 00;
when the first latch control signal CT1 is the first clock signal CK _00 and the third clock signal CK _180, and the third latch control signal CT3 is the first clock signal CK _00 and the third clock signal CK _180, if the toggle level of the first latch control signal CT1 occurs at the high level of the first clock signal CK _00 and the low level of the third clock signal CK _180, the toggle level of the third latch control signal CT3 occurs at the low level of the first clock signal CK _00 and the low level of the third clock signal CK _ 180; if the toggle level of the first latch control signal CT1 occurs at the low level of the first clock signal CK _00 and the high level of the third clock signal CK _180, the toggle level of the third latch control signal CT3 occurs at the high level of the first clock signal CK _00 and the low level of the third clock signal CK _ 180.
Similarly, the trigger level of the second latch control signal CT2 and the trigger level of the fourth latch control signal CT4 are similar to the trigger level of the first latch control signal CT1 and the trigger level of the third latch control signal CT3, and are not described herein again.
In this embodiment, the second gating enable signal en _90 is generated after latching the first gating enable signal en _0, and therefore, the second gating enable signal en _90 transitions following the first gating enable signal en _0 when the trigger level of the second control signal arrives. This technical means can ensure that the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate gated by the second gating enable signal EN _90 do not appear earlier than the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate gated by the first gating enable signal EN _0, as shown in fig. 5, which illustrates a case where the second gating enable signal EN _90 is generated by directly performing latch processing on the first switch signal EN _ EVEN, i.e., a case where the second gating enable signal EN _90 is earlier than the first gating enable signal EN _0, in which the second gating enable signal EN _90 gates the second clock signal CK _90, outputs the second clock gating signal CK90_ gate, and performs processing on the fourth clock signal CK _270, and outputs the fourth clock gating signal CK270_ gate; the first gating enable signal en _0 gates the first clock signal CK _00 to output a first clock gating signal CK00_ gate, gates the third clock signal CK _180 to output a third clock gating signal CK180_ gate. As can be seen from the dotted line portion, the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate occur earlier than the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate gated by the first gating enable signal en _ 0.
Similarly, since the fourth gating enable signal en _270 is generated after the third gating enable signal en _180 is latched, the technical means can also ensure that the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate generated by gating the fourth gating enable signal en _270 do not appear earlier than the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate gated by the third gating enable signal en _ 180.
As an alternative embodiment, the trigger level of the second latch control signal CT2 lags behind the trigger level of the first latch control signal CT1 by a quarter of the period of the first clock signal CK _ 00;
the trigger level of the fourth latch control signal CT4 lags behind the trigger level of the third latch control signal CT3 by a quarter of the period of the first clock signal CK _ 00.
Specifically, the trigger level of the second latch control signal CT2 and the trigger level of the first latch control signal CT1 include the following situations:
when the first latch control signal CT1 is the first clock signal CK _00 and the second latch control signal CT2 is the second clock signal CK _90, if the toggle level of the first latch control signal CT1 appears at the low level of the first clock signal CK _00, the toggle level of the second latch control signal CT2 appears at the low level of the second clock signal CK _ 90; if the toggle level of the first latch control signal CT1 appears at the high level of the first clock signal CK _00, the toggle level of the second latch control signal CT2 appears at the high level of the second clock signal CK _ 90;
when the first latch control signal CT1 is the third clock signal CK _180 and the second latch control signal CT2 is the fourth clock signal CK _270, if the toggle level of the first latch control signal CT1 appears at the low level of the third clock signal CK _180, the toggle level of the second latch control signal CT2 appears at the low level of the fourth clock signal CK _ 270; if the trigger level of the first latch control signal CT1 appears at the high level of the third clock signal CK _180, the trigger level of the second latch control signal CT2 appears at the high level of the fourth clock signal CK _ 270;
when the first latch control signal CT1 is the first clock signal CK _00 and the second latch control signal CT2 is the fourth clock signal CK _270, if the toggle level of the first latch control signal CT1 appears at the low level of the first clock signal CK _00, the toggle level of the second latch control signal CT2 appears at the high level of the fourth clock signal CK _ 270; if the trigger level of the first latch control signal CT1 appears at the high level of the first clock signal CK _00, the trigger level of the second latch control signal CT2 appears at the low level of the fourth clock signal CK _ 270;
when the first latch control signal CT1 is the third clock signal CK _180 and the second latch control signal CT2 is the second clock signal CK _90, if the toggle level of the first latch control signal CT1 appears at the low level of the third clock signal CK _180, the toggle level of the second latch control signal CT2 appears at the high level of the second clock signal CK _ 90; if the trigger level of the first latch control signal CT1 appears at the high level of the third clock signal CK _180, the trigger level of the second latch control signal CT2 appears at the low level of the fourth clock signal CK _ 90;
when the first latch control signal CT1 is the first clock signal CK _00 and the third clock signal CK _180, and the second latch control signal CT2 is the second clock signal CK _90 and the fourth clock signal CK _270, if the trigger level of the first latch control signal CT1 appears at the low level of the first clock signal CK _00 and the high level of the third clock signal CK _180, the trigger level of the second latch control signal CT2 appears at the low level of the second clock signal CK _90 and the high level of the fourth clock signal CK _270, which is illustrated in fig. 7 and 8; if the toggle level of the first latch control signal CT1 occurs at the high level of the first clock signal CK _00 and the low level of the third clock signal CK _180, the toggle level of the second latch control signal CT2 occurs at the high level of the second clock signal CK _90 and the low level of the fourth clock signal CK _ 270.
Similarly, the trigger level of the fourth latch control signal CT4 and the trigger level of the third latch control signal CT3 and the trigger level of the second latch control signal CT2 and the trigger level of the first latch control signal CT1 are similar, and are not described herein again.
In the present embodiment, by setting the relationship between the trigger level of the second latch control signal CT2 and the trigger level of the first latch control signal CT1 such that the trigger level of the second latch control signal CT2 is the low level of the second clock signal CK _90 when the trigger level of the first latch control signal CT1 is the low level of the first clock signal CK _00 and the trigger level of the second latch control signal CT2 is the high level of the second clock signal CK _90 when the trigger level of the first latch control signal CT1 is the high level of the first clock signal CK _00, the setting enables the first transition edge of the clock gating signal controlled to be output by the second gating enable signal en _90 to lag behind the first transition edge of the clock gating signal controlled to be output by the first gating enable signal en _0 on the basis that the second gating enable signal en _90 does not occur earlier than the first gating enable signal en _0, and the lag time is one quarter of the first clock signal CK _ 00.
If the trigger level of the second latch control signal CT2 is earlier than the trigger level of the first latch control signal CT1 by a quarter of the period of the first clock signal CK _00, the trigger level of the second latch control signal CT2 is the high level of the second clock signal CK _90 when the trigger level of the first latch control signal CT1 is the low level of the first clock signal CK _ 00; when the trigger level of the first latch control signal CT1 is the high level of the first clock signal CK _00, the trigger level of the second latch control signal CT2 is the low level of the second clock signal CK _90, which causes the first transition edge of the clock gating signal controlled to be output by the second gating enable signal en _90 to occur earlier than the first transition edge of the clock gating signal controlled to be output by the first gating enable signal en _0, so that the first transition edges of the phases in the output four-phase clock gating signal are out of order.
As shown in fig. 6, in the figure, the second gating enable signal en _90 gates the second clock signal CK _90 to output the second clock gating signal CK90_ gate, and gates the fourth clock signal CK _270 to output the fourth clock gating signal CK270_ gate; the first gating enable signal en _0 gates the first clock signal CK _00 to output a first clock gating signal CK00_ gate, and gates the third clock signal CK _180 to output a third clock gating signal CK180_ gate, where the dotted lines indicate the positions of the first transition edges of the clock gating signals.
The first set of the first gating enable signal en _0, the second gating enable signal en _90, and the four-phase clock gating signal illustrate the four-phase clock gating signal output when the trigger level of the first latch control signal CT1 is the low level of the first clock signal CK _00, the trigger level of the second latch control signal CT2 is the high level of the second clock signal CK _90, i.e., the trigger level of the second latch control signal CT2 is earlier than the trigger level of the first latch control signal CT1 by a time equal to one-fourth of the period of the first clock signal CK _ 00. As can be seen, the first transition edges of the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate occur at the rising edge of the level labeled 5 in the first clock signal CK _00, and the first transition edges of the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate occur at the falling edge of the level labeled 4 in the first clock signal CK _00, so that the relationship of the first rising edge of each phase in the four-phase clock gating signals is confused.
The second group of the first gating enable signal en _0, the second gating enable signal en _90, and the four-phase clock gating signal illustrate the four-phase clock gating signal output when the trigger level of the first latch control signal CT1 is the low level of the first clock signal CK _00, the trigger level of the second latch control signal CT2 is the low level of the second clock signal CK _90, i.e., the trigger level of the second latch control signal CT2 lags behind the trigger level of the first latch control signal CT1 by a quarter of the period of the first clock signal CK _ 00. As can be seen, the first transition edges of the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate occur at the rising edge of the level labeled 5 in the first clock signal CK _00, while the first transition edges of the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate occur in the middle of the level labeled 5 in the first clock signal CK _00, and the first rising edges of the phases in the four-phase clock gating signal are sequentially discharged.
Similarly, the first transition edge of the clock gating signal controlled to be output by the fourth gating enable signal en _270 can occur later than the first transition edge of the clock gating signal controlled to be output by the third gating enable signal en _ 180.
As an alternative embodiment, the latch module 10 (including either of the first latch module 10-1 and the second latch module 10-2) includes two stages of latches, a first stage latch LAT1 and a second stage latch LAT2, respectively, and the first stage latch LAT1 and the second stage latch LAT2 are cascaded;
as shown in fig. 4 and 13, the first stage latch LAT1 in the first latch module 10-1 is configured to latch the first switch signal EN _ EVEN under the control of the first latch control signal CT1, and generate the first gating enable signal EN _ 0;
as shown in fig. 4 and 13, the second stage latch LAT2 of the first latch block 10-1 is configured to latch the first gating enable signal en _0 under the control of the second latch control signal CT2, and generate the second gating enable signal en _ 90;
as shown in fig. 10 and 13, the first stage latch LAT1 of the second latch module 10-2 is configured to latch the second switching signal EN _ ODD under the control of the third latch control signal CT3, so as to generate the third gating enable signal EN _ 180;
as shown in fig. 10 and 13, the second stage latch LAT2 of the second latch module 10-2 is used for latching the third gating enable signal en _180 under the control of the fourth latch control signal CT4, and generating the fourth gating enable signal en _ 270.
In this embodiment, specifically, the first-stage latch LAT1 and the second-stage latch LAT2 in the first latch block 10-1 are cascaded by two stages of latches, so that the second-stage latch LAT2 performs latch processing with reference to the first gating enable signal en _0 to generate the second gating enable signal en _90, the first-stage latch LAT1 and the second-stage latch LAT2 in the second latch block 10-2 are cascaded, and the second-stage latch LAT2 performs latch processing with reference to the third gating enable signal en _180 to generate the fourth gating enable signal en _ 270.
As an alternative embodiment, as shown in fig. 7, 11 and 14, the latch (any one of the first stage latch LAT1 and the second stage latch LAT 2) includes a first tri-state not gate 11, a second tri-state not gate 12 and a first inverter 13;
the input end of the first tri-state not gate 11 is used as the input end I1 of the latch, the output end of the first tri-state not gate 11 is connected with the output end of the second tri-state not gate 12 and the input end of the first inverter 13, and the output end of the first inverter 13 is connected with the input end of the second tri-state not gate 12 and is used as the output end O1 of the latch;
the low-level enable terminal of the first tri-state not gate 11 serves as the first enable terminal P11 of the latch, the high-level enable terminal of the first tri-state not gate 11 serves as the second enable terminal P12 of the latch, the low-level enable terminal of the second tri-state not gate 12 serves as the third enable terminal P13 of the latch, and the high-level enable terminal of the second tri-state not gate 12 serves as the fourth enable terminal P14 of the latch.
It should be noted that, to implement the latch function, the trigger level of the enable terminal of the first tri-state not gate 11 should lag behind or lead the trigger level of the enable terminal of the second tri-state not gate 12, and the lag time or lead time should be one half of the first clock signal CK _ 00.
The latch provided by the embodiment comprises two tri-state NOT gates, wherein each of the two tri-state NOT gates is provided with a low-level enable terminal and a high-level enable terminal.
It should be noted that, on the basis of this embodiment, a person skilled in the art may modify the two tri-state not gates to have only one enable terminal, or one of the two tri-state not gates has two enable terminals, and the other one has one enable terminal, as long as it is ensured that the trigger level of the enable terminal of the first tri-state not gate 11 should lag behind or lead the trigger level of the enable terminal of the second tri-state not gate 12, and the lag behind or lead time should be one half of the first clock signal CK _ 00.
For example: the first tri-state not gate 11 only has a low level enable terminal, and the second tri-state not gate 12 only has a low level enable terminal; the first tri-state not gate 11 only has a low level enable terminal, and the second tri-state not gate 12 only has a high level enable terminal; the first tri-state not gate 11 only has a high-low level enable terminal and a low level enable terminal, and the second tri-state not gate 12 only has a high level enable terminal; the first tri-state not gate 11 has only a high-low level enable terminal and a low level enable terminal, and the second tri-state not gate 12 has only a high level enable terminal.
As an alternative embodiment, as shown in fig. 7 and 14, the input terminal I1 of the first stage latch LAT1 of the first latch module 10-1 is used for receiving the first switching signal EN _ EVEN, the output O1 of the first stage latch LAT1 in the first latch block 10-1 is used to output the first gating enable signal en _0, the first enable terminal P11 of the first stage latch LAT1 in the first latch block 10-1 and the fourth enable terminal P14 of the first stage latch LAT1 in the first latch block 10-1 are used for receiving the first clock signal CK _00, the second enable terminal P12 of the first stage latch LAT1 in the first latch module 10-1 and the third enable terminal P13 of the first stage latch LAT1 in the first latch module 10-1 are used for receiving the third clock signal CK _ 180;
as shown in fig. 7 and 14, the input terminal I1 of the second-stage latch LAT2 in the first latch module 10-1 is configured to receive the first gating enable signal en _0, the output terminal O1 of the second-stage latch LAT2 in the first latch module 10-1 is configured to output the second gating enable signal en _90, the first enable terminal P11 of the second-stage latch LAT2 in the first latch module 10-1 and the fourth enable terminal P14 of the second-stage latch LAT2 in the first latch module 10-1 are configured to receive the second clock signal CK _90, the second enable terminal P12 of the second-stage latch LAT2 in the first latch module 10-1 and the third enable terminal P13 of the second-stage latch LAT2 in the first latch module 10-1 are configured to receive the fourth clock signal CK _ 270;
as shown in fig. 11 and 14, the input terminal I1 of the first stage latch LAT1 in the second latch module 10-2 is configured to receive the second switch signal EN _ ODD, the output terminal O1 of the first stage latch LAT1 in the second latch module 10-2 is configured to output the third gating enable signal EN _180, the first enable terminal P11 of the first stage latch LAT1 in the second latch module 10-2 and the fourth enable terminal P14 of the first stage latch LAT1 in the second latch module 10-2 are configured to receive the third clock signal CK _180, the second enable terminal P12 of the first stage latch LAT1 in the second latch module 10-2 and the third enable terminal P13 of the first stage latch LAT1 in the second latch module 10-2 are configured to receive the first clock signal CK _ 00;
as shown in fig. 11 and 14, the input terminal I1 of the second stage latch LAT2 in the second latch module 10-2 is used for receiving the third gating enable signal en _180, the output terminal O1 of the second stage latch LAT2 in the second latch module 10-2 is used for outputting the fourth gating enable signal en _270, the first enable terminal P11 of the second stage latch LAT2 in the second latch module 10-2 and the fourth enable terminal P14 of the second stage latch LAT2 in the second latch module 10-2 are used for receiving the fourth clock signal CK _270, and the second enable terminal P12 of the second stage latch LAT2 in the second latch module 10-2 and the third enable terminal P13 of the second stage latch LAT2 in the second latch module 10-2 are used for receiving the second clock signal CK _ 90.
It should be noted that, in this embodiment, each stage of latches is connected to the enable terminals through two types of clock signals, and therefore, the first latch control signal CT1 includes the first clock signal CK _00 and the third clock signal CK _180, the second latch control signal CT2 includes the second clock signal CK _90 and the fourth clock signal CK _270, the third latch control signal CT3 includes the first clock signal CK _00 and the third clock signal CK _180, and the fourth latch control signal CT4 includes the second clock signal CK _90 and the fourth clock signal CK _ 270.
Among the four enable terminals included in the latch LAT of each stage in this embodiment, the first enable terminal P11 and the third enable terminal P13 are active low, and the second enable terminal P12 and the fourth enable terminal P14 are active high, so that the trigger level of the first latch control signal CT1 occurs at the low level of the first clock signal CK _00 and the high level of the third clock signal CK _180, the trigger level of the second latch control signal CT2 occurs at the low level of the second clock signal CK _90 and the high level of the fourth clock signal CK _270, the trigger level of the third latch control signal CT3 occurs at the high level of the first clock signal CK _00 and the low level of the third clock signal CK _180, and the trigger level of the fourth latch control signal CT4 occurs at the high level of the second clock signal CK _90 and the low level of the fourth clock signal CK _ 270.
In this embodiment, the first clock signal CK _00, the second clock signal CK _90, the third clock signal CK _180, and the fourth clock signal CK _270 in each latch module are all connected to two enable terminals at the same time, the load and the transmission path of the clock are completely consistent, the matching is good, and one of the two enable terminals is active at a high level and active at a low level, so that the whole latch module exhibits high symmetry.
It should be noted that, on the basis of this embodiment, a person skilled in the art may modify the two tri-state not gates to have only one enable terminal, or one of the two tri-state not gates has two enable terminals, and the other one has one enable terminal. In order to ensure that the two deformed tri-state not gates can realize the latch function, the trigger level of the enable terminal of the first tri-state not gate 11 should lag behind or lead the trigger level of the enable terminal of the second tri-state not gate 12, and the lag behind or lead time should be half of the first clock signal CK _00, so the latch control signal received by each enable terminal needs to be adjusted accordingly.
For example: in this case, in the first stage latch LAT1 of the first latch module 10-1 in this embodiment, the low level enable terminal of the first tristate not gate 11 is used for receiving the first clock signal CK _00, and the low level enable terminal of the second tristate not gate 12 is used for receiving the third clock signal CK _ 180;
a first tri-state not gate 11 in the latch is adjusted to have only a high level enable end, and a second tri-state not gate 12 has only a high level enable end, at this time, in the first stage latch LAT1 of the first latch module 10-1 in this embodiment, the high level enable end of the first tri-state not gate 11 is used for receiving the third clock signal CK _180, and the low level enable end of the second tri-state not gate 12 is used for receiving the first clock signal CK _ 00;
in the first stage latch LAT1 of the first latch module 10-1 in this embodiment, the low level enable terminal of the first tristate not gate 11 is used for receiving the first clock signal CK _00, and the high level enable terminal of the second tristate not gate 12 is used for receiving the first clock signal CK _ 00.
In the first stage latch LAT1 of the first latch module 10-1 in this embodiment, the low level enable terminal of the first tristate not gate 11 is used for receiving the first clock signal CK _00, the high level enable terminal of the first tristate not gate 11 is used for receiving the third clock signal CK _180, and the high level enable terminal of the second tristate not gate 12 is used for receiving the first clock signal CK _ 00.
Other variations and modifications are similar and will not be described here.
As an alternative embodiment, as shown in fig. 4, the latch control circuit 1 includes the first latch module 10-1, and the clock output circuit 2 includes two clock gating modules, namely, a first clock gating module 20-1 and a second clock gating module 20-2;
the first clock gating module 20-1 is configured to gate the first clock signal CK _00 to output a first clock gating signal CK00_ gate and gate the third clock signal CK _180 to output a third clock gating signal CK180_ gate under the control of the first gating enable signal en _ 0;
the second clock gating module 20-2 is configured to gate the second clock signal CK _90 to output a second clock gating signal CK90_ gate and gate the fourth clock signal CK _270 to output a fourth clock gating signal CK270_ gate under the control of the second gating enable signal en _ 90;
the phase difference between adjacent ones of the first, second, third, and fourth clock gating signals CK00_ gate, CK90_ gate, CK180_ gate, and CK270_ gate is 90 °.
In this embodiment, the first clock signal CK _00 and the third clock signal CK _180 are gated by the first gating enable signal en _0 at the same time, and the second clock signal CK _90 and the fourth clock signal CK _270 are gated by the second gating enable signal en _90 at the same time, when the first gating enable signal en _0 and the second gating enable signal en _90 are high, the first clock gating signal CK00_ gate replicates the first clock signal CK _00, the second clock gating signal CK90_ gate replicates the second clock signal CK _90, the third clock gating signal CK180_ gate replicates the third clock signal CK _180, the fourth clock gating signal 270_ gate replicates the fourth clock signal CK _270, and since the phase difference between adjacent signals in the four-phase clock signals is 90 °, the four-phase clock gating signals obtained by one-to-one copying can still maintain the phase relationship, meanwhile, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate can still maintain a differential relationship, and the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate can still maintain a differential relationship.
In the prior art, in the gating process of the four-phase clock gating signal, the clock signal of each phase of the four-phase clock signal needs to be controlled separately by a separate gating enable signal en. In the embodiment, a four-phase clock gating signal with unchanged phase relationship can be obtained by adopting a scheme that one gating enable signal en controls two clock signals at the same time, and the area of the whole gating circuit can be greatly reduced. Meanwhile, two clock signals are simultaneously controlled through one gating enable signal en, the simultaneous opening and closing of the differential signals can be realized, and the symmetry of the differential signals is strictly kept.
As an alternative embodiment, as shown in fig. 7 and 8, the trigger level of the first latch control signal CT1 occurs at the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _ 180; the trigger level of the second latch control signal CT2 occurs at a low level of the second clock signal CK _90 and/or a high level of the fourth clock signal CK _ 270;
the first clock gating module 20-1 is configured to copy the first clock signal CK _00 to start the first clock gating signal CK00_ gate to turn over when the first gating enable signal en _0 is high, and output a low level to stop the first clock gating signal CK00_ gate from turning over when the first gating enable signal en _0 is low;
the first clock gating module 20-1 is further configured to copy the third clock signal CK _180 when the first gating enable signal en _0 is high, so as to start the inversion of the third clock gating signal CK180_ gate, and output a high level when the first gating enable signal en _0 is low, so as to stop the inversion of the third clock gating signal CK180_ gate;
the second clock gating module 20-2 is configured to copy the second clock gating signal CK _90 to start the second clock gating signal CK90_ gate when the second gating enable signal en _90 is high, and output a low level to stop the second clock gating signal CK90_ gate when the second gating enable signal en _90 is low;
the second clock gating module 20-2 is further configured to copy the fourth clock signal CK _270 when the second gating enable signal en _90 is high, so as to start the fourth clock gating signal CK270_ gate to turn over, and output a high level when the second gating enable signal en _90 is low, so as to stop the fourth clock gating signal CK270_ gate from turning over.
It should be noted that the four-phase clock gating signals generated by the gating circuit are required to have no change in phase relationship among the clock gating signals, that is, the phase difference between the clock gating signals before the adjacent clock gating signals is 90 °, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate are differential signals, the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate are differential signals, and the clock gating signals of the respective phases are also required to have no glitch before and after the gating circuit is turned on and off, and the first rising edges of the respective phases can be sequentially released.
First, the present embodiment can avoid the glitches before and after the four-phase clock gating signal is turned on and off, and the case that the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate are before and after the clock gating signal is turned off is described with reference to fig. 9, which is specifically as follows:
it should be noted that, in the two groups of first gating enable signals en _0 illustrated in fig. 9, the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _180 are both the trigger level of the first latch control signal CT 1.
(1) As shown in fig. 9, the first group of the first switch signal EN _ EVEN, the first gate enable signal EN _0, the first clock gating signal CK00_ gate, and the third clock gating signal CK180_ gate in fig. 9 show the case where the first gate enable signal EN _0, the first clock gating signal CK00_ gate, and the third clock gating signal CK180_ gate are turned off when the first switch signal EN _ EVEN is turned off in the middle of the level denoted by reference numeral 12 (the position corresponding to the trigger level of the first latch control signal CT 1).
When the first switch signal EN _ EVEN is turned off at a position corresponding to the low level of the first clock signal CK _00, the first gate enable signal EN _0 immediately follows the change from high to low, and then the first clock gate signal CK00_ gate also immediately stops being output here, since the first clock signal CK _00 copied by the first clock gate signal CK00_ gate before being turned off is a low-level signal, and after being turned off, the first gate enable signal EN _0 also outputs a low-level signal in this scheme, and thus no glitch is generated. For the third clock gating signal CK180_ gate, the third clock gating signal CK180_ gate also stops being output immediately here, and no glitch is generated because the third clock gating signal CK180_ gate replicated by the third clock gating signal CK180_ gate before being turned off is a high-level signal, and the third clock gating signal CK180_ gate also outputs a high-level signal in the present scheme after being turned off.
(2) As shown in fig. 9, the second group of the first switching signal EN _ EVEN, the first gate enable signal EN _0, the first clock gating signal CK00_ gate, and the third clock gating signal CK180_ gate in fig. 9 show the case where the first gate enable signal EN _0, the first clock gating signal CK00_ gate, and the third clock gating signal CK180_ gate are turned off when the first switching signal EN _ EVEN is turned off in the middle of the level denoted by 11 (not at the position corresponding to the trigger level of the first latch control signal CT 1).
When the first switch signal EN _ EVEN is turned off at a position corresponding to the high level of the first clock signal CK _00, the first gate enable signal EN _0 does not immediately follow the change, but follows the change from high to low when the next low level of the first clock signal CK _00 comes, and the first clock gate signal CK00_ gate does not immediately stop being output at this point, and similarly stops being output when the next low level of the first clock signal CK _00 comes. The third clock gating signal CK180_ gate does not stop outputting immediately here, and similarly stops outputting when the next low level of the first clock signal CK _00 arrives. Therefore, if the clock gating switching signal EN is turned off at a position corresponding to the high level of the first clock signal CK _00, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate are not immediately turned off, so that a complete clock can be output without glitches.
Similarly, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate in this embodiment do not generate glitches before and after being turned on, and the analysis process is similar and will not be described herein again. Neither glitch exists in the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate in this embodiment.
Therefore, the embodiment can avoid the glitch problem caused by the fact that the four-phase clock gating signal is suddenly turned off or on when the trigger level of the first latch control signal CT1 or the second latch signal is not reached, wherein the first switch signal EN _ EVEN is suddenly turned off or on when the trigger level of the first latch control signal CT1 or the second latch signal is not reached; the glitch problem that the four-phase clock gating signal is suddenly turned off or on when the trigger level of the first latch control signal CT1 or the second latch control signal CT2 is reached, which is caused by the fact that the first switch signal EN _ EVEN is suddenly turned off or on, can also be avoided.
Next, in this embodiment, the first rising edge of each phase can be sequentially released, specifically as follows:
(1) when the first clock signal CK _00 and the third clock signal CK _180 are simultaneously turned on or off by the first gating enable signal en _0, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate start to be output at the same position, and due to the differential relationship between the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate, a first transition edge of the first clock gating signal CK00_ gate and a first transition edge of the third clock gating signal CK180_ gate will occur simultaneously, and one is a rising edge and one is a falling edge;
in the present embodiment, as shown in fig. 9, since the trigger level of the first latch control signal CT1 occurs at the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _180, the first gating enable signal en _0 will change from low to high at the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _180 (the middle of the low level of the first clock signal CK _00 numbered 4), so that the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate will start to be output at the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _180 (the middle of the low level of the first clock signal CK _00 numbered 4).
Since the first clock gating signal CK00_ gate is at a low level before the output is started, when the output is started, the level of the first clock gating signal CK _00 (the second half of the low level denoted by 4) copied by the first clock gating signal CK00_ gate is also at a low level, where there is no transition edge, and then the first clock gating signal CK00_ gate outputs a first rising edge (corresponding to the first falling edge of the third clock gating signal CK180_ gate) and outputs a first falling edge (corresponding to the first rising edge of the third clock gating signal CK180_ gate) after half of the period of the first clock gating signal CK _ 00. Before the output is started, the third clock gating signal CK180_ gate is at a high level, and after the output is started, the level (the second half of the high level denoted by 4) of the third clock gating signal CK _180 copied by the third clock gating signal CK180_ gate is also at a high level, where there is no transition edge, and then the third clock gating signal CK180_ gate outputs a first rising edge (corresponding to the first rising edge of the first clock gating signal CK00_ gate) and outputs a first rising edge (corresponding to the first falling edge of the first clock gating signal CK00_ gate) after half of the period of the first clock gating signal CK _ 00.
That is, in the present embodiment, the first transition edge of the first clock gating signal CK00_ gate is a rising edge, the first transition edge of the third clock gating signal CK180_ gate is a falling edge, the first rising edge of the third clock gating signal CK180_ gate lags behind the first rising edge of the third clock gating signal CK180_ gate, and the lag time is one-half of the first clock gating signal CK _ 00.
Similarly, the first transition edge of the second clock gating signal CK90_ gate is a rising edge, the first transition edge of the fourth clock gating signal CK270_ gate is a falling edge, the first rising edge of the fourth clock gating signal CK270_ gate lags the first rising edge of the second clock gating signal CK90_ gate by one-half of the first clock gating signal CK _ 00.
(2) In the present embodiment, the trigger level of the second latch control signal CT2 is the low level of the second clock signal CK _90 and/or the high level of the fourth clock signal CK _270, the trigger level of the first latch control signal CT1 is the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _180, i.e., the trigger level of the second latch control signal CT2 lags behind the trigger level of the first latch control signal CT1 by a quarter of the first clock signal CK _00, so that the first transition edges of the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate, which are controlled to be output by the second gating enable signal en _90, can lag behind the first transition edges of the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate, which are controlled to be output by the first gating enable signal en _0, and the lag time is one quarter of the first clock signal CK _ 00.
Therefore, in the present embodiment, the first rising edge of the first clock gating signal CK00_ gate and the first falling edge of the third clock gating signal CK180_ gate occur first, then the first rising edge of the second clock gating signal CK90_ gate and the first falling edge of the fourth clock gating signal CK270_ gate, then the first rising edge of the first clock gating signal CK00_ gate and the first rising edge of the third clock gating signal CK180_ gate, and finally the first falling edge of the second clock gating signal CK90_ gate and the first rising edge of the fourth clock gating signal CK270_ gate, i.e., the first rising edge of each phase in the present embodiment, can be discharged sequentially.
In the four-phase clock gating signal output by the embodiment, the clock gating signal of the initial phase (i.e., the first clock gating signal CK00_ gate) starts to be output in the phase of the first clock signal CK _00, and the first rising edge is output.
As an alternative embodiment, as shown in fig. 7, the clock gating module (either one of the first clock gating module 20-1 and the second clock gating module 20-2) includes a first nand gate 21, a second nand gate 22, a third nand gate 23, and a fourth nand gate 24;
a first input end of the first nand-gate 21 is used as a first signal input end I21 of the clock gating module, a second input end of the first nand-gate 21 is used as a first gating enable end P21 of the clock gating module, an output end of the first nand-gate 21 is connected to a first input end of the second nand-gate 22, a second input end of the second nand-gate 22 is used for receiving a high level, and an output end of the second nand-gate 22 is used as a first signal output end O21 of the clock gating module;
the first input end of the third nand gate 23 is configured to receive a high level, the second input end of the third nand gate 23 is used as the second signal input end I22 of the clock gating module, the output end of the third nand gate 23 is connected to the second input end of the fourth nand gate 24, the first input end of the fourth nand gate 24 is used as the second gating enable end P22 of the clock gating module, and the output end of the fourth nand gate 24 is used as the second signal output end O22 of the clock gating module.
In the clock gating module of this embodiment, when the first gating enable terminal P21 is high, the first nand gate 21 and the second nand gate 22 are equivalent to two-stage inverters, and the first signal output terminal O21 replicates the signal input by the first signal input terminal I21; when the first gate enable terminal P21 is low, the first signal output terminal O21 outputs a low level no matter whether the signal received by the first signal input terminal I21 is high or low;
when the second gating enable terminal P22 is high, the third nand gate 23 and the fourth nand gate 24 act as two stages of inverters, and the second signal output terminal O22 copies the signal input by the second signal input terminal I22; when the second gate enable terminal P22 is low, the second signal output terminal O22 outputs a high level regardless of whether the signal received at the second signal input terminal I22 is high or low.
Meanwhile, in the embodiment, a first signal transmission channel of the clock gating module is constructed through the first nand gate 21 and the second nand gate 22, a second signal transmission channel of the clock gating module is constructed through the third nand gate 23 and the fourth nand gate 24, the two transmission channels are both constructed through two stages of nand gates, and good matching performance and symmetry are guaranteed.
As an alternative embodiment, as shown in fig. 7, the first signal input terminal I21 of the first clock gating module 20-1 is configured to receive the first clock signal CK _00, the second signal input terminal I22 of the first clock gating module 20-1 is configured to receive the third clock signal CK _180, the first gating enable terminal P21 and the second gating enable terminal P22 of the first clock gating module 20-1 are configured to receive the first gating enable signal en _0, the first signal output terminal O21 of the first clock gating module 20-1 is configured to output the first clock gating signal CK00_ gate, and the second signal output terminal O22 of the first clock gating module 20-1 is configured to output the third clock gating signal CK180_ gate;
the first signal input end I21 of the second clock gating module 20-2 is configured to receive the second clock signal CK _90, the second signal input end I22 of the second clock gating module 20-2 is configured to receive the fourth clock signal CK _270, the first gating enable end P21 and the second gating enable end P22 of the second clock gating module 20-2 are configured to receive the second gating enable signal en _90, the first signal output end O21 of the second clock gating module 20-2 is configured to output the second clock gating signal CK90_ gate, and the second signal output end O22 of the second clock gating module 20-2 is configured to output the fourth clock gating signal CK270_ gate.
In this embodiment, when the first switch signal EN _ EVEN is high, the first gating enable signal EN _0 is high, and the second gating enable signal EN _90 is high, at this time, the first clock gating signal CK00_ gate output by the first signal output terminal O21 of the first clock gating block 20-1 duplicates the first clock signal CK _00 received by the first signal input terminal I21, and the third clock gating signal CK180_ gate output by the second signal output terminal O22 of the first clock gating block 20-1 duplicates the third clock signal CK _180 received by the second signal input terminal I22; the second clock gating signal CK90_ gate output by the first signal output end O21 of the second clock gating module 20-2 duplicates the second clock signal CK _90 received by the first signal input end I21, and the fourth clock gating signal CK270_ gate output by the second signal output end O22 of the second clock gating module 20-2 duplicates the fourth clock signal CK _270 received by the second signal input end I22;
when the first switch signal EN _ EVEN is low, the first gating enable signal EN _0 is low, the second gating enable signal EN _90 is low, the first signal output end O21 of the first clock gating block 20-1 outputs a low level, and the second signal output end O22 of the first clock gating block 20-1 outputs a high level; the first signal output terminal O21 of the second clock gating module 20-2 outputs a low level, and the second signal output terminal O22 of the second clock gating module 20-2 outputs a high level.
In the scheme provided by this embodiment, the clock output circuit 2 is composed of two identical clock gating modules, and each clock gating module is built by a two-stage nand gate, so that each clock signal in the four-phase clock signals is correspondingly connected to one signal input end, that is, one clock gating signal can be output at the corresponding signal output end.
As an alternative embodiment, as shown in fig. 10, the latch control circuit 1 includes the second latch module 10-2, and the clock output circuit 2 includes two clock gating modules, namely a first clock gating module 20-1 and a second clock gating module 20-2;
the first clock gating module 20-1 is configured to gate the third clock signal CK _180 under the control of the third gating enable signal en _180 to output a first clock gating signal CK00_ gate, and gate the first clock signal CK _00 to output a third clock gating signal CK180_ gate;
the second clock gating module 20-2 is configured to gate the fourth clock signal CK _270 to output a second clock gating signal CK90_ gate and gate the second clock signal CK _90 to output a fourth clock gating signal CK270_ gate under the control of the fourth gating enable signal en _ 270;
the phase difference between adjacent ones of the first, second, third, and fourth clock gating signals CK00_ gate, CK90_ gate, CK180_ gate, and CK270_ gate is 90 °.
In this embodiment, when the third gate enable signal en _180 and the fourth gate enable signal en _270 are high, the first clock gate signal CK00_ gate replicates the third clock signal CK _180, the second clock gate signal CK90_ gate replicates the fourth clock signal CK _270, the third clock gate signal CK180_ gate replicates the first clock signal CK _00, the fourth clock gate signal CK270_ gate replicates the second clock signal CK _90, and in the four-phase clock signals, since the angle at which the fourth clock signal CK _270 lags behind the third clock signal CK _180 is 90 °, the angle at which the second clock gate signal CK90_ gate lags behind the first clock gate signal CK00_ gate is 90 °, the angle at which the second clock signal CK _90 lags behind the first clock signal CK _00 is 90 °, the angle at which the fourth clock gate signal CK270_ gate lags behind the third clock signal CK _180 _ gate is 90 °, the angle at which the fourth clock gate signal CK _270 _180 ° lags behind the third clock gate is 90, the angle of 90 °, the fourth clock signal CK _270 _ gate is 90, and the angle of the fourth clock signal CK _180 _ gate is 90, the second clock signal CK _90, the angle of 90, the second clock signal CK _90, the fourth clock signal CK _90, the clock signal CK _00, the clock signal CK _270 _180 is high and the clock signal CK _270 is high, the clock signal CK _0 and the clock signal CK _00, the clock signal CK _0 and the clock signal CK _00 are the clock signal CK _0 and, since the first clock gating signal CK _00 and the third clock gating signal CK _180 are a pair of differential signals, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate are still differential signals, and the angle of the third clock gating signal CK180_ gate lagging behind the first clock gating signal CK00_ gate is 180 °, in this embodiment, the phase relationship of the four phase clock gating signals obtained by cross copying the differential signals can still be maintained, meanwhile, the first clock gating signal CK00_ gate and the third clock gating signal CK180_ gate can still maintain the differential relationship, and the second clock gating signal CK90_ gate and the fourth clock gating signal CK270_ gate can still maintain the differential relationship.
In this embodiment, a scheme of controlling two clock signals by one gating enable signal en simultaneously can obtain a four-phase clock gating signal with a constant phase relationship, and the area of the whole gating circuit can be greatly reduced. Meanwhile, two clock signals are simultaneously controlled through one gating enable signal en, the differential signals can be simultaneously turned on and off, and the symmetry of the differential signals is strictly kept.
As an alternative embodiment, as shown in fig. 11 and 12, the trigger level of the third latch control signal CT3 occurs at the high level of the first clock signal CK _00 and/or the low level of the third clock signal CK _ 180; a trigger level of the fourth latch control signal CT4 occurs at a high level of the second clock signal CK _90 and/or a low level of the fourth clock signal CK _ 270;
the first clock gating module 20-1 is configured to copy the third clock signal CK _180 to start the first clock gating signal CK00_ gate to turn over when the third gating enable signal en _180 is high, and output a low level to stop the first clock gating signal CK00_ gate from turning over when the third gating enable signal en _180 is low;
the first clock gating module 20-1 is further configured to copy the first clock signal CK _00 when the third gating enable signal en _180 is high, so as to start the inversion of the third clock gating signal CK180_ gate, and output a high level when the third gating enable signal en _180 is low, so as to stop the inversion of the third clock gating signal CK180_ gate;
the second clock gating module 20-2 is configured to copy the fourth clock gating signal CK _270 to start the second clock gating signal CK90_ gate when the fourth gating enable signal en _270 is high, and output a low level to stop the second clock gating signal CK90_ gate when the fourth gating enable signal en _270 is low;
the second clock gating module 20-2 is further configured to copy the second clock signal CK _90 when the fourth gating enable signal en _270 is high, so as to start the fourth clock gating signal CK270_ gate to turn over, and output a high level when the fourth gating enable signal en _270 is low, so as to stop the fourth clock gating signal CK270_ gate from turning over.
In this embodiment, the trigger level of the third latch control signal CT3 is the high level of the first clock signal CK _00 and/or the low level of the third clock signal CK _180, the trigger level of the fourth latch control signal CT4 is the high level of the second clock signal CK _90 and/or the low level of the fourth clock signal CK _270, and is just 180 ° different from the trigger level of the first latch control signal CT1 and the trigger level of the second latch control signal CT2, which can avoid the glitch problem that the second switch signal EN _ ODD is suddenly turned off or on when the trigger level of the third latch control signal CT3 or the fourth latch signal CT2 does not arrive, and the glitch problem that the four-phase clock gating signal is suddenly turned off or on when the trigger level of the first latch control signal CT3 or the fourth latch signal CT2 and the trigger level occurs at the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _180, Embodiments of the low level of the second clock signal CK _90 and/or the high level of the fourth clock signal CK _270 just form a complement.
In addition, the embodiment can also avoid the problem that the second switching signal EN _ ODD is suddenly turned off or turned on when the trigger level of the third latch control signal CT3 or the fourth latch control signal CT4 arrives, so that the four-phase clock gating signal is suddenly turned off or turned on to cause glitch, that is, the embodiment can ensure that the clock gating signal of each phase in the four-phase clock gating signal can output a complete cycle before and after the gating circuit is turned on and off, and glitch does not occur.
In addition, the present embodiment can also ensure that the phase relationship between the clock gating signals is not changed, and the first rising edge of each phase can be sequentially released.
The analysis process of this embodiment to generate the above effects is similar to the embodiment shown in fig. 7, and is not described herein again.
It should be noted that, in the four-phase clock gating signals output in the present embodiment, the clock gating signal at the start phase (i.e., the first clock gating signal CK00_ gate) starts to be output at the phase of the third clock signal CK _180, and the first clock gating signal emits a rising edge. In the embodiment shown in fig. 7, the clock gating signal of the initial phase (i.e., the first clock gating signal CK00_ gate) starts to be output at the phase of the first clock signal CK _00, and the first clock gating signal emits a rising edge.
As an alternative embodiment, as shown in fig. 11, the clock gating module (including any one of the first clock gating module 20-1 and the second clock gating module 20-2) includes a first nand gate 21, a second nand gate 22, a third nand gate 23, and a fourth nand gate 24;
a first input end of the first nand-gate 21 is used as a first signal input end I21 of the clock gating module, a second input end of the first nand-gate 21 is used as a first gating enable end P21 of the clock gating module, an output end of the first nand-gate 21 is connected to a first input end of the second nand-gate 22, a second input end of the second nand-gate 22 is used for receiving a high level, and an output end of the second nand-gate 22 is used as a first signal output end O21 of the clock gating module;
the first input end of the third nand gate 23 is configured to receive a high level, the second input end of the third nand gate 23 is used as the second signal input end I22 of the clock gating module, the output end of the third nand gate 23 is connected to the second input end of the fourth nand gate 24, the first input end of the fourth nand gate 24 is used as the second gating enable end P22 of the clock gating module, and the output end of the fourth nand gate 24 is used as the second signal output end O22 of the clock gating module.
In this embodiment, when the first gate enable terminal P21 is high, the first nand gate 21 and the second nand gate 22 act as two stages of inverters, and the first signal output terminal O21 replicates the signal input by the first signal input terminal I21; when the first gating enable terminal P21 is low, the first signal output terminal O21 outputs a low level no matter whether the signal received by the first signal input terminal I21 is high or low;
when the second gating enable terminal P22 is high, the third nand gate 23 and the fourth nand gate 24 act as two stages of inverters, and the second signal output terminal O22 copies the signal input by the second signal input terminal I22; when the second gate enable terminal P21 is low, the second signal output terminal O22 outputs a high level regardless of whether the signal received by the second signal input terminal I22 is high or low.
Meanwhile, in the embodiment, a first signal transmission channel of the clock gating module is constructed through the first nand gate 21 and the second nand gate 22, a second signal transmission channel of the clock gating module is constructed through the third nand gate 23 and the fourth nand gate 24, the two transmission channels are both constructed through two stages of nand gates, and good matching performance and symmetry are guaranteed.
As an alternative embodiment, as shown in fig. 11, the first signal input terminal I21 of the first clock gating module 20-1 is configured to receive the third clock signal CK _180, the second signal input terminal I22 of the first clock gating module 20-1 is configured to receive the first clock signal CK _00, the first gate enable terminal P21 and the second gate enable terminal P22 of the first clock gating module 20-1 are configured to receive the third gate enable signal en _180, the first signal output terminal O21 of the first clock gating module 20-1 is configured to output the first clock gating signal CK00_ gate, and the second signal output terminal O22 of the first clock gating module 20-1 is configured to output the third clock gating signal CK180_ gate;
the first signal input end I21 of the second clock gating module 20-2 is configured to receive the fourth clock signal CK _270, the second signal input end I22 of the second clock gating module 20-2 is configured to receive the second clock signal CK _90, the first gating enable end P21 and the second gating enable end P22 of the second clock gating module 20-2 are configured to receive the fourth gating enable signal en _270, the first signal output end O21 of the second clock gating module 20-2 is configured to output the second clock gating signal CK90_ gate, and the second signal output end O22 of the second clock gating module 20-2 is configured to output the fourth clock gating signal CK270_ gate.
The scheme can ensure that the phase relation among the clock gating signals is unchanged, the clock gating signals of all the phases can output complete cycles before and after the gating circuit is switched on and off, burrs cannot occur, and the first rising edge of all the phases can be sequentially released. In the four-phase clock gating signal output by the present embodiment, the clock gating signal of the initial phase (i.e., the first clock gating signal CK00_ gate) starts to be output at the phase of the first clock signal CK _00, and the first clock gating signal emits a rising edge.
The clock output circuit 2 of the scheme is composed of two identical clock gating modules, and each clock gating module is built by a two-stage NAND gate, so that the load and the transmission path of the clock signal of each phase in the four-phase clock signal are consistent in the clock output circuit 2, and good matching and symmetry are guaranteed.
As an alternative embodiment, as shown in fig. 13, the latch control circuit 1 includes the first latch module 10-1 and the second latch module 10-2, and the clock output circuit 2 includes two first clock gating modules 20-1, namely, a first clock gating module 20-11 and a second first clock gating module 20-12, and two second clock gating modules 20-2, namely, a first second clock gating module 20-21 and a second clock gating module 20-22;
the first clock gating module 20-11 is configured to gate the first clock signal CK _00 under the control of the first gating enable signal en _0 to output a first clock gating signal CK00_ gate, or gate the third clock signal CK _180 under the control of the third gating enable signal en _180 to output the first clock gating signal CK00_ gate;
the second first clock gating module 20-12 is configured to gate the second clock signal CK _90 under the control of the second gating enable signal en _90 to output a second clock gating signal CK90_ gate, or gate the fourth clock signal CK _270 under the control of the fourth gating enable signal en _270 to output the second clock gating signal CK90_ gate;
the first second clock gating module 20 to 21 is configured to gate the third clock signal CK _180 under the control of the first gating enable signal en _0 to output a third clock gating signal CK180_ gate, or gate the first clock signal CK _00 under the control of the third gating enable signal en _180 to output the third clock gating signal CK180_ gate;
the second clock gating module 20 to 22 is configured to gate the fourth clock signal CK _270 under the control of the second gating enable signal en _90 to output a fourth clock gating signal CK270_ gate, or gate the second clock signal CK _90 under the control of the fourth gating enable signal en _270 to output the fourth clock gating signal CK270_ gate;
the phase difference between adjacent ones of the first, second, third, and fourth clock gating signals CK00_ gate, CK90_ gate, CK180_ gate, and CK270_ gate is 90 °.
In the embodiment integrated with the embodiments shown in fig. 7 and 11, by controlling the first switch signal EN _ EVEN, the four-phase clock gating signal of the clock gating signal (i.e., the first clock gating signal CK00_ gate) provided by the embodiment of fig. 7 and having the phase of the first clock signal CK _00 as the initial phase can be output; by controlling the second switching signal EN _ ODD, the embodiment of fig. 11 outputs the four-phase clock gating signal of the clock gating signal (i.e., the first clock gating signal CK00_ gate) starting at the phase of the third clock signal CK _ 180.
As an alternative embodiment, as shown in fig. 14 and 15, the trigger level of the first latch control signal CT1 occurs at the low level of the first clock signal CK _00 and/or the high level of the third clock signal CK _ 180; the trigger level of the second latch control signal CT2 occurs at a low level of the second clock signal CK _90 and/or a high level of the fourth clock signal CK _ 270; a trigger level of the third latch control signal CT3 occurs at a high level of the first clock signal CK _00 and/or a low level of the third clock signal CK _ 180; the trigger level of the fourth latch control signal CT4 occurs at a high level of the second clock signal CK _90 and/or a low level of the fourth clock signal CK _ 270;
the first clock gating module 20-11 is configured to copy the first clock signal CK _00 when the first gating enable signal en _0 is high, so as to start the first clock gating signal CK00_ gate to turn over, and output a low level when the first gating enable signal en _0 is low, so as to stop the first clock gating signal CK00_ gate from turning over; the clock signal input unit is further configured to copy the third clock signal CK _180 when the third gating enable signal en _180 is high, so as to start the inversion of the first clock gating signal CK00_ gate, and output a high level when the third gating enable signal en _180 is low, so as to stop the inversion of the first clock gating signal CK00_ gate;
the second first clock gating module 20-12 is configured to copy the second clock signal CK _90 to start the second clock gating signal CK90_ gate to turn over when the second gating enable signal en _90 is high, and output a low level to stop the second clock gating signal CK90_ gate from turning over when the second gating enable signal en _90 is low; the clock signal circuit is further configured to copy the fourth clock signal CK _270 to start the second clock gating signal CK90_ gate to be inverted when the fourth gating enable signal en _270 is high, and output a high level to stop the second clock gating signal CK90_ gate to be inverted when the fourth gating enable signal en _270 is low;
the first second clock gating module 20-21 is configured to copy the third clock gating signal CK _180 when the first gating enable signal en _0 is high, so as to start the inversion of the third clock gating signal CK180_ gate, and output a low level when the first gating enable signal en _0 is low, so as to stop the inversion of the third clock gating signal CK180_ gate; the clock signal controller is further configured to copy the first clock signal CK _00 to start the third clock gating signal CK180_ gate to be inverted when the third gating enable signal en _180 is high, and output a high level to stop the third clock gating signal CK180_ gate to be inverted when the third gating enable signal en _180 is low;
the second clock gating module 20 to 22 is configured to copy the fourth clock signal CK _270 to start outputting the second clock gating signal CK90_ gate when the second gating enable signal en _90 is high, and output a low level to stop the second clock gating signal CK90_ gate from inverting when the second gating enable signal en _90 is low; and is further configured to copy the second clock signal CK _90 to start the fourth clock gating signal CK270_ gate to turn over when the fourth gating enable signal en _270 is high, and to output a high level to stop the fourth clock gating signal CK270_ gate from turning over when the fourth gating enable signal en _270 is low.
This embodiment is an integration of the embodiment of fig. 7 and the embodiment of fig. 11, and thus naturally has the effects of both the embodiment of fig. 7 and the embodiment of fig. 11, and details are not repeated here. Meanwhile, compared with the embodiments of fig. 7 and 11, the present embodiment can realize the controllability of the clock gating signal (i.e., the first clock gating signal CK00_ gate) at the start phase in the four-phase clock gating signal, and can switch between the two, thereby providing a more comprehensive four-phase clock gating signal for the device that uses the clock later.
As an alternative embodiment, as shown in fig. 14, the first clock gating module 20-1 (including any one of the first clock gating module 20-11 and the second first clock gating module 20-12) includes a first nand gate 21, a second nand gate 22, a third nand gate 23, a fourth nand gate 24, and a second inverter 25, a first input end of the first nand gate 21 is used as the first signal input end I211 of the first clock gating module 20-1, a second input end of the first nand gate 21 is used as the first gating enable end P211 of the first clock gating module 20-1, a first input end of the second nand gate 22 is used as the second signal input end I212 of the first clock gating module 20-1, a second input end of the second nand gate 22 is used as the second gating enable end P212 of the first clock gating module 20-1, the output end of the first nand gate 21 is connected to the first input end of the third nand gate 23, the output end of the second nand gate 22 is connected to the second input end of the third nand gate 23, the output end of the third nand gate 23 is connected to the first input end of the fourth nand gate 24, the second input end of the fourth nand gate 24 is configured to receive a high level, the output end of the fourth nand gate 24 is connected to the input end of the second inverter 25, and the output end of the second inverter 25 is used as the signal output end O21 of the first clock gating module 20-1.
In the clock gating module of this embodiment, when the first gating enable terminal P211 is high and the second gating enable terminal P212 is low, the first nand gate 21, the third nand gate 23, and the fourth nand gate 24 are equivalent to three-level inverters, and the second inverter 25 is added to form a four-level inverter, at this time, the signal output terminal O21 replicates the signal input by the first signal input terminal I211; when the first gate enable terminal P211 is low and the second gate enable terminal P212 is low, the signal output terminal O21 outputs a low level no matter whether the signal received by the first signal input terminal I211 is high or low;
when the first gating enable terminal P211 is low and the second gating enable terminal P212 is high, the second nand gate 22, the third nand gate 23 and the fourth nand gate 24 are equivalent to a three-level inverter, and are added with the first nand gate 21 to form a four-level inverter, at this time, the signal output terminal O21 replicates the signal input by the second signal input terminal I212; when the first gating enable terminal P211 is low and the second gating enable terminal P212 is low, the signal output terminal O21 outputs a low level regardless of whether the signal received by the second signal input terminal I212 is high or low.
As an alternative embodiment, as shown in fig. 14, the first signal input terminal I211 of the first clock gating module 20-11 is configured to receive the first clock signal CK _00, the second signal input terminal I212 of the first clock gating module 20-11 is configured to receive the third clock signal CK _180, the first gating enable terminal P211 of the first clock gating module 20-11 is configured to receive the first gating enable signal en _0, the second gating enable terminal P212 of the first clock gating module 20-11 is configured to receive the third gating enable signal en _180, and the signal output terminal O21 of the first clock gating module 20-11 is configured to output the first clock gating signal CK00_ gate;
the first signal input terminal I211 of the second first clock gating module 20-12 is configured to receive the second clock signal CK _90, the second signal input terminal I212 of the second first clock gating module 20-12 is configured to receive the fourth clock signal CK _270, the first gating enable terminal P211 of the second first clock gating module 20-12 is configured to receive the second gating enable signal en _90, the second gating enable terminal P212 of the second first clock gating module 20-12 is configured to receive the fourth gating enable signal en _270, and the signal output terminal O21 of the second first clock gating module 20-12 is configured to output the second clock gating signal CK90_ gate.
In this embodiment, when the first switch signal EN _ EVEN is high and the second switch signal EN _ ODD is low, the first gating enable signal EN _0 is high, the second gating enable signal EN _90 is high, the third gating enable signal EN _180 is low, and the fourth gating enable signal EN _270 is low, at this time, the first clock gating signal CK00_ gate output by the signal output end O21 of the first clock gating module 20-11 duplicates the first clock signal CK _00 received by the first signal input end I211 of the first clock gating module 20-11, and the second clock gating signal CK90_ gate output by the signal output end O21 of the second first clock gating module 20-12 duplicates the second clock signal CK _90 received by the first signal input end I211 of the second first clock gating module 20-12;
when the first switch signal EN _ EVEN is low and the second switch signal EN _ ODD is high, the first gating enable signal EN _0 is low, the second gating enable signal EN _90 is low, the third gating enable signal EN _180 is high, and the fourth gating enable signal EN _270 is high, at this time, the first clock gating signal CK00_ gate output by the signal output terminal O21 of the first clock gating module 20-11 duplicates the third clock signal CK _180 received by the first signal input terminal I211 of the first clock gating module 20-11, and the second clock gating signal CK90_ gate output by the signal output terminal O21 of the second first clock gating module 20-12 duplicates the fourth clock signal CK _270 received by the first signal input terminal I211 of the second first clock gating module 20-12;
when the first switch signal EN _ EVEN is low and the second switch signal EN _ ODD is low, the first gating enable signal EN _0 is low, the second gating enable signal EN _90 is low, the third gating enable signal EN _180 is low, and the fourth gating enable signal EN _270 is low, at which time, the signal output terminal O21 of the first and second clock gating modules 20 to 21 outputs a low level, and the signal output terminal O21 of the second and second clock gating modules 20 to 22 outputs a low level.
As an alternative embodiment, as shown in fig. 14, the second clock gating module 20-2 (including any one of the first second clock gating module 20-21 and the second clock gating module 20-22) includes a fifth nand gate 26, a sixth nand gate 27, a seventh nand gate 28, an eighth nand gate 29, a ninth nand gate 30, and a third inverter 31, a first input end of the fifth nand gate 26 serves as the first signal input end I221 of the second clock gating module 20-2, a second input end of the fifth nand gate 26 is configured to receive a high level, an output end of the fifth nand gate 26 is connected to a first input end of the sixth nand gate 27, a second input end of the sixth nand gate 27 serves as the first gating enable end P221 of the second clock gating module 20-2, and a first input end of the seventh nand gate 28 serves as the second signal input end of the second clock gating module 20-2 A terminal I222, a second input end of the seventh nand gate 28 is configured to receive a high level, an output end of the seventh nand gate 28 is connected to a first input end of the eighth nand gate 29, a second input end of the eighth nand gate 29 is used as a second gate enable terminal P222 of the second clock gating module 20-2, an output end of the sixth nand gate 27 is connected to a first input end of the ninth nand gate 30, an output end of the eighth nand gate 29 is connected to a second input end of the ninth nand gate 30, an output end of the ninth nand gate 30 is connected to an input end of the third inverter 31, and an output end of the third inverter 31 is used as a signal output end O22 of the second clock gating module 20-2.
In the clock gating module of this embodiment, when the first gating enable terminal P221 is high and the second gating enable terminal P222 is low, the fifth nand gate 26, the sixth nand gate 27, and the ninth nand gate 30 are equivalent to three-level inverters, and in addition to the third inverter 31, four-level inverters are formed, and at this time, the signal output terminal O22 replicates the signal input by the first signal input terminal I221; when the first gate enable terminal P221 is low and the second gate enable terminal P222 is low, the signal output terminal O22 outputs a high level no matter whether the signal received by the first signal input terminal I221 is high or low;
when the first gate enable terminal P221 is low and the second gate enable terminal P222 is high, the seventh nand gate 28, the eighth nand gate 29, and the ninth nand gate 30 are equivalent to three-level inverters, and the third inverter 31 is added to constitute a four-level inverter, at this time, the signal output terminal O22 duplicates the signal input by the second signal input terminal I222; when the first gate enable terminal P221 is low and the second gate enable terminal P222 is low, the signal output terminal O22 outputs a high level no matter whether the signal received by the second signal input terminal I222 is high or low.
As an alternative embodiment, as shown in fig. 14, the first signal input terminal I221 of the first second clock gating module 20-21 is configured to receive the third clock signal CK _180, the second signal input terminal I222 of the first second clock gating module 20-21 is configured to receive the first clock signal CK _00, the first gating enable terminal P221 of the first second clock gating module 20-21 is configured to receive the first gating enable signal en _0, the second gating enable terminal P222 of the first second clock gating module 20-21 is configured to receive the third gating enable signal en _180, and the signal output terminal O22 of the first second clock gating module 20-21 is configured to output the third clock gating signal CK180_ gate;
the first signal input terminal I221 of the second clock gating module 20-22 is configured to receive the fourth clock signal CK _270, the second signal input terminal I222 of the second clock gating module 20-22 is configured to receive the second clock signal CK _90, the first gating enable terminal P221 of the second clock gating module 20-22 is configured to receive the second gating enable signal en _90, the second gating enable terminal P222 of the second clock gating module 20-22 is configured to receive the fourth gating enable signal en _270, and the signal output terminal O22 of the second clock gating module 20-22 is configured to output the fourth clock gating signal CK270_ gate.
In this embodiment, when the first switch signal EN _ EVEN is high and the second switch signal EN _ ODD is low, the first gating enable signal EN _0 is high, the second gating enable signal EN _90 is high, the third gating enable signal EN _180 is low, and the fourth gating enable signal EN _270 is low, at this time, the third clock gating signal CK180_ gate output by the signal output terminal O22 of the first second clock gating module 20-21 replicates the third clock signal CK _180 received by the first signal input terminal I221 of the first second clock gating module 20-21, and the fourth clock gating signal CK270_ gate output by the signal output terminal O22 of the second clock gating module 20-22 replicates the fourth clock signal CK270_ 270 received by the first signal input terminal I221 of the second clock gating module 20-22;
when the first switch signal EN _ EVEN is low and the second switch signal EN _ ODD is high, the first gating enable signal EN _0 is low, the second gating enable signal EN _90 is low, the third gating enable signal EN _180 is high, and the fourth gating enable signal EN _270 is high, at this time, the third clock gating signal CK180_ gate output by the signal output terminal O22 of the first second clock gating module 20-21 duplicates the first clock signal CK _00 received by the first signal input terminal I221 of the first second clock gating module 20-21, and the fourth clock gating signal CK270_ gate output by the signal output terminal O22 of the second clock gating module 20-22 duplicates the second clock signal CK _90 received by the first signal input terminal I221 of the second clock gating module 20-22;
when the first switch signal EN _ EVEN is low and the second switch signal EN _ ODD is low, the first gating enable signal EN _0 is low, the second gating enable signal EN _90 is low, the third gating enable signal EN _180 is low, and the fourth gating enable signal EN _270 is low, at which time, the signal output terminal O22 of the first and second clock gating modules 20 to 21 outputs a high level, and the signal output terminal O22 of the second and second clock gating modules 20 to 22 outputs a high level.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
in the embodiment provided by the application, the latch control circuit performs latch processing on the switch signal of the gated clock through at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal, the clock output circuit performs gate control on the multi-phase clock signals by receiving at least one gated enable signal generated by the latch control circuit to output the multi-phase clock gated signals, when the switch signal of the gated clock changes from low to high, the gated enable signal changes from low to high at the trigger level of the latch control signal (i.e. at least one clock signal in the multi-phase clock signals) of the latch control circuit, at this time, the switch equivalent to the clock output circuit is closed, and the multi-phase clock gated signals start to be output; when the switch signal of the gating clock changes from high to low, the trigger level of the gating enable signal in the latch control signal (namely at least one clock signal in the multi-phase clock signals) of the latch control circuit changes from high to low, at the moment, the switch of the clock output circuit is equivalently switched off, the multi-phase clock gating signal stops outputting, and then the gating of the multi-phase clock signals is realized, and the direct high-frequency turnover of the multi-phase clock signals is avoided, so that the relevant circuits which work by using the multi-phase frequency division clock generate turnover at the transition edge of each clock, thereby causing unnecessary power consumption loss.
Example two
As shown in fig. 16, the present embodiment provides an electronic device 300 including:
a controller 310;
a memory 320; and
a multi-phase clock signal gating circuit 330 disposed between the controller 310 and the memory 320, wherein the controller 310 operates the memory 320 through the multi-phase clock signal gating circuit 330;
the multi-phase clock signal gating circuit 330 comprises: the latch control circuit 1 is used for latching a switching signal of a gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal;
and the clock output circuit 2 is used for performing gating processing on the multi-phase clock signal according to the at least one gating enabling signal so as to output the multi-phase clock gating signal.
As an alternative embodiment, the multiphase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, a phase difference between adjacent clock signals is 90 °, the switching signals of the gated clock at least include a first switching signal and/or a second switching signal, and the latch control circuit 1 at least includes one latch module or two latch modules;
the first latch module is configured to latch the first switch signal under control of a first latch control signal to generate a first gate control enable signal, and latch the first gate control enable signal under control of a second latch control signal to generate a second gate control enable signal, where the first latch control signal includes the first clock signal and/or the third clock signal, and the second latch control signal includes the second clock signal and/or the fourth clock signal;
the second latch module is configured to latch the second switch signal under the control of a third latch control signal to generate a third gating enable signal, and latch the third gating enable signal under the control of a fourth latch control signal to generate a fourth gating enable signal, where the third latch control signal includes the first clock signal and/or the third clock signal, and the fourth latch control signal includes the second clock signal and/or the fourth clock signal;
the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal, and the lag time or lead time is half of the period of the first clock signal; the trigger level of the second latch control signal lags or leads the trigger level of the fourth latch control signal by a time lag or lead of one-half of the period of the first clock signal.
In a specific implementation process, when the controller 310 operates the memory 320 through the gating circuit 330 for the multi-phase clock signals, the gating circuit 330 for the multi-phase clock signals may also be any one of the gating circuits in the first embodiment.
EXAMPLE III
As shown in fig. 17, the present embodiment provides a gating method of a multi-phase clock signal, including:
step S101: latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal;
step S102: and performing gating processing on the multi-phase clock signal according to the at least one gating enable signal to output a multi-phase clock gating signal.
As an alternative embodiment, the multiphase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, a phase difference between adjacent clock signals is 90 °, and the switching signals of the gated clock at least include a first switching signal and/or a second switching signal;
the gating method comprises the following steps:
performing latch processing on the first switch signal under the control of a first latch control signal to generate a first gate control enable signal, and performing latch processing on the first gate control enable signal under the control of a second latch control signal to generate a second gate control enable signal, wherein the first latch control signal comprises the first clock signal and/or the third clock signal, and the second latch control signal comprises the second clock signal and/or the fourth clock signal; or
Performing latch processing on the second switching signal under the control of a third latch control signal to generate a third gate control enable signal, and performing latch processing on the third gate control enable signal under the control of a fourth latch control signal to generate a fourth gate control enable signal, wherein the third latch control signal comprises the first clock signal and/or the third clock signal, and the fourth latch control signal comprises the second clock signal and/or the fourth clock signal;
the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal by a time lag or lead of one-half of the period of the first clock signal; the trigger level of the second latch control signal lags or leads the trigger level of the fourth latch control signal by a time lag or lead of one-half of the period of the first clock signal.
As an alternative embodiment, the trigger level of the second latch control signal lags behind the trigger level of the first latch control signal by a time equal to one quarter of the period of the first clock signal;
the trigger level of the fourth latch control signal lags behind the trigger level of the third latch control signal by a time that is one-quarter of the period of the first clock signal.
As an alternative embodiment, the gating method includes:
under the control of the first gating enable signal, gating processing is carried out on the first clock signal to output a first clock gating signal, and gating processing is carried out on the third clock signal to output a third clock gating signal;
under the control of the second gating enable signal, gating the second clock signal to output a second clock gating signal, and gating the fourth clock signal to output a fourth clock gating signal;
the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
As an alternative embodiment, the trigger level of the first latch control signal occurs at a low level of the first clock signal and/or at a high level of the third clock signal; a trigger level of the second latch control signal occurs at a low level of the second clock signal and/or a high level of the fourth clock signal;
the gating method comprises the following steps:
when the first gating enable signal is high, copying the first clock signal to enable the first clock gating signal to start to turn over, and when the first gating enable signal is low, outputting low level to enable the first clock gating signal to stop turning over;
when the first gating enable signal is high, copying the third clock signal to enable the third clock gating signal to start to turn over, and when the first gating enable signal is low, outputting high level to enable the third clock gating signal to stop turning over;
when the second gating enable signal is high, copying the second clock signal to enable the second clock gating signal to start to turn over, and when the second gating enable signal is low, outputting low level to enable the second clock gating signal to stop turning over;
when the second gating enable signal is high, copying the fourth clock signal to enable the fourth clock gating signal to start to turn over, and when the second gating enable signal is low, outputting high level to enable the fourth clock gating signal to stop turning over.
As an alternative embodiment, the gating method includes:
under the control of the third gating enable signal, gating processing is carried out on the third clock signal to output a first clock gating signal, and gating processing is carried out on the first clock signal to output a third clock gating signal;
under the control of the fourth gating enable signal, gating the fourth clock signal to output a second clock gating signal, and gating the second clock signal to output a fourth clock gating signal;
the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
As an alternative embodiment, the trigger level of the third latch control signal occurs at a high level of the first clock signal and/or a low level of the third clock signal; a trigger level of the fourth latch control signal occurs at a high level of the second clock signal and/or a low level of the fourth clock signal;
the gating method comprises the following steps:
when the third gating enable signal is high, copying the third clock signal to enable the first clock gating signal to start to turn over, and when the third gating enable signal is low, outputting low level to enable the first clock gating signal to stop turning over;
when the third gating enable signal is high, copying the first clock signal to enable the third clock gating signal to start to turn over, and when the third gating enable signal is low, outputting high level to enable the third clock gating signal to stop turning over;
when the fourth gating enable signal is high, copying the fourth clock signal to enable the second clock gating signal to start to turn over, and when the fourth gating enable signal is low, outputting low level to enable the second clock gating signal to stop turning over;
when the fourth gating enable signal is high, copying the second clock signal to enable the fourth clock gating signal to start to turn over, and when the fourth gating enable signal is low, outputting high level to enable the fourth clock gating signal to stop turning over.
As an alternative embodiment, the gating method includes:
gating the first clock signal under the control of the first gating enable signal to output a first clock gating signal, or gating the third clock signal under the control of the third gating enable signal to output the first clock gating signal;
gating the second clock signal under the control of the second gating enable signal to output a second clock gating signal, or gating the fourth clock signal under the control of the fourth gating enable signal to output the second clock gating signal;
gating the third clock signal under the control of the first gating enable signal to output a third clock gating signal, or gating the first clock signal under the control of the third gating enable signal to output the third clock gating signal;
gating the fourth clock signal under the control of the second gating enable signal to output a fourth clock gating signal, or gating the second clock signal under the control of the fourth gating enable signal to output the fourth clock gating signal;
the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
As an alternative embodiment, the gating method includes:
a trigger level of the first latch control signal occurs at a low level of the first clock signal and/or a high level of the third clock signal; a trigger level of the second latch control signal occurs at a low level of the second clock signal and/or a high level of the fourth clock signal; a trigger level of the third latch control signal occurs at a high level of the first clock signal and/or a low level of the third clock signal; a trigger level of the fourth latch control signal occurs at a high level of the second clock signal and/or a low level of the fourth clock signal;
the gating method comprises the following steps:
when the first gating enable signal is high, copying the first clock signal to enable the first clock gating signal to start to turn over, and when the first gating enable signal is low, outputting low level to enable the first clock gating signal to stop turning over; the clock signal generating circuit is further configured to copy the third clock signal when the third gating enable signal is high, so as to start the first clock gating signal to be inverted, and output a high level when the third gating enable signal is low, so as to stop the first clock gating signal from being inverted;
when the second gating enable signal is high, copying the second clock signal to enable the second clock gating signal to start to turn over, and when the second gating enable signal is low, outputting low level to enable the second clock gating signal to stop turning over; the clock signal generator is further configured to copy the fourth clock signal when the fourth gating enable signal is high, so that the second clock gating signal starts to be inverted, and output a high level when the fourth gating enable signal is low, so that the second clock gating signal stops being inverted;
copying the third clock signal when the first gating enable signal is high so that the third clock gating signal starts to turn over, and outputting a low level when the first gating enable signal is low so that the third clock gating signal stops turning over; the clock signal generating circuit is further configured to copy the first clock signal when the third gating enable signal is high, so that the third clock gating signal starts to flip, and output a high level when the third gating enable signal is low, so that the third clock gating signal stops flipping;
copying the fourth clock signal to start outputting the second clock gating signal when the second gating enable signal is high, and outputting a low level to stop the second clock gating signal from turning over when the second gating enable signal is low; and the clock signal generating unit is further configured to copy the second clock signal when the fourth gating enable signal is high, so that the fourth clock gating signal starts to flip, and output a high level when the fourth gating enable signal is low, so that the fourth clock gating signal stops flipping.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (24)

1. A gating circuit for multi-phase clock signals, comprising:
the latch control circuit is used for latching the switch signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal;
the clock output circuit is used for carrying out gating processing on the multi-phase clock signals according to the at least one gating enabling signal so as to output the multi-phase clock gating signals;
when the switch signal of the gating clock changes from low to high, the gating enable signal changes from low to high under the trigger of the trigger level of the latch control signal of the latch control circuit, at the moment, the switch of the clock output circuit is closed, and the multiphase clock gating signal starts to be output; when the switch signal of the gating clock changes from high to low, the gating enable signal changes from high to low under the trigger of the trigger level of the latch control signal of the latch control circuit, at the moment, the switch of the clock output circuit is switched off, and the multi-phase clock gating signal stops outputting.
2. The gate control circuit of claim 1, wherein the multi-phase clock signals are four-phase clock signals, the four-phase clock signals sequentially comprise a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, a phase difference between adjacent clock signals is 90 °, the switching signals of the gate control clock comprise at least a first switching signal and/or a second switching signal, and the latch control circuit comprises at least one latch module or two latch modules;
the first latch module is configured to perform latch processing on the first switch signal under control of a first latch control signal to generate a first gating enable signal, and perform latch processing on the first gating enable signal under control of a second latch control signal to generate a second gating enable signal, where the first latch control signal includes the first clock signal and/or the third clock signal, and the second latch control signal includes the second clock signal and/or the fourth clock signal;
the second latch module is configured to latch the second switch signal under the control of a third latch control signal to generate a third gating enable signal, and latch the third gating enable signal under the control of a fourth latch control signal to generate a fourth gating enable signal, where the third latch control signal includes the first clock signal and/or the third clock signal, and the fourth latch control signal includes the second clock signal and/or the fourth clock signal;
the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal, and the lag time or lead time is half of the period of the first clock signal; the trigger level of the second latch control signal lags or leads the trigger level of the fourth latch control signal by a time lag or lead of one-half of the period of the first clock signal.
3. The gate control circuit of claim 2, wherein a trigger level of the second latch control signal lags a trigger level of the first latch control signal by a time of one quarter of a period of the first clock signal;
the trigger level of the fourth latch control signal lags behind the trigger level of the third latch control signal by a time that is one-quarter of the period of the first clock signal.
4. The gating circuit of claim 3, wherein the latch module comprises two stages of latches, the two stages of latches being cascaded;
the first-stage latch in the first latch module is used for latching the first switching signal under the control of the first latch control signal to generate a first gating enable signal;
the second-stage latch in the first latch module is used for latching the first gating enable signal under the control of the second latch control signal to generate a second gating enable signal;
the first-stage latch in the second latch module is used for latching the second switch signal under the control of the third latch control signal to generate a third gating enable signal;
and the second-stage latch in the second latch module is used for latching the third gating enable signal under the control of the fourth latch control signal to generate the fourth gating enable signal.
5. The gating circuit of claim 4, wherein the latch comprises a first tri-state not gate, a second tri-state not gate, and a first inverter;
the input end of the first tri-state not gate is used as the input end of the latch, the output end of the first tri-state not gate is connected with the output end of the second tri-state not gate and the input end of the first inverter, and the output end of the first inverter is connected with the input end of the second tri-state not gate and is used as the output end of the latch;
the low-level enabling end of the first tri-state not gate is used as a first enabling end of the latch, the high-level enabling end of the first tri-state not gate is used as a second enabling end of the latch, the low-level enabling end of the second tri-state not gate is used as a third enabling end of the latch, and the high-level enabling end of the second tri-state not gate is used as a fourth enabling end of the latch.
6. The gating circuit of claim 5, wherein an input of the first stage latch of the first latch block is to receive the first switching signal, wherein an output of the first stage latch of the first latch block is to output the first gating enable signal, wherein the first enable terminal of the first stage latch of the first latch block and the fourth enable terminal of the first stage latch of the first latch block are to receive the first clock signal, wherein the second enable terminal of the first stage latch of the first latch block and the third enable terminal of the first stage latch of the first latch block are to receive the third clock signal;
an input end of the second-stage latch in the first latch module is configured to receive the first gating enable signal, an output end of the second-stage latch in the first latch module is configured to output the second gating enable signal, a first enable end of the second-stage latch in the first latch module and a fourth enable end of the second-stage latch in the first latch module are configured to receive the second clock signal, and a second enable end of the second-stage latch in the first latch module and a third enable end of the second-stage latch in the first latch module are configured to receive the fourth clock signal;
an input end of the first-stage latch in the second latch module is configured to receive the second switching signal, an output end of the first-stage latch in the second latch module is configured to output the third gating enable signal, a first enable end of the first-stage latch in the second latch module and a fourth enable end of the first-stage latch in the second latch module are configured to receive the third clock signal, and a second enable end of the first-stage latch in the second latch module and a third enable end of the first-stage latch in the second latch module are configured to receive the first clock signal;
the input end of the second stage latch in the second latch module is configured to receive the third gating enable signal, the output end of the second stage latch in the second latch module is configured to output the fourth gating enable signal, the first enable end of the second stage latch in the second latch module and the fourth enable end of the second stage latch in the second latch module are configured to receive the fourth clock signal, and the second enable end of the second stage latch in the second latch module and the third enable end of the second stage latch in the second latch module are configured to receive the second clock signal.
7. The gating circuit of claim 3, wherein the latch control circuit comprises the first latch block, the clock output circuit comprises two clock gating blocks;
the first clock gating module is used for gating the first clock signal to output a first clock gating signal and gating the third clock signal to output a third clock gating signal under the control of the first gating enable signal;
the second clock gating module is used for gating the second clock signal to output a second clock gating signal and gating the fourth clock signal to output a fourth clock gating signal under the control of the second gating enable signal;
the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
8. The gate control circuit of claim 7, wherein a trigger level of the first latch control signal occurs at a low level of the first clock signal and/or a high level of the third clock signal; a trigger level of the second latch control signal occurs at a low level of the second clock signal and/or a high level of the fourth clock signal;
the first clock gating module is used for copying the first clock signal when the first gating enable signal is high so as to enable the first clock gating signal to start to turn over, and outputting low level when the first gating enable signal is low so as to enable the first clock gating signal to stop turning over;
the first clock gating module is further configured to copy the third clock signal when the first gating enable signal is high, so as to start the inversion of the third clock gating signal, and output a high level when the first gating enable signal is low, so as to stop the inversion of the third clock gating signal;
the second clock gating module is used for copying the second clock signal when the second gating enable signal is high so as to enable the second clock gating signal to start to turn over, and outputting low level when the second gating enable signal is low so as to enable the second clock gating signal to stop turning over;
the second clock gating module is further configured to copy the fourth clock signal when the second gating enable signal is high, so as to start to flip the fourth clock gating signal, and output a high level when the second gating enable signal is low, so as to stop the flip of the fourth clock gating signal.
9. The gate circuit of claim 8, wherein the clock gating module comprises a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate;
a first input end of the first nand gate is used as a first signal input end of the clock gating module, a second input end of the first nand gate is used as a first gating enable end of the clock gating module, an output end of the first nand gate is connected with a first input end of the second nand gate, a second input end of the second nand gate is used for receiving a high level, and an output end of the second nand gate is used as a first signal output end of the clock gating module;
the first input end of the third nand gate is configured to receive a high level, the second input end of the third nand gate is used as the second signal input end of the clock gating module, the output end of the third nand gate is connected to the second input end of the fourth nand gate, the first input end of the fourth nand gate is used as the second gating enable end of the clock gating module, and the output end of the fourth nand gate is used as the second signal output end of the clock gating module.
10. The gate control circuit of claim 9, wherein the first signal input of the first clock gating block is configured to receive the first clock signal, the second signal input of the first clock gating block is configured to receive the third clock signal, the first gate enable and the second gate enable of the first clock gating block are configured to receive the first gate enable signal, the first signal output of the first clock gating block is configured to output the first clock gating signal, and the second signal output of the first clock gating block is configured to output the third clock gating signal;
a first signal input end of the second clock gating module is configured to receive the second clock signal, a second signal input end of the second clock gating module is configured to receive the fourth clock signal, a first gating enable end and a second gating enable end of the second clock gating module are configured to receive the second gating enable signal, a first signal output end of the second clock gating module is configured to output the second clock gating signal, and a second signal output end of the second clock gating module is configured to output the fourth clock gating signal.
11. The gating circuit of claim 3, wherein the latch control circuit comprises the second latch block, and the clock output circuit comprises two clock gating blocks;
the first clock gating module is used for gating the third clock signal to output a first clock gating signal and gating the first clock signal to output a third clock gating signal under the control of the third gating enable signal;
the second clock gating module is used for gating the fourth clock signal to output a second clock gating signal and gating the second clock signal to output a fourth clock gating signal under the control of the fourth gating enable signal;
the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
12. The gate control circuit of claim 11, wherein a trigger level of the third latch control signal occurs at a high level of the first clock signal and/or a low level of the third clock signal; a trigger level of the fourth latch control signal occurs at a high level of the second clock signal and/or a low level of the fourth clock signal;
the first clock gating module is used for copying the third clock signal when the third gating enable signal is high so as to enable the first clock gating signal to start to turn over, and outputting low level when the third gating enable signal is low so as to enable the first clock gating signal to stop turning over;
the first clock gating module is further configured to copy the first clock signal when the third gating enable signal is high, so that the third clock gating signal starts to turn over, and output a high level when the third gating enable signal is low, so that the third clock gating signal stops turning over;
the second clock gating module is configured to copy the fourth clock signal when the fourth gating enable signal is high, so as to start to flip the second clock gating signal, and output a low level when the fourth gating enable signal is low, so as to stop the flip of the second clock gating signal;
the second clock gating module is further configured to copy the second clock signal when the fourth gating enable signal is high, so as to start to flip the fourth clock gating signal, and output a high level when the fourth gating enable signal is low, so as to stop the flip of the fourth clock gating signal.
13. The gating circuit of claim 12, wherein the clock gating module comprises a first nand gate, a second nand gate, a third nand gate, and a fourth nand gate;
a first input end of the first nand gate is used as a first signal input end of the clock gating module, a second input end of the first nand gate is used as a first gating enable end of the clock gating module, an output end of the first nand gate is connected with a first input end of the second nand gate, a second input end of the second nand gate is used for receiving high level, and an output end of the second nand gate is used as a first signal output end of the clock gating module;
the first input end of the third nand gate is configured to receive a high level, the second input end of the third nand gate is used as the second signal input end of the clock gating module, the output end of the third nand gate is connected to the second input end of the fourth nand gate, the first input end of the fourth nand gate is used as the second gating enable end of the clock gating module, and the output end of the fourth nand gate is used as the second signal output end of the clock gating module.
14. The gating circuit of claim 13, wherein the first clock gating block has a first signal input for receiving the third clock signal, a second signal input for receiving the first clock signal, a first gate enable and a second gate enable for receiving the third gate enable, a first signal output for outputting the first clock gating signal, and a second signal output for outputting the third clock gating signal;
a first signal input end of the second clock gating module is configured to receive the fourth clock signal, a second signal input end of the second clock gating module is configured to receive the second clock signal, a first gating enable end and a second gating enable end of the second clock gating module are configured to receive the fourth gating enable signal, a first signal output end of the second clock gating module is configured to output the second clock gating signal, and a second signal output end of the second clock gating module is configured to output the fourth clock gating signal.
15. The gating circuit of claim 3, wherein the latch control circuit comprises the first latch block and the second latch block, and wherein the clock output circuit comprises two first clock gating blocks and two second clock gating blocks;
the first clock gating module is used for gating the first clock signal under the control of the first gating enable signal to output a first clock gating signal, or gating the third clock signal under the control of the third gating enable signal to output the first clock gating signal;
the second first clock gating module is used for gating the second clock signal under the control of the second gating enable signal to output a second clock gating signal, or gating the fourth clock signal under the control of the fourth gating enable signal to output the second clock gating signal;
the first second clock gating module is used for gating the third clock signal under the control of the first gating enable signal to output a third clock gating signal, or gating the first clock signal under the control of the third gating enable signal to output the third clock gating signal;
the second clock gating module is configured to gate the fourth clock signal under the control of the second gating enable signal to output a fourth clock gating signal, or gate the second clock signal under the control of the fourth gating enable signal to output the fourth clock gating signal;
the phase difference between adjacent signals in the first clock gating signal, the second clock gating signal, the third clock gating signal and the fourth clock gating signal is 90 degrees.
16. The gate control circuit of claim 15,
a trigger level of the first latch control signal occurs at a low level of the first clock signal and/or a high level of the third clock signal; a trigger level of the second latch control signal occurs at a low level of the second clock signal and/or a high level of the fourth clock signal; a trigger level of the third latch control signal occurs at a high level of the first clock signal and/or a low level of the third clock signal; a trigger level of the fourth latch control signal occurs at a high level of the second clock signal and/or a low level of the fourth clock signal;
the first clock gating module is used for copying the first clock signal when the first gating enable signal is high so as to enable the first clock gating signal to start to turn over, and outputting low level when the first gating enable signal is low so as to enable the first clock gating signal to stop turning over; the clock signal generating circuit is further configured to copy the third clock signal when the third gating enable signal is high, so that the first clock gating signal starts to be inverted, and output a high level when the third gating enable signal is low, so that the first clock gating signal stops being inverted;
the second first clock gating module is used for copying the second clock signal when the second gating enable signal is high so as to enable the second clock gating signal to start to turn over, and outputting low level when the second gating enable signal is low so as to enable the second clock gating signal to stop turning over; the clock signal generating circuit is further configured to copy the fourth clock signal when the fourth gating enable signal is high, so as to start to flip the second clock gating signal, and output a high level when the fourth gating enable signal is low, so as to stop the second clock gating signal from flipping;
the first second clock gating module is used for copying the third clock signal when the first gating enable signal is high so as to enable the third clock gating signal to start to turn over, and outputting low level when the first gating enable signal is low so as to enable the third clock gating signal to stop turning over; the clock signal generating circuit is further configured to copy the first clock signal when the third gating enable signal is high, so that the third clock gating signal starts to turn over, and output a high level when the third gating enable signal is low, so that the third clock gating signal stops turning over;
the second clock gating module is configured to copy the fourth clock signal to start outputting the second clock gating signal when the second gating enable signal is high, and output a low level to stop the second clock gating signal from turning over when the second gating enable signal is low; and the clock signal generating unit is further configured to copy the second clock signal when the fourth gating enable signal is high, so that the fourth clock gating signal starts to flip, and output a high level when the fourth gating enable signal is low, so that the fourth clock gating signal stops flipping.
17. The gate control circuit of claim 16, wherein the first clock gating module comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, and a second inverter, a first input of the first NAND gate is used as a first signal input of the first clock gating module, a second input of the first NAND gate is used as a first gate enable of the first clock gating module, a first input of the second NAND gate is used as a second signal input of the first clock gating module, a second input of the second NAND gate is used as a second gate enable of the first clock gating module, an output of the first NAND gate is connected to a first input of the third NAND gate, an output of the second NAND gate is connected to a second input of the third NAND gate, and an output of the third NAND gate is connected to a first input of the fourth NAND gate, the second input end of the fourth nand gate is used for receiving high level, the output end of the fourth nand gate is connected with the input end of the second inverter, and the output end of the second inverter is used as the signal output end of the first clock gating module.
18. The gate control circuit of claim 17,
a first signal input end of the first clock gating module is configured to receive the first clock signal, a second signal input end of the first clock gating module is configured to receive the third clock signal, a first gating enable end of the first clock gating module is configured to receive the first gating enable signal, a second gating enable end of the first clock gating module is configured to receive the third gating enable signal, and a signal output end of the first clock gating module is configured to output the first clock gating signal;
a first signal input end of the second first clock gating module is configured to receive the second clock signal, a second signal input end of the second first clock gating module is configured to receive the fourth clock signal, a first gating enable end of the second first clock gating module is configured to receive the second gating enable signal, a second gating enable end of the second first clock gating module is configured to receive the fourth gating enable signal, and a signal output end of the second first clock gating module is configured to output the second clock gating signal.
19. The gate control circuit of claim 16, wherein the second clock gating module comprises a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, a ninth NAND gate, and a third inverter, a first input of the fifth NAND gate is used as the first signal input of the second clock gating module, a second input of the fifth NAND gate is used for receiving a high level, an output of the fifth NAND gate is connected to the first input of the sixth NAND gate, a second input of the sixth NAND gate is used as the first gate enable of the second clock gating module, a first input of the seventh NAND gate is used as the second signal input of the second clock gating module, a second input of the seventh NAND gate is used for receiving a high level, and an output of the seventh NAND gate is connected to the first input of the eighth NAND gate, the second input end of the eighth nand gate is used as the second gate-control enable end of the second clock gating module, the output end of the sixth nand gate is connected to the first input end of the ninth nand gate, the output end of the eighth nand gate is connected to the second input end of the ninth nand gate, the output end of the ninth nand gate is connected to the input end of the third inverter, and the output end of the third inverter is used as the signal output end of the second clock gating module.
20. The gate control circuit of claim 19,
a first signal input end of the first second clock gating module is configured to receive the third clock signal, a second signal input end of the first second clock gating module is configured to receive the first clock signal, a first gating enable end of the first second clock gating module is configured to receive the first gating enable signal, a second gating enable end of the first second clock gating module is configured to receive the third gating enable signal, and a signal output end of the first second clock gating module is configured to output the third clock gating signal;
a first signal input end of the second clock gating module is configured to receive the fourth clock signal, a second signal input end of the second clock gating module is configured to receive the second clock signal, a first gating enable end of the second clock gating module is configured to receive the second gating enable signal, a second gating enable end of the second clock gating module is configured to receive the fourth gating enable signal, and a signal output end of the second clock gating module is configured to output the fourth clock gating signal.
21. An electronic device, comprising:
a controller;
a memory; and
a gating circuit of the multi-phase clock signal disposed between the controller and the memory, wherein the controller operates the memory through the gating circuit of the multi-phase clock signal;
the gating circuit of the multi-phase clock signal comprises: the latch control circuit is used for latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal;
the clock output circuit is used for carrying out gating processing on the multi-phase clock signals according to the at least one gating enabling signal so as to output the multi-phase clock gating signals;
when the switch signal of the gating clock changes from low to high, the gating enable signal changes from low to high under the trigger of the trigger level of the latch control signal of the latch control circuit, at the moment, the switch of the clock output circuit is closed equivalently, and the multiphase clock gating signal starts to be output; when the switch signal of the gating clock changes from high to low, the gating enable signal changes from high to low under the trigger of the trigger level of the latch control signal of the latch control circuit, at the moment, the switch of the clock output circuit is equivalently switched off, and the multi-phase clock gating signal stops outputting.
22. The electronic device according to claim 21, wherein the multi-phase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, a phase difference between adjacent clock signals is 90 °, the clock-gated switching signals include at least a first switching signal and/or a second switching signal, and the latch control circuit includes at least one latch module or two latch modules;
the first latch module is configured to perform latch processing on the first switch signal under control of a first latch control signal to generate a first gating enable signal, and perform latch processing on the first gating enable signal under control of a second latch control signal to generate a second gating enable signal, where the first latch control signal includes the first clock signal and/or the third clock signal, and the second latch control signal includes the second clock signal and/or the fourth clock signal;
the second latch module is configured to latch the second switch signal under the control of a third latch control signal to generate a third gating enable signal, and latch the third gating enable signal under the control of a fourth latch control signal to generate a fourth gating enable signal, where the third latch control signal includes the first clock signal and/or the third clock signal, and the fourth latch control signal includes the second clock signal and/or the fourth clock signal;
the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal, and the lag time or lead time is half of the period of the first clock signal; a trigger level of the second latch control signal lags or leads a trigger level of the fourth latch control signal by a time half of a period of the first clock signal.
23. A method for gating a multi-phase clock signal, comprising:
latching the switching signal of the gated clock according to at least one clock signal in the multi-phase clock signals to generate at least one gated enable signal;
gating the multi-phase clock signal according to the at least one gating enable signal to output a multi-phase clock gating signal;
when the switch signal of the gating clock changes from low to high, the gating enable signal changes from low to high under the trigger of the trigger level of the latch control signal of the latch control circuit, at the moment, the switch of the clock output circuit is closed equivalently, and the multiphase clock gating signal starts to be output; when the switch signal of the gating clock changes from high to low, the gating enable signal changes from high to low under the trigger of the trigger level of the latch control signal of the latch control circuit, at the moment, the switch of the clock output circuit is equivalently switched off, and the multi-phase clock gating signal stops outputting.
24. The gating method of claim 23, wherein the multi-phase clock signals are four-phase clock signals, the four-phase clock signals sequentially include a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, and a phase difference between adjacent clock signals is 90 °, and the switching signals of the gated clock comprise at least a first switching signal and/or a second switching signal;
the gating method comprises the following steps:
performing latch processing on the first switch signal under the control of a first latch control signal to generate a first gate control enable signal, and performing latch processing on the first gate control enable signal under the control of a second latch control signal to generate a second gate control enable signal, wherein the first latch control signal comprises the first clock signal and/or the third clock signal, and the second latch control signal comprises the second clock signal and/or the fourth clock signal; or
Under the control of a third latch control signal, performing latch processing on the second switch signal to generate a third gate control enable signal, and under the control of a fourth latch control signal, performing latch processing on the third gate control enable signal to generate a fourth gate control enable signal, wherein the third latch control signal comprises the first clock signal and/or the third clock signal, and the fourth latch control signal comprises the second clock signal and/or the fourth clock signal;
the trigger level of the first latch control signal lags or leads the trigger level of the third latch control signal by a time lag or lead of one-half of the period of the first clock signal; the trigger level of the second latch control signal lags or leads the trigger level of the fourth latch control signal by a time lag or lead of one-half of the period of the first clock signal.
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