CN109217849B - Phase interpolator - Google Patents
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- CN109217849B CN109217849B CN201710527949.0A CN201710527949A CN109217849B CN 109217849 B CN109217849 B CN 109217849B CN 201710527949 A CN201710527949 A CN 201710527949A CN 109217849 B CN109217849 B CN 109217849B
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- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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Abstract
A phase interpolator includes an input port and an output port, at least one data selector, and at least one smoothing buffer. The input port of each data selector is respectively connected with the input port of the phase interpolator, the output port of each data selector is connected with the input port of the corresponding smoothing buffer, and the output port of each smoothing buffer is respectively connected with the output port of the phase interpolator. The smoothing buffer includes N delay elements. Each delay cell includes a first inverter and a second inverter. The phase interpolator outputs the signals obtained from the data selector in a delay way through N cascaded delay units in the smoothing buffer, so that the linearity of the phase interpolator can be improved, and the more the number of the cascaded delay units is, the longer the delay time is.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a phase interpolator.
Background
Phase Interpolators (PIs) are widely used in various circuits, such as polar modulation circuits, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs) and Clock Data Recovery (CDR) circuits in wireless transceivers, mainly for interpolating and synthesizing high-precision multipath phase relationships or as sampling clock signals, and the linearity of the phase interpolator determines the overall noise performance of the application circuit, so that a phase interpolator with high linearity becomes a key for design.
The phase interpolator is mainly implemented by interpolation means, such as voltage interpolation, which can be implemented in CMOS. A general interpolation method is to use two adjacent phases that are 90 degrees out of phase and mix them in a certain ratio to obtain an intermediate phase. The position of the intermediate phase can be adjusted by adjusting the mixing proportion, and the adjustment of any phase from 0 degree to 90 degrees is realized. If a data selector is added to select two adjacent phases of 0 degrees, 90 degrees, 180 degrees, 270 degrees before adjusting the mixing, any phase from 0 degrees to 360 degrees can be obtained.
Since the influence of power supply noise in the circuit greatly affects the final performance of the circuit, the delay of one first inverter can generate a jitter of several picoseconds due to the power supply noise, and both a delay line (delay line) and a phase interpolator can be equivalently regarded as a cascade of several first inverters. Compared with the delay line, the inverter circuit of the Complementary metal-oxide-semiconductor (CMOS) structure of the phase interpolator has fewer stages, strong power supply noise suppression capability and wide phase adjustment range.
However, the gain of the CMOS inverter of the phase interpolator having the CMOS structure is high, so that the linearity and the accuracy of the phase interpolator are not high, thereby affecting the sampling of the clock signal.
Disclosure of Invention
Embodiments of the present invention provide a phase interpolator, which can improve linearity of the phase interpolator.
In a first aspect, a phase interpolator is provided, comprising:
input and output ports, at least one data selector and at least one smoothing buffer. The input port of each data selector is respectively connected with the input port of the phase interpolator, the output port of each data selector is connected with the input port of the corresponding smoothing buffer, and the output port of each smoothing buffer is respectively connected with the output port of the phase interpolator. The smoothing buffer comprises N delay units, wherein N is a positive integer greater than or equal to 2. Each delay unit comprises a first inverter and a second inverter, wherein a first input port of the first inverter of the kth delay unit is connected with an output port of the first inverter of the (k-1) th delay unit, a first input port of the second inverter of the kth delay unit is connected with an output port of the first inverter of the kth delay unit, and an output port of the second inverter of each delay unit is respectively connected with an output port of the phase interpolator; and the input port of the first inverter in the 1 st delay unit is connected with the output port of the corresponding data selector.
The phase interpolator delays and outputs the signals obtained from the data selector through the N cascaded delay units in the smoothing buffer, so that the linearity of the phase interpolator can be improved, and the more the number of the delay units is, the longer the delay time is.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the first inverter includes a first transistor, a second transistor, i cascaded third transistors, and j cascaded fourth transistors. The first transistor, the second transistor, the third transistor, and the fourth transistor include a first port, a second port, and a third port, respectively. A first port of the first transistor and a first port of the second transistor are respectively connected to a first input port of the first inverter, a second port of the first transistor is connected to a third port of any one of the cascaded i third transistors, and a third port of the first transistor and a third port of the second transistor are respectively connected to an output port of the first inverter. The second port of the second transistor is connected to the third port of any one of the j fourth transistors of the cascade. And the second port of any one third transistor of the cascaded i third transistors is switched on a high level, wherein the first port of the 1 st third transistor is switched on a low level. A second port of any one fourth transistor of the j cascaded fourth transistors is connected with a low level, wherein a first port of a 1 st fourth transistor is connected with a high level; wherein i and j are positive integers greater than 2.
The first inverter composed of the first transistor, the second transistor, the third crystal and the fourth crystal can invert the phase of the signal transmitted by the data selector and output the inverted phase, thereby realizing the effect of time delay.
With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the first transistor and the third transistor may be, but are not limited to, P-type field effect transistors, and the second transistor and the fourth transistor may be, but are not limited to, N-type field effect transistors.
With reference to the first aspect, in a third possible implementation manner of the first aspect, the second inverter includes a fifth transistor, a sixth transistor, p cascaded seventh transistors, and q cascaded eighth transistors. The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor include a first port, a second port, and a third port, respectively. A first port of the fifth transistor and a first port of the sixth transistor are respectively connected to a first input port of the second inverter, a second port of the fifth transistor is connected to a third port of any seventh transistor of the p cascaded seventh transistors, and a third port of the fifth transistor and a third port of the sixth transistor are respectively connected to an output port of the second inverter. A third port of the sixth transistor is connected to a third port of any eighth transistor of the q eighth transistors of the cascade. And a second port of any seventh transistor of the p seventh transistors in the cascade is switched into a high level, wherein a first port of the 1 st seventh transistor is switched into a low level. And a second port of any eighth transistor of the q cascaded eighth transistors is connected with a low level, wherein a first port of a 1 st eighth transistor is connected with a high level, and p and q are positive integers greater than 2.
Through the second inverter formed by the fifth transistor, the sixth transistor, the seventh crystal and the eighth crystal, the phase of the signal transmitted by the first inverter can be inverted and output, the phase of the signal output by the phase interpolator is ensured to be the same as the phase of the signal output by the data selector, and meanwhile, the signal output by the data selector can be delayed and output.
With reference to the first aspect or the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the fifth transistor and the seventh transistor may be, but are not limited to, P-type field effect transistors, and the sixth transistor and the eighth transistor may be, but are not limited to, N-type field effect transistors.
With reference to the first aspect or any one of the first to fourth possible implementation manners of the first aspect, in a fifth possible implementation manner of the first aspect, the delay unit further includes a ground capacitor, and an output port of each delay unit is connected to the ground capacitor. The grounding capacitor can store the current output by the delay unit and control the output rate of the phase interpolator.
Drawings
Fig. 1 is a schematic structural diagram of a system architecture according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a phase interpolator according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a smoothing buffer according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an inverter according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an inverter according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a phase interpolator according to an embodiment of the present invention.
Detailed Description
Fig. 1 shows a system architecture to which an embodiment of the present invention is applicable, which includes a Phase Locked Loop (PLL), a Phase Interpolator (PI), a Finite State Machine (FSM), and a Phase Detector (PD). In the system, a PLL (phase locked loop) sends in-phase (I) and quadrature (Q) signals to a PI (phase locked loop), and a Clock (CK) with any phase between 0 degree and 360 degrees can be obtained through the PIIQ) Signal, the CKIQCan participate in the Data (Data, D) in the PDin) After FSM integration, the sampling signal generates phase control bit of PI, so that CKIQIs maintained at D at any timeinOf the center of (c).
In the system architecture, PI is mainly used for synthesizing high-precision multipath phases through an interpolation means, and the sampling result of a clock signal can be influenced by the linearity of the PI. Based on this, an embodiment of the present invention provides a phase interpolator, which has a structure shown in fig. 2, and specifically includes:
an input port 201, an output port 202, at least one data selector 203 and at least one smoothing buffer 204.
Wherein, the input port of each data selector 203 is connected to the input port 201 of the phase interpolator, and the output port of each data selector 203 is connected to the input port of the corresponding smoothing buffer 204. One data selector 203 may be correspondingly connected to one smooth buffer 204, or may be correspondingly connected to a plurality of smooth buffers 204, and in actual application, the number of the connected smooth buffers 204 may be selected according to simulation based on a requirement on a time length of a delay. The output port of each smoothing buffer 204 is connected to the output port 202 of the phase interpolator, respectively. The smoothing buffer 204 includes N delay units 2041, where N is a positive integer greater than or equal to 2. The phase interpolator may delay and output the signal obtained from the data selector 203 through N cascaded delay units 2041, so that the linearity of the phase interpolator may be improved.
In the embodiment of the present invention, each of the N delay units 2041 includes a first inverter 20411 and a second inverter 20412. The signal output from the data selector 203 is delayed once by the first inverter 20411 in the delay unit 2041 and then delayed a second time by the second inverter 20412, and after a signal is inverted twice, the phase of the output signal is the same as the phase at the input. For example, the phase of the signal input from the first inverter 20411 is 90 degrees, the phase of the signal converted by the first inverter 20411 is 270 degrees, and the phase of the signal is changed to 90 degrees after the conversion by the second inverter 20412. Similarly, when the signal input by the first inverter 20411 is at a high level, the output signal is at a low level, and the signal output by the second inverter 20412 is at a high level again, wherein the process of converting the high level into the low level by the first inverter 20411 and the process of converting the high level into the low level by the second inverter 20412 both generate a delay. Therefore, the more the delay unit 2041, the longer the delay generated by the signal output from the smoothing buffer 204, and the signal delay output is realized.
The transition of the signal from the data selector 203 through one inverter will generate a delay, i.e. a rising or falling edge, and the more delay units 2041 are connected, the more rising or falling edges are generated, and the smoother the rising or falling edge of the signal output by the phase interpolator. When the signal output is represented graphically, the rising edge or the falling edge can be represented as a bump, and the linearity is not good if the rising edge or the falling edge generated by one or two inverters can cause the output signal to jump. The more delay units 2041 are, the more rising edges or falling edges are generated, the more dense the bumps are, so that the bumps look like a smooth curve, and the linearity of the output of the phase interpolator can be improved.
Based on the above structure, fig. 3 exemplarily shows a structure of a smoothing buffer 204 provided by an embodiment of the present invention, in fig. 3, a first input port of a first inverter 20411 of a kth delay unit 2041 is connected to an output port of the first inverter 20411 of a kth-1 th delay unit 2041, a first input port of a second inverter 20412 of the kth delay unit 2041 is connected to an output port of the first inverter 20411 of the kth delay unit 2041, and an output port of the second inverter 20412 of each delay unit 2041 is connected to an output port 202 of the phase interpolator. An input port of the first inverter 20411 in the 1 st delay unit 2041 of the N delay units 2041 is connected to the output port of the corresponding data selector 203, the first inverter 20411 of the 1 st delay unit 2041 is respectively connected to the first input port of the second inverter 20412 and the first input port of the first inverter 20411 of the 2 nd delay unit 2041, and k is greater than or equal to 2 and is less than N. The signal output by the data selector 203 passes through the first inverter 20411 of the 1 st delay unit 2041, then passes through the first input port of the second inverter of the 1 st delay unit 2041 and the subsequent cascaded delay unit 2041, and finally converges to the output port 202 of the phase interpolator to complete the output.
The phase interpolator outputs the signal obtained from the data selector in a delay way through the cascaded delay units in the smoothing buffer, so that the linearity of the phase interpolator can be improved, and the more the number of the cascaded delay units is, the longer the delay time is.
In order to obtain the best linearity, the total delay of the cascaded N delay units is about half a clock cycle, so the available frequency of the smoothing buffer obtained by using a fixed number of delay units is narrow. If the smoothing buffer needs to be adjustable for a large range of frequencies, the structure in fig. 4 below can be used to adjust the strength of the third and fourth transistors to increase or decrease the delay of the delay unit, making the total delay length close to half a clock cycle.
Optionally, fig. 4 exemplarily shows a structure of any one of the first inverters 20411 in the N delay units 2041, in fig. 4, the first inverter 20411 includes a first transistor, a second transistor, i cascaded third transistors and j cascaded fourth transistors, the first transistor, the second transistor, the third transistor and the fourth transistor respectively include a first port, a second port and a third port, and i and j are positive integers greater than 2.
It should be noted that the first port of each transistor described in the embodiments of the present invention may be a gate of the transistor, the second port and the third port may be a source or a drain of the transistor, and if the second port is a source, the third port is a drain; if the second port is a drain, the third port is a source.
A first port of the first transistor and a first port of the second transistor are respectively connected to a first input port of the first inverter 20411, a second port of the first transistor is connected to a third port of any one of the i cascaded third transistors, and a third port of the first transistor and a third port of the second transistor are respectively connected to an output port of the first inverter 20411. The second port of the second transistor is connected to the third port of any one of the j fourth transistors in the cascade. The second port of any one of the i cascaded third transistors is switched on a high level, wherein the first port of the 1 st third transistor is switched on a low level. The first port of the 1 st third transistor is connected with a low level, so that the 1 st third transistor is in a normally open state, and the power supply strength entering the first transistor is adjusted. When the 1 st third transistor is normally on, the high level accessed by the second port can enter the third port of the first transistor through the 1 st third transistor. The first port of the other third transistor may be controlled by a processor or controller, and the number of third transistors that are turned on and off may be determined empirically.
And a second port of any one fourth transistor in the j cascaded fourth transistors is connected with a low level VSS, wherein a first port of the 1 st fourth transistor is connected with a high level VDD. The first port of the 1 st fourth transistor is connected with high level, so that the 1 st fourth transistor is in a normally open state, and the power supply strength entering the second transistor is adjusted. When the 1 st fourth transistor is normally on, the low level connected to the second port of the 1 st fourth transistor enters the third port of the second transistor through the 1 st fourth transistor. The first ports of the other fourth transistors may be controlled by a processor or a controller, and the number of the turned-on and turned-off fourth transistors may be determined empirically to ensure the time length of the delay.
The third transistor in the top row can adjust the power supply strength from high level VDD to the first transistor, from VDD through the 1 st third transistor, through the inverse first transistor and to VOUTThe current flows to the ground capacitor to charge. The first port of the 1 st third transistor is normally connected to ground, that is, to a low level. The other third transistor is digitally controlled, so to speak by the processor, the number of control openings being determined by simulation data. When the current flowing to the grounding capacitor is large, the capacitor is charged quickly, the rising edge of the delay unit is delayed slightly, when the current is small, the capacitor is charged slowly, and the rising edge of the delay unit is delayed greatly. Similarly, the fourth transistor in the bottom row can adjust the delay of the falling edge of the delay unit, the 1 st fourth transistor is grounded and normally open, the other fourth transistors are controlled by a number, and the number of the controlled opening can be determined by simulation data.
Optionally, fig. 5 exemplarily shows a structure of any one of the N delay units 2041 and the second inverter 20412, in fig. 5, the second inverter 20412 includes a fifth transistor, a sixth transistor, p cascaded seventh transistors, and q cascaded eighth transistors, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor respectively include a first port, a second port, and a third port, and p and q are positive integers greater than 2.
A first port of the fifth transistor and a first port of the sixth transistor are respectively connected to the first input port of the second inverter 20412, a second port of the fifth transistor is connected to a third port of any seventh transistor of the p cascaded seventh transistors, and a third port of the fifth transistor and a third port of the sixth transistor are respectively connected to the output port of the second inverter 20412. The third port of the sixth transistor is connected to the third port of any eighth transistor of the q eighth transistors in the cascade. The second port of any one seventh transistor in the p cascaded seventh transistors is switched into high level, wherein the first port of the 1 st seventh transistor is switched into low level. The first port of the 1 st seventh transistor is connected with a low level, so that the 1 st seventh transistor is in a normally-on state, and the power supply strength entering the fifth transistor is adjusted. When the 1 st seventh transistor is normally on, a high level connected to the second port of the 1 st seventh transistor may enter the third port of the fifth transistor through the 1 st seventh transistor. The first port of the further seventh transistor may be controlled by a processor or controller and the number of seventh transistors that are switched on and off may be determined empirically.
And a second port of any eighth transistor in the q cascaded eighth transistors is connected with a low level VSS, wherein a first port of the 1 st eighth transistor is connected with a high level VDD. The first port of the 1 st eighth transistor is connected with a high level, so that the 1 st eighth transistor is in a normally-on state, and the power supply strength entering the sixth transistor is adjusted. When the 1 st eighth transistor is normally on, the low level connected to the second port of the 1 st eighth transistor enters the third port of the sixth transistor through the 1 st eighth transistor. The first ports of the other eighth transistors may be controlled by a processor or a controller, and the number of the eighth transistors to be turned on and off may be determined empirically to ensure the time length of the delay.
The uppermost row of seventh transistors can adjust the power supply strength from the high level VDD to the first transistor, from VDD, through the 1 st seventh transistor, through the anti-fifth transistor, and to VOUTThe current flows to the ground capacitor to charge. The first port of the 1 st seventh transistor is normally connected to the ground, that is, to a low level. The other seventh transistor is digitally controlled, so to speak by the processor, the number of control openings being determined by simulation data. When the current flowing to the grounding capacitor is large, the capacitor is charged quickly, the rising edge of the delay unit is delayed slightly, when the current is small, the capacitor is charged slowly, and the rising edge of the delay unit is delayed greatly. Similarly, the eighth transistor in the bottom row can adjust the delay of the falling edge of the delay unit, the 1 st eighth transistor is grounded and normally on, and the other eighth transistors are grounded and normally onThe transistors are digitally controlled and the amount of control turned on can be determined by simulation data.
Optionally, the first transistor, the third transistor, the fifth transistor, and the seventh transistor described in the above embodiments are P-type field effect transistors (also referred to as P-type Metal oxide semiconductors (PMOS)), and the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are N-type field effect transistors (also referred to as N-type Metal oxide semiconductors (NMOS)).
Optionally, in order to control the operation rate of the phase interpolator, the phase interpolator may further include a grounded capacitor 205, as shown in fig. 6. The output port of each delay unit 2041 is connected to the ground capacitor 205. The operation rate of the phase interpolator can be adjusted by shorting a capacitor at the output port of each delay unit 2041.
In the embodiment of the present invention, the phase interpolator may be applied in practice as follows: first all the PMOS and NMOS in the smoothing buffer of the phase interpolator are turned off to minimize the total delay. Then, a phase detector is used behind the smoothing buffer to determine whether the total delay is less than half a clock cycle, if the total delay is less than half a clock cycle, the number of closing the PMOS and the NMOS can be reduced to gradually increase the delay, namely, part of the PMOS and the NMOS are gradually opened until the phase detector informs that the total delay is greater than half a clock cycle, so that the linearity of the phase interpolator is improved by delaying and outputting signals transmitted in the data selector.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit and scope of the application. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.
Claims (6)
1. A phase interpolator, comprising: an input port, an output port, at least one data selector, and at least one smoothing buffer;
the input port of each data selector is connected with the input port of the phase interpolator, the input port of each smooth buffer is connected with the output port of one data selector, and the output port of each smooth buffer is connected with the output port of the phase interpolator;
the smoothing buffer comprises N delay units, wherein N is a positive integer greater than or equal to 2;
each delay unit comprises a first inverter and a second inverter, wherein a first input port of the first inverter of the kth delay unit is connected with an output port of the first inverter of the (k-1) th delay unit, a first input port of the second inverter of the kth delay unit is connected with an output port of the first inverter of the kth delay unit, and an output port of the second inverter of each delay unit is respectively connected with an output port of the phase interpolator; and the input port of the first inverter in the 1 st delay unit is connected with the output port of the corresponding data selector.
2. The phase interpolator of claim 1, wherein for any first inverter of the N delay cells, the first inverter comprises a first transistor, a second transistor, i third transistors in cascade, and j fourth transistors in cascade, the first transistor, the second transistor, the third transistor, and the fourth transistor respectively comprise a first port, a second port, and a third port;
a first port of the first transistor and a first port of the second transistor are connected with a first input port of the first inverter, a second port of the first transistor is connected with a third port of any third transistor in the cascaded i third transistors, and a third port of the first transistor and a third port of the second transistor are connected with an output port of the first inverter;
the second port of the second transistor is connected with the third port of any one of j fourth transistors in the cascade;
a second port of any one of the i cascaded third transistors is switched in a high level, wherein a first port of a 1 st third transistor is switched in a low level;
a second port of any one fourth transistor in the j cascaded fourth transistors is connected with a low level, wherein a first port of a 1 st fourth transistor is connected with a high level; wherein i and j are positive integers greater than 2.
3. The phase interpolator of claim 2, wherein said first transistor and said third transistor are P-type field effect transistors and said second transistor and said fourth transistor are N-type field effect transistors.
4. The phase interpolator of claim 1, wherein the second inverter comprises a fifth transistor, a sixth transistor, p seventh transistors in cascade, and q eighth transistors in cascade, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprising a first port, a second port, and a third port, respectively;
a first port of the fifth transistor and a first port of the sixth transistor are connected with a first input port of the second inverter, a second port of the fifth transistor is connected with a third port of any one seventh transistor in the cascaded p seventh transistors, and a third port of the fifth transistor and a third port of the sixth transistor are connected with an output port of the second inverter;
a third port of the sixth transistor is connected with a third port of any eighth transistor in the q cascaded eighth transistors;
a second port of any one seventh transistor in the p cascaded seventh transistors is connected with a high level, wherein a first port of a 1 st seventh transistor is connected with a low level;
and a second port of any eighth transistor in the q cascaded eighth transistors is switched into a low level, wherein a first port of a 1 st eighth transistor is switched into a high level, and p and q are positive integers greater than 2.
5. The phase interpolator of claim 4, wherein said fifth transistor and said seventh transistor are P-type field effect transistors and said sixth transistor and said eighth transistor are N-type field effect transistors.
6. The phase interpolator of any of claims 1 to 5, further comprising a capacitor connected to ground, wherein the output port of each of said delay cells is connected to said capacitor connected to ground.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412947A (en) * | 2002-10-30 | 2003-04-23 | 威盛电子股份有限公司 | Buffer capable of regulating work period and its operation method |
| CN101310440A (en) * | 2005-12-27 | 2008-11-19 | 英特尔公司 | Phase interpolator |
| CN102208908A (en) * | 2010-03-30 | 2011-10-05 | 台湾积体电路制造股份有限公司 | Static phase interpolator and clock and data recovery (CDR) circuits employing the same |
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| US9503066B2 (en) * | 2013-07-08 | 2016-11-22 | Micron Technology, Inc. | Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412947A (en) * | 2002-10-30 | 2003-04-23 | 威盛电子股份有限公司 | Buffer capable of regulating work period and its operation method |
| CN101310440A (en) * | 2005-12-27 | 2008-11-19 | 英特尔公司 | Phase interpolator |
| CN102208908A (en) * | 2010-03-30 | 2011-10-05 | 台湾积体电路制造股份有限公司 | Static phase interpolator and clock and data recovery (CDR) circuits employing the same |
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