CN109217849A - A kind of phase interpolator - Google Patents
A kind of phase interpolator Download PDFInfo
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- CN109217849A CN109217849A CN201710527949.0A CN201710527949A CN109217849A CN 109217849 A CN109217849 A CN 109217849A CN 201710527949 A CN201710527949 A CN 201710527949A CN 109217849 A CN109217849 A CN 109217849A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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Abstract
A kind of phase interpolator, the phase interpolator include input port and output port, at least one data selector and at least one smoothing buffer.The input port of each data selector is connect with the input port of phase interpolator respectively, the output port of each data selector is connected with the input port of corresponding smoothing buffer, and the output port of each smoothing buffer is connect with the output port of phase interpolator respectively.Smoothing buffer includes N number of delay unit.Each delay unit includes the first phase inverter and the second phase inverter.The signal obtained from data selector is delayed by N number of delay unit of smoothing buffer cascade and is exported by phase interpolator, the linearity of phase interpolator can be improved, the quantity of cascade delay unit is more, and delay time is longer.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of phase interpolators.
Background technique
Phase interpolator (phase interpolator, PI) is widely used in various circuits, such as wireless receiving and dispatching
Polar modulation circuit, phaselocked loop (phase locked loop, PLL), delay phase-locked loop (Delay-in machine
LockedLoop, DLL) and high-speed serial communication in clock data recovery circuit (clock data recovery, CDR), it is main
If being used to, interpolation synthesizes high-precision multichannel phase relation or as sampled clock signal, the linearity decides application circuit
Overall noise, therefore with high linearity phase interpolator become design key.
Phase interpolator is mainly realized by interpolation means, such as the voltage interpolation that can be realized with CMOS.It is general to insert
Value means are the phases to be misplaced using two neighboring 90 degree, are mixed with certain ratio, to obtain an intermediate phase.It is logical
Overregulate the position of the adjustable intermediate phase of ratio of mixing, realize from 0 degree to 90 degree arbitrary phase adjusting.If
Data selector is added before adjusting mixing to select 0 degree, 90 degree, 180 degree, 270 degree of two adjacent phases therein then may be used
With the arbitrary phase obtaining from 0 degree to 360 degree.
Since the influence of circuit interior power noise influences very big, often the first phase inverter delay on circuit final performance
Several picoseconds of shake can be generated by power supply noise, and delay line (delay line) and phase interpolator equivalent can be regarded as
The cascade of several first phase inverters.Compared with delay line, the complementary metal oxide semiconductor of phase interpolator
The cascade series of the Nverter circuit of (Complementary metal-oxide-semiconductor, CMOS) structure compared with
Few, strong to the rejection ability of power supply noise, phase adjustment range is wide.
But the phase interpolator of CMOS structure leads to phase interpolator because the gain of its CMOS reverser is very high
The linearity is not high, and precision is also poor, to influence the sampling to clock signal.
Summary of the invention
The embodiment of the present invention provides a kind of phase interpolator, and the linearity of phase interpolator can be improved.
In a first aspect, providing a kind of phase interpolator, comprising:
Input port and output port, at least one data selector and at least one smoothing buffer.Each data choosing
The input port for selecting device is connect with the input port of the phase interpolator respectively, the output port of each data selector with
The input port of corresponding smoothing buffer connects, the output port of each smoothing buffer respectively with the phase interpolator
Output port connection.The smoothing buffer includes N number of delay unit, and N is the positive integer more than or equal to 2.Each delay unit
Including the first phase inverter and the second phase inverter, the first input port of the first phase inverter of k-th of delay unit with kth -1
The output port of first phase inverter of delay unit connects, the first input end of the second phase inverter of k-th of delay unit
Mouth is connect with the output port of the first phase inverter of k-th of delay unit, the second phase inverter in each delay unit
Output port is connect with the output port of the phase interpolator respectively；Wherein, the first phase inverter in the 1st delay unit
Input port is connected with the output port of the corresponding data selector.
Phase interpolator is prolonged the signal obtained from data selector by N number of delay unit of smoothing buffer cascade
When export, the linearity of phase interpolator can be improved, the quantity of delay unit is more, and delay time is longer.
With reference to first aspect, in the first possible implementation of the first aspect, first phase inverter includes the
One transistor, second transistor, cascade i third transistor and cascade j the 4th transistor., the first transistor,
The second transistor, the third transistor and the 4th transistor respectively include first port, second port and third
Port.The first port of the first port of the first transistor and the second transistor respectively with first phase inverter
First input port connection, any third of the second port of the first transistor and the cascade i third transistor
The third port of transistor connects, the third port of the third port of the first transistor and the second transistor respectively with
The output port of first phase inverter connects.The second port of the second transistor and the cascade j the 4th crystal
The third port of any 4th transistor in pipe connects.Any third transistor of the cascade i third transistor
Second port accesses high level, wherein the first port of the 1st third transistor accesses low level.The cascade j the 4th
The second port of any 4th transistor of transistor accesses low level, wherein the first port access of the 1st the 4th transistor
High level；Wherein, i, j are the positive integer greater than 2.
The first phase inverter being made up of the first transistor, second transistor, third crystal and the 4th crystal, can make
By the reverse-phase output of the signal of data selector transmission, to realize the effect of delay.
With reference to first aspect or the first possible implementation of first aspect, second in first aspect are possible
In implementation, the first transistor and the third transistor be can be, but not limited to as p type field effect transistor, and described
Two-transistor and the 4th transistor can be, but not limited to as n type field effect transistor.
With reference to first aspect, in a third possible implementation of the first aspect, second phase inverter includes the
Five transistors, the 6th transistor, cascade p the 7th transistors and cascade q the 8th transistors., the 5th transistor,
6th transistor, the 7th transistor and the 8th transistor respectively include first port, second port and third
Port.The first port of 5th transistor and the first port of the 6th transistor respectively with second phase inverter
First input port connection, any 7th of the second port of the 5th transistor and the cascade p the 7th transistors the
The third port of transistor connects, the third port of the third port of the 5th transistor and the 6th transistor respectively with
The output port of second phase inverter connects.The third port of 6th transistor and the cascade q the 8th crystal
The third port of any 8th transistor in pipe connects.Any 7th transistor of the cascade p the 7th transistors
Second port accesses high level, wherein the first port of the 1st the 7th transistor accesses low level.The cascade q the 8th
The second port of any 8th transistor of transistor accesses low level, wherein the first port access of the 1st the 8th transistor
High level, wherein p, q are the positive integer greater than 2.
The second phase inverter being made up of the 5th transistor, the 6th transistor, the 7th crystal and the 8th crystal, can make
By the reverse-phase output of the signal of the first phase inverter transmission, it ensure that the phase of the signal of phase interpolator output and data are selected
The phase for selecting device output is identical, while the signal that can also export data selector realizes delay output.
With reference to first aspect or the third possible implementation of first aspect, the 4th kind in first aspect are possible
In implementation, the 5th transistor and the 7th transistor be can be, but not limited to as p type field effect transistor, and described
Six transistors and the 8th transistor can be, but not limited to as n type field effect transistor.
With reference to first aspect or the first possible implementation of first aspect is into the 4th kind of possible implementation
Any possible implementation further includes in the fifth possible implementation of the first aspect ground capacity, each described
The output port of delay unit is connect with the ground capacity respectively.Ground capacity can store the electric current of delay unit output,
Control the output speed of phase interpolator.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of system architecture provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of phase interpolator provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of smoothing buffer provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of phase inverter provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of phase inverter provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of phase interpolator provided in an embodiment of the present invention.
Specific embodiment
Fig. 1 shows a kind of system architecture that the embodiment of the present invention is applicable in, which includes phaselocked loop (phase
Locked loop, PLL), phase interpolator (phase interpolator, PI), finite state machine (finite state
Machine, FSM) and phase discriminator (phasedetector, PD).Within the system, PLL issues same phase (in-phase, I) and just
Hand over (quadrature, Q) two paths of signals to PI, by the clock of any phase between available 0 degree to 360 degree of PI
(clock, CKIQ) signal, the CKIQIt can participate in PD to data (Data, Din) sampling, sampled signal by FSM integrate
The phase controlling bit for generating PI afterwards, so that CKIQIt is maintained at D at any timeinCenter.
In the system architecture, PI mainly passes through interpolation means and synthesizes high-precision multichannel phase, the height of the linearity
The low sampled result that can influence clock signal.Based on this, the embodiment of the invention provides a kind of phase interpolators, such as Fig. 2 institute
The structure shown, the phase interpolator specifically include:
Input port 201, output port 202, at least one data selector 203 and at least one smoothing buffer 204.
Wherein, the input port of each data selector 203 is connect with the input port of the phase interpolator 201 respectively,
The output port of each data selector 203 is connected with the input port of corresponding smoothing buffer 204.One data selector
203 can be correspondingly connected with a smoothing buffer 204, multiple smoothing buffers 204 can also be correspondingly connected with, in practical application
When, based on the demand of the duration to delay, the quantity of the smoothing buffer 204 of selection connection can be carried out according to emulation.Each
The output port of smoothing buffer 204 is connect with the output port of phase interpolator 202 respectively.Smoothing buffer 204 includes N number of
Delay unit 2041, N are the positive integer more than or equal to 2.Phase interpolator can will be from by N number of cascade delay unit 2041
The delay output of signal obtained in data selector 203, so as to improve the linearity of phase interpolator.
In embodiments of the present invention, each delay unit 2041 includes the first phase inverter in above-mentioned N number of delay unit 2041
20411 and second phase inverter 20412.The signal that data selector 203 exports is by the first phase inverter in delay unit 2041
It is delayed after 20411 primary, is then delayed second by the second phase inverter 20412, and a signal is by reverse phase twice
Afterwards, the phase when phase of output signal and input is identical.For example, the phase of the signal of the first phase inverter 20411 input is 90
Degree, the phase of the signal after the first phase inverter 20411 is converted is 270 degree, using the conversion of the second phase inverter 20412
Afterwards, the phase of signal becomes 90 degree again.Equally, when the signal of the first phase inverter 20411 input is high level, output signal is
Low level, the signal exported after the second phase inverter 20412 become high level again, wherein the first phase inverter 20411 will be high electric
Flat turn be changed to low level process and the second phase inverter 20412 by high level be converted to it is low level during can all generate and prolong
When.Therefore, delay unit more than 2041, the delay that the signal that smoothing buffer 204 exports generates is longer, to realize signal
Delay output.
The signal obtained from data selector 203 will generate primary delay by the conversion of a phase inverter, that is,
A rising edge or failing edge are generated, the delay unit more than 2041 of connection, the rising edge or failing edge of generation are more, and phase is inserted
Rising edge or the failing edge for being worth the signal of device output are more smooth.When with signal output is indicated on figure, rising edge or failing edge
It can be expressed as protrusion, if rising edge or failing edge that individually one or two phase inverter generates can make the signal of output have
Jump, the linearity are bad.And when delay unit more than 2041, the rising edge or failing edge of generation are more, and protrusion is also more closely knit,
Protrusion may appear to more like smooth curve in this way, so as to improve the linearity of phase interpolator output.
Based on above structure, Fig. 3 illustratively shows a kind of knot of smoothing buffer 204 provided in an embodiment of the present invention
Structure, in Fig. 3, the first input port and -1 delay unit of kth of the first phase inverter 20411 of k-th of delay unit 2041
The output port of 2041 the first phase inverter 20411 connects, and the first of the second phase inverter 20412 of k-th of delay unit 2041
Input port is connect with the output port of the first phase inverter 20411 of k-th of delay unit 2041, in each delay unit 2041
The second phase inverter 20412 output port and phase interpolator output port 202 connect.Wherein, N number of delay unit 2041
In the 1st delay unit 2041 in the first phase inverter 20411 input port and the output of corresponding data selector 203
It is first defeated to be respectively connected to the 20412 of the second phase inverter for port connection, the first phase inverter 20411 of the 1st delay unit 2041
The first input port of first phase inverter 20411 of inbound port and the 2nd delay unit 2041,2≤k < N.Data selector
The signal of 203 outputs passes through the 1st delay unit after the first phase inverter 20411 of the 1st delay unit 2041 respectively
The first input port of 2041 the second phase inverter and the delay unit 2041 of subsequent cascaded, finally converge to phase interpolator
Output port 202 completes output.
The signal obtained from data selector is delayed by phase interpolator by the delay unit of smoothing buffer cascade
Output, can be improved the linearity of phase interpolator, the quantity of cascade delay unit is more, and delay time is longer.
Total delay of the optimal linearity in order to obtain, above-mentioned each cascade N number of delay unit will be half of clock cycle
Left and right, so the usable frequency of the smoothing buffer obtained using the delay unit of fixed quantity is relatively narrow.If smoothing buffer
It needs that wide range of frequencies is adjusted, then the structure in following figure 4 can be used to adjust third transistor and the 4th transistor
Intensity increase or decrease the delay of delay unit, make the length being always delayed close to half of clock cycle.
Optionally, Fig. 4 illustratively shows any one first phase inverter 20411 in above-mentioned N number of delay unit 2041
Structure, in Fig. 4, first phase inverter 20411 include the first transistor, second transistor, cascade i third transistor
With cascade j the 4th transistors, the first transistor, second transistor, third transistor and the 4th transistor respectively include the
Single port, second port and third port, i, j are the positive integer greater than 2.
It should be noted that the first port of each transistor described in embodiments of the present invention can be the grid of transistor
Pole, second port and third port can be source electrode or the drain electrode of transistor, if second port is source electrode, third port is
Drain electrode；If second port is drain electrode, third port is source electrode.
Wherein, the first port of the first transistor and the first port of second transistor respectively with the first phase inverter 20411
First input port connection, any third crystal in the second port of the first transistor and cascade i third transistor
The third port of pipe connects, the third port of the third port of the first transistor and second transistor respectively with the first phase inverter
20411 output port connection.Any 4th crystal in the second port of second transistor and cascade j the 4th transistors
The third port of pipe connects.The second port of any third transistor in cascade i third transistor accesses high level,
In, the first port of the 1st third transistor accesses low level.The first port access low level of 1st third transistor can
So that the 1st third transistor is in normally open, realize adjust enter the first transistor for electric strength.At the 1st
When third transistor is normally opened, the high level of second port access can enter the first crystalline substance by the 1st third transistor
The third port of body pipe.The first port of other third transistor can be controlled by processor or controller, can foundation
Experience determines the quantity of the third transistor of opening and closing.
The second port of any 4th transistor in cascade j the 4th transistors accesses low level VSS, wherein the 1st
The first port of a 4th transistor accesses high level VDD.The first port access high level of 1st the 4th transistor can make
The 1st the 4th transistor be in normally open, realize adjusting enter second transistor for electric strength.At the 1st the 4th
When transistor is normally opened, the low level of second port access enters the of second transistor by the 1st the 4th transistor
Three ports.The first port of other 4th transistors can be controlled by processor or controller, can empirically be come true
Surely the quantity of the 4th transistor opened and closed guarantees the time span of delay.
The one of the top arranges the 3rd transistor and high level VDD is adjusted to the first transistor for electric strength, adjusts from VDD
By the 1st third transistor, V is arrived again using anti-the first transistorOUTFlow to ground capacity charging.Wherein the 1st third crystalline substance
The first port ground connection of body pipe is normally opened, that is to say, that it is normally opened to connect low level.Other third transistor be by digital control, can be with
Say controlled by processor, controlling open quantity can be determined by emulation data.Flow to the electric current of ground capacity then capacitor greatly
Charging is fast, and the rising edge delay of delay unit is small, and the small then capacitor charging of electric current is slow, and the rising edge delay of delay unit is big.Similarly,
Bottom one arranges the delay that the failing edge of delay unit is adjusted in the 4th transistor, and the 1st the 4th transistor ground connection is normally opened, other
The 4th transistor by digital control, controlling open quantity can be determined by emulation data.
Optionally, Fig. 5 illustratively shows any one second phase inverter 20412 in above-mentioned N number of delay unit 2041
Structure, in Fig. 5, the second phase inverter 20412 include the 5th transistor, the 6th transistor, cascade p the 7th transistors and
Cascade q the 8th transistors, the 5th transistor, the 6th transistor, the 7th transistor and the 8th transistor respectively include first
Port, second port and third port, p, q are the positive integer greater than 2.
Wherein, the first port of the first port of the 5th transistor and the 6th transistor respectively with the second phase inverter 20412
First input port connection, any 7th crystal in the second port of the 5th transistor and cascade p the 7th transistors
The third port of pipe connects, the third port of the third port of the 5th transistor and the 6th transistor respectively with the second phase inverter
20412 output port connection.Any 8th crystal in the third port of 6th transistor and cascade q the 8th transistors
The third port of pipe connects.The second port of any 7th transistor in cascade p the 7th transistors accesses high level,
In, the first port of the 1st the 7th transistor accesses low level.The first port access low level of 1st the 7th transistor can
So that the 1st the 7th transistor is in normally open, realize adjust enter the 5th transistor for electric strength.At the 1st
When 7th transistor is normally opened, the high level of second port access can enter the 5th crystalline substance by the 1st the 7th transistor
The third port of body pipe.The first port of other 7th transistors can be controlled by processor or controller, can foundation
Experience determines the quantity of the 7th transistor of opening and closing.
The second port of any 8th transistor in cascade q the 8th transistors accesses low level VSS, wherein the 1st
The first port of a 8th transistor accesses high level VDD.The first port access high level of 1st the 8th transistor can make
The 1st the 8th transistor be in normally open, realize adjusting enter the 6th transistor for electric strength.At the 1st the 8th
When transistor is normally opened, the low level of second port access enters the of the 6th transistor by the 1st the 8th transistor
Three ports.The first port of other 8th transistors can be controlled by processor or controller, can empirically be come true
Surely the quantity of the 8th transistor opened and closed guarantees the time span of delay.
The one of the top arranges the 7th transistor and high level VDD is adjusted to the first transistor for electric strength, adjusts from VDD
By the 1st the 7th transistor, V is arrived again using anti-5th transistorOUTFlow to ground capacity charging.Wherein the 1st the 7th crystalline substance
The first port ground connection of body pipe is normally opened, that is to say, that it is normally opened to connect low level.Other 7th transistors be by digital control, can be with
Say controlled by processor, controlling open quantity can be determined by emulation data.Flow to the electric current of ground capacity then capacitor greatly
Charging is fast, and the rising edge delay of delay unit is small, and the small then capacitor charging of electric current is slow, and the rising edge delay of delay unit is big.Similarly,
Bottom one arranges the delay that the failing edge of delay unit is adjusted in the 8th transistor, and the 1st the 8th transistor ground connection is normally opened, other
The 8th transistor by digital control, controlling open quantity can be determined by emulation data.
Optionally, the first transistor, third transistor described in above-described embodiment, the 5th transistor and the 7th crystal
Pipe is p type field effect transistor, can also be referred to as P type metal oxide semiconductor (positive channel Metal
Oxide Semiconductor, PMOS), second transistor, the 4th transistor, the 6th transistor and the 8th transistor are N-type field
Effect transistor, also referred to as N-type metal-oxide semiconductor (MOS) (negative channel Metal Oxide
Semiconductor, NMOS).
Optionally, in order to control the operating rate of phase interpolator, as shown in fig. 6, the phase interpolator can be with
Including a ground capacity 205.The output port of each delay unit 2041 is connect with ground capacity 205 respectively.Prolong each
The operating rate of an adjustable phase interpolator of capacitor is shorted at the output port of Shi Danyuan 2041.
In embodiments of the present invention, above-mentioned phase interpolator can be in practical application are as follows: is first shut off phase interpolator
Smoothing buffer in all PMOS and NMOS, making always to be delayed reaches minimum.Then, phase discriminator is used behind smoothing buffer
Come determine total delay whether less than half clock cycle, if always less than half clock cycle of delay, can reduce closing
The quantity of PMOS and NMOS is delayed to gradually increase, that is, gradually opens part PMOS and NMOS, until phase discriminator notice is total
Until delay has been above half of clock cycle, to export by the way that the signal transmitted in data selector is delayed, phase is improved
The linearity of position interpolation device.
Obviously, those skilled in the art can carry out various modification and variations without departing from this Shen to the embodiment of the present invention
Spirit and scope please.In this way, if these modifications and variations of the embodiment of the present invention belong to the claim of this application and its wait
Within the scope of technology, then the application is also intended to include these modifications and variations.
Claims (6)
1. a kind of phase interpolator characterized by comprising input port, output port, at least one data selector and extremely
A few smoothing buffer；
The input port of each data selector is connect with the input port of the phase interpolator, each smoothing buffer it is defeated
Inbound port is connect with the output port of a data connector, the output port of each smoothing buffer and the phase interpolator
Output port connection；
The smoothing buffer includes N number of delay unit, and N is the positive integer more than or equal to 2；
Each delay unit includes the first phase inverter and the second phase inverter, and the first of the first phase inverter of k-th of delay unit is defeated
Inbound port is connect with the output port of first phase inverter of -1 delay unit of kth, and the second of k-th of delay unit is anti-
The first input port of phase device is connect with the output port of the first phase inverter of k-th of delay unit, each delay unit
In the output port of the second phase inverter connect respectively with the output port of the phase interpolator；Wherein, the 1st delay unit
In the output port of input port and the corresponding data selector of the first phase inverter connect.
2. phase interpolator as described in claim 1, which is characterized in that for any first in N number of delay unit
Phase inverter, first phase inverter include the first transistor, second transistor, cascade i third transistor and cascade j
4th transistor, the first transistor, the second transistor, the third transistor and the 4th transistor wrap respectively
Include first port, second port and third port；
The first of the first port and first phase inverter of the first port of the first transistor and the second transistor
Input port connection, the second port of the first transistor and any third in the cascade i third transistor are brilliant
The third port of body pipe connects, the third port of the third port of the first transistor and the second transistor and described the
The output port of one phase inverter connects；
The third of the second port of the second transistor and any 4th transistor in the cascade j the 4th transistors
Port connection；
The second port of any third transistor in the cascade i third transistor accesses high level, wherein the 1st
The first port of third transistor accesses low level；
The second port of any 4th transistor in the cascade j the 4th transistors accesses low level, wherein the 1st
The first port of 4th transistor accesses high level；Wherein, i, j are the positive integer greater than 2.
3. phase interpolator as claimed in claim 2, which is characterized in that the first transistor and the third transistor are
P type field effect transistor, the second transistor and the 4th transistor are n type field effect transistor.
4. phase interpolator as described in claim 1, which is characterized in that second phase inverter includes the 5th transistor, the
Six transistors, cascade p the 7th transistors and cascade q the 8th transistors, the 5th transistor, the 6th crystal
Pipe, the 7th transistor and the 8th transistor respectively include first port, second port and third port；
The first of the first port of 5th transistor and the first port of the 6th transistor and second phase inverter
Input port connection, the second port of the 5th transistor and any 7th in the cascade p the 7th transistors are brilliant
The third port of body pipe connects, the third port of the third port of the 5th transistor and the 6th transistor and described the
The output port of two phase inverters connects；
The third of the third port of 6th transistor and any 8th transistor in the cascade q the 8th transistors
Port connection；
The second port of any 7th transistor in the cascade p the 7th transistors accesses high level, wherein the 1st
The first port of 7th transistor accesses low level；
The second port of any 8th transistor in the cascade q the 8th transistors accesses low level, wherein the 1st
The first port of 8th transistor accesses high level, wherein p, q are the positive integer greater than 2.
5. phase interpolator as claimed in claim 4, which is characterized in that the 5th transistor and the 7th transistor are
P type field effect transistor, the 6th transistor and the 8th transistor are n type field effect transistor.
6. phase interpolator as claimed in claim 1 to 5, which is characterized in that it further include ground capacity, it is each described to prolong
The output port of Shi Danyuan is connect with the ground capacity.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110233611A (en) * | 2019-06-18 | 2019-09-13 | 苏州兆凯电子有限公司 | A kind of cascade phase interpolation method, circuit and a kind of clock data recovery circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233611A (en) * | 2019-06-18 | 2019-09-13 | 苏州兆凯电子有限公司 | A kind of cascade phase interpolation method, circuit and a kind of clock data recovery circuit |
| CN110233611B (en) * | 2019-06-18 | 2023-02-28 | 苏州兆凯电子有限公司 | Cascade phase interpolation method and circuit and clock data recovery circuit |
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| CN109217849B (en) | 2020-10-27 |
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